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Merge "Fix topology description of cpus for DynamIQ based FVP" into integration

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Mark Dykes 2020-02-14 19:12:44 +00:00 • committed by TrustedFirmware Code Review
commit 956059385c
4 changed files with 43 additions and 3 deletions
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2
fdts/fvp-base-gicv3-psci-common.dtsi
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@ -39,7 +39,7 @@
#address-cells = <2>; #address-cells = <2>;
#size-cells = <0>; #size-cells = <0>;
cpu-map { CPU_MAP:cpu-map {
cluster0 { cluster0 {
core0 { core0 {
cpu = <&CPU0>; cpu = <&CPU0>;

2
fdts/fvp-base-gicv3-psci-dynamiq-2t.dts
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@ -6,7 +6,7 @@
/dts-v1/; /dts-v1/;
#include "fvp-base-gicv3-psci-common.dtsi" #include "fvp-base-gicv3-psci-dynamiq-common.dtsi"
&CPU0 { &CPU0 {
reg = <0x0 0x0>; reg = <0x0 0x0>;

40
fdts/fvp-base-gicv3-psci-dynamiq-common.dtsi Normal file
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@ -0,0 +1,40 @@
/*
* Copyright (c) 2020, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
/dts-v1/;
#include "fvp-base-gicv3-psci-common.dtsi"
/* DynamIQ based designs have upto 8 CPUs in each cluster */
&CPU_MAP {
cluster0 {
core0 {
cpu = <&CPU0>;
};
core1 {
cpu = <&CPU1>;
};
core2 {
cpu = <&CPU2>;
};
core3 {
cpu = <&CPU3>;
};
core4 {
cpu = <&CPU4>;
};
core5 {
cpu = <&CPU5>;
};
core6 {
cpu = <&CPU6>;
};
core7 {
cpu = <&CPU7>;
};
};
};

2
fdts/fvp-base-gicv3-psci-dynamiq.dts
View file

@ -6,7 +6,7 @@
/dts-v1/; /dts-v1/;
#include "fvp-base-gicv3-psci-common.dtsi" #include "fvp-base-gicv3-psci-dynamiq-common.dtsi"
&CPU0 { &CPU0 {
reg = <0x0 0x0>; reg = <0x0 0x0>;