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refactor(neoverse-rd): define naming convention for RoS macros

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As part of the refactoring for the second generation platforms,
introduce a naming convention for macros within nrd_ros_def2.h and
nrd_ros_fw_def2.h.  All macros, except those related to page table
entries, must adhere to the format NRD_ROS_<name>. Page table entry
macros are handled separately and are not part of this patch.

Signed-off-by: Rohit Mathew <rohit.mathew@arm.com>
Change-Id: Ifcdc30b1c80b9848b793de2013095fc98d57bec6
This commit is contained in:
Rohit Mathew 2024-03-19 17:00:31 +00:00
parent 069bad718f
commit 947e78728e
3 changed files with 26 additions and 27 deletions
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20
plat/arm/board/neoverse_rd/common/include/nrd2/nrd_ros_def2.h
View file

@ -15,23 +15,23 @@
******************************************************************************/
/* System Reg */
#define CSS_SYSTEMREG_DEVICE_BASE UL(0x0C010000)
#define CSS_SYSTEMREG_DEVICE_SIZE UL(0x00010000)
#define NRD_ROS_SYSTEMREG_BASE UL(0x0C010000)
#define NRD_ROS_SYSTEMREG_SIZE UL(0x00010000)
/* NOR flash 2 */
#define CSS_NOR2_FLASH_DEVICE_BASE ULL(0x001054000000)
#define CSS_NOR2_FLASH_DEVICE_SIZE UL(0x000004000000)
#define NRD_ROS_NOR2_FLASH_BASE ULL(0x001054000000)
#define NRD_ROS_NOR2_FLASH_SIZE UL(0x000004000000)
/* Memory controller */
#define SOC_MEMCNTRL_BASE UL(0x10000000)
#define SOC_MEMCNTRL_SIZE UL(0x10000000)
#define NRD_ROS_MEMCNTRL_BASE UL(0x10000000)
#define NRD_ROS_MEMCNTRL_SIZE UL(0x10000000)
/* System peripherals */
#define SOC_SYSTEM_PERIPH_BASE UL(0x0C000000)
#define SOC_SYSTEM_PERIPH_SIZE UL(0x02000000)
#define NRD_ROS_SYSTEM_PERIPH_BASE UL(0x0C000000)
#define NRD_ROS_SYSTEM_PERIPH_SIZE UL(0x02000000)
/* Platform peripherals */
#define SOC_PLATFORM_PERIPH_BASE UL(0x0E000000)
#define SOC_PLATFORM_PERIPH_SIZE UL(0x02000000)
#define NRD_ROS_PLATFORM_PERIPH_BASE UL(0x0E000000)
#define NRD_ROS_PLATFORM_PERIPH_SIZE UL(0x02000000)
#endif /* NRD_ROS_DEF2_H */

27
plat/arm/board/neoverse_rd/common/include/nrd2/nrd_ros_fw_def2.h
View file

@ -19,42 +19,42 @@
#define NRD_ROS_PLATFORM_PERIPH_MMAP \
MAP_REGION_FLAT( \
SOC_PLATFORM_PERIPH_BASE, \
SOC_PLATFORM_PERIPH_SIZE, \
NRD_ROS_PLATFORM_PERIPH_BASE, \
NRD_ROS_PLATFORM_PERIPH_SIZE, \
MT_DEVICE | MT_RW | MT_SECURE)
#if SPM_MM
#define NRD_ROS_PLATFORM_PERIPH_USER_MMAP \
MAP_REGION_FLAT( \
SOC_PLATFORM_PERIPH_BASE, \
SOC_PLATFORM_PERIPH_SIZE, \
NRD_ROS_PLATFORM_PERIPH_BASE, \
NRD_ROS_PLATFORM_PERIPH_SIZE, \
MT_DEVICE | MT_RW | MT_SECURE | MT_USER)
#endif
#define NRD_ROS_SYSTEM_PERIPH_MMAP \
MAP_REGION_FLAT( \
SOC_SYSTEM_PERIPH_BASE, \
SOC_SYSTEM_PERIPH_SIZE, \
NRD_ROS_SYSTEM_PERIPH_BASE, \
NRD_ROS_SYSTEM_PERIPH_SIZE, \
MT_DEVICE | MT_RW | MT_SECURE)
#define NRD_ROS_MEMCNTRL_MMAP(n) \
MAP_REGION_FLAT( \
NRD_REMOTE_CHIP_MEM_OFFSET(n) + \
SOC_MEMCNTRL_BASE, \
SOC_MEMCNTRL_SIZE, \
NRD_ROS_MEMCNTRL_BASE, \
NRD_ROS_MEMCNTRL_SIZE, \
MT_DEVICE | MT_RW | MT_SECURE)
#define NRD_ROS_SECURE_SYSTEMREG_USER_MMAP \
MAP_REGION_FLAT( \
CSS_SYSTEMREG_DEVICE_BASE, \
CSS_SYSTEMREG_DEVICE_SIZE, \
NRD_ROS_SYSTEMREG_BASE, \
NRD_ROS_SYSTEMREG_SIZE, \
MT_DEVICE | MT_RW | MT_SECURE | MT_USER)
#define NRD_ROS_SECURE_NOR2_USER_MMAP \
MAP_REGION_FLAT( \
CSS_NOR2_FLASH_DEVICE_BASE, \
CSS_NOR2_FLASH_DEVICE_SIZE, \
NRD_ROS_NOR2_FLASH_BASE, \
NRD_ROS_NOR2_FLASH_SIZE, \
MT_DEVICE | MT_RW | MT_SECURE | MT_USER)
@ -64,7 +64,6 @@
V2M_FLASH0_SIZE, \
MT_DEVICE | MT_RO | MT_SECURE)
/*******************************************************************************
* TZ config
******************************************************************************/
@ -74,7 +73,7 @@
* where both the DRAM regions are marked for non-secure access. This applies
* to multi-chip platforms.
*/
#define NRD_PLAT_TZC_NS_REMOTE_REGIONS_DEF(n) \
#define NRD_ROS_TZC_NS_REMOTE_REGIONS_DEF(n) \
{NRD_REMOTE_CHIP_MEM_OFFSET(n) + ARM_DRAM1_BASE, \
NRD_REMOTE_CHIP_MEM_OFFSET(n) + ARM_DRAM1_END, \
ARM_TZC_NS_DRAM_S_ACCESS, PLAT_ARM_TZC_NS_DEV_ACCESS}, \

6
plat/arm/board/neoverse_rd/platform/rdn2/rdn2_security.c
View file

@ -25,20 +25,20 @@ static const arm_tzc_regions_info_t tzc_regions[] = {
static const arm_tzc_regions_info_t tzc_regions_mc[][NRD_CHIP_COUNT - 1] = {
{
/* TZC memory regions for second chip */
NRD_PLAT_TZC_NS_REMOTE_REGIONS_DEF(1),
NRD_ROS_TZC_NS_REMOTE_REGIONS_DEF(1),
{}
},
#if NRD_CHIP_COUNT > 2
{
/* TZC memory regions for third chip */
NRD_PLAT_TZC_NS_REMOTE_REGIONS_DEF(2),
NRD_ROS_TZC_NS_REMOTE_REGIONS_DEF(2),
{}
},
#endif
#if NRD_CHIP_COUNT > 3
{
/* TZC memory regions for fourth chip */
NRD_PLAT_TZC_NS_REMOTE_REGIONS_DEF(3),
NRD_ROS_TZC_NS_REMOTE_REGIONS_DEF(3),
{}
},
#endif