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refactor(cpufeat): rename ENABLE_SPE_FOR_LOWER_ELS to ENABLE_SPE_FOR_NS

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At the moment we hardcode the SPE functionality to be available on the
non-secure side only, by setting MDCR_EL2.E2PB accordingly.

This should be reflected in the feature selection symbol, so rename that
to ENABLE_SPE_FOR_NS, to make it clearer that SPE is not supported in
the secure world.

Change-Id: I3f9b48eab1a45d6ccfcbb9c90a11eeb66867ad9a
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
This commit is contained in:
Andre Przywara 2023-02-03 15:30:14 +00:00
parent 16e3ddba1f
commit 90118bb5c1
9 changed files with 11 additions and 11 deletions
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4
Makefile
View file

@ -1096,7 +1096,7 @@ $(eval $(call assert_booleans,\
ENABLE_RUNTIME_INSTRUMENTATION \ ENABLE_RUNTIME_INSTRUMENTATION \
ENABLE_SME_FOR_NS \ ENABLE_SME_FOR_NS \
ENABLE_SME_FOR_SWD \ ENABLE_SME_FOR_SWD \
ENABLE_SPE_FOR_LOWER_ELS \ ENABLE_SPE_FOR_NS \
ENABLE_SVE_FOR_NS \ ENABLE_SVE_FOR_NS \
ENABLE_SVE_FOR_SWD \ ENABLE_SVE_FOR_SWD \
ERROR_DEPRECATED \ ERROR_DEPRECATED \
@ -1237,7 +1237,7 @@ $(eval $(call add_defines,\
ENABLE_RUNTIME_INSTRUMENTATION \ ENABLE_RUNTIME_INSTRUMENTATION \
ENABLE_SME_FOR_NS \ ENABLE_SME_FOR_NS \
ENABLE_SME_FOR_SWD \ ENABLE_SME_FOR_SWD \
ENABLE_SPE_FOR_LOWER_ELS \ ENABLE_SPE_FOR_NS \
ENABLE_SVE_FOR_NS \ ENABLE_SVE_FOR_NS \
ENABLE_SVE_FOR_SWD \ ENABLE_SVE_FOR_SWD \
ENCRYPT_BL31 \ ENCRYPT_BL31 \

2
bl31/bl31.mk
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@ -87,7 +87,7 @@ BL31_SOURCES += services/std_svc/trng/trng_main.c \
services/std_svc/trng/trng_entropy_pool.c services/std_svc/trng/trng_entropy_pool.c
endif endif
ifeq (${ENABLE_SPE_FOR_LOWER_ELS},1) ifeq (${ENABLE_SPE_FOR_NS},1)
BL31_SOURCES += lib/extensions/spe/spe.c BL31_SOURCES += lib/extensions/spe/spe.c
endif endif

2
docs/getting_started/build-options.rst
View file

@ -428,7 +428,7 @@ Common build options
handle context switching for SME, SVE, and FPU/SIMD registers to ensure that handle context switching for SME, SVE, and FPU/SIMD registers to ensure that
no data is leaked to non-secure world. This is experimental. Default is 0. no data is leaked to non-secure world. This is experimental. Default is 0.
- ``ENABLE_SPE_FOR_LOWER_ELS`` : Boolean option to enable Statistical Profiling - ``ENABLE_SPE_FOR_NS`` : Boolean option to enable Statistical Profiling
extensions. This is an optional architectural feature for AArch64. extensions. This is an optional architectural feature for AArch64.
The default is 1 but is automatically disabled when the target architecture The default is 1 but is automatically disabled when the target architecture
is AArch32. is AArch32.

2
lib/el3_runtime/aarch64/context_mgmt.c
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@ -482,7 +482,7 @@ void cm_setup_context(cpu_context_t *ctx, const entry_point_info_t *ep)
static void manage_extensions_nonsecure(bool el2_unused, cpu_context_t *ctx) static void manage_extensions_nonsecure(bool el2_unused, cpu_context_t *ctx)
{ {
#if IMAGE_BL31 #if IMAGE_BL31
#if ENABLE_SPE_FOR_LOWER_ELS #if ENABLE_SPE_FOR_NS
spe_enable(el2_unused); spe_enable(el2_unused);
#endif #endif

4
make_helpers/defaults.mk
View file

@ -355,11 +355,11 @@ V := 0
WARMBOOT_ENABLE_DCACHE_EARLY := 0 WARMBOOT_ENABLE_DCACHE_EARLY := 0
# Build option to enable/disable the Statistical Profiling Extensions # Build option to enable/disable the Statistical Profiling Extensions
ENABLE_SPE_FOR_LOWER_ELS := 1 ENABLE_SPE_FOR_NS := 1
# SPE is only supported on AArch64 so disable it on AArch32. # SPE is only supported on AArch64 so disable it on AArch32.
ifeq (${ARCH},aarch32) ifeq (${ARCH},aarch32)
override ENABLE_SPE_FOR_LOWER_ELS := 0 override ENABLE_SPE_FOR_NS := 0
endif endif
# Include Memory Tagging Extension registers in cpu context. This must be set # Include Memory Tagging Extension registers in cpu context. This must be set

2
plat/allwinner/common/allwinner-common.mk
View file

@ -87,7 +87,7 @@ endif
COLD_BOOT_SINGLE_CPU := 1 COLD_BOOT_SINGLE_CPU := 1
# Do not enable SPE (not supported on ARM v8.0). # Do not enable SPE (not supported on ARM v8.0).
ENABLE_SPE_FOR_LOWER_ELS := 0 ENABLE_SPE_FOR_NS := 0
# Do not enable SVE (not supported on ARM v8.0). # Do not enable SVE (not supported on ARM v8.0).
ENABLE_SVE_FOR_NS := 0 ENABLE_SVE_FOR_NS := 0

2
plat/arm/board/fvp/fvp_pm.c
View file

@ -53,7 +53,7 @@ static void fvp_cluster_pwrdwn_common(void)
{ {
uint64_t mpidr = read_mpidr_el1(); uint64_t mpidr = read_mpidr_el1();
#if ENABLE_SPE_FOR_LOWER_ELS #if ENABLE_SPE_FOR_NS
/* /*
* On power down we need to disable statistical profiling extensions * On power down we need to disable statistical profiling extensions
* before exiting coherency. * before exiting coherency.

2
plat/arm/board/tc/platform.mk
View file

@ -161,7 +161,7 @@ override CTX_INCLUDE_AARCH32_REGS := 0
override CTX_INCLUDE_PAUTH_REGS := 1 override CTX_INCLUDE_PAUTH_REGS := 1
override ENABLE_SPE_FOR_LOWER_ELS := 0 override ENABLE_SPE_FOR_NS := 0
override ENABLE_AMU := 1 override ENABLE_AMU := 1
override ENABLE_AMU_AUXILIARY_COUNTERS := 1 override ENABLE_AMU_AUXILIARY_COUNTERS := 1

2
plat/qti/msm8916/platform.mk
View file

@ -44,7 +44,7 @@ WARMBOOT_ENABLE_DCACHE_EARLY := 1
# Disable features unsupported in ARMv8.0 # Disable features unsupported in ARMv8.0
ENABLE_AMU := 0 ENABLE_AMU := 0
ENABLE_SPE_FOR_LOWER_ELS := 0 ENABLE_SPE_FOR_NS := 0
ENABLE_SVE_FOR_NS := 0 ENABLE_SVE_FOR_NS := 0
# MSM8916 uses ARM Cortex-A53 r0p0 so likely all the errata apply # MSM8916 uses ARM Cortex-A53 r0p0 so likely all the errata apply