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refactor(fdts stm32mp1): move STM32MP DDR node

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Move the generic part of DDR node in SOC dtsi file.
DDR dtsi files only include the part configured by CubeMX tool.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@foss.st.com>
Change-Id: I8c211e9782604da32aeaab98d0ef75fb1cd9c58d
This commit is contained in:
Nicolas Le Bayon 2021-02-25 11:03:53 +01:00 • committed by Yann Gautier
parent e8a953a9b8
commit 8cafbda6d3
2 changed files with 133 additions and 141 deletions
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256
fdts/stm32mp15-ddr.dtsi
View file

@ -1,153 +1,127 @@
// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause // SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
/* /*
* Copyright (C) 2018, STMicroelectronics - All Rights Reserved * Copyright (C) 2018-2021, STMicroelectronics - All Rights Reserved
*/ */
/ { &ddr {
soc { st,mem-name = DDR_MEM_NAME;
ddr: ddr@5a003000{ st,mem-speed = <DDR_MEM_SPEED>;
st,mem-size = <DDR_MEM_SIZE>;
compatible = "st,stm32mp1-ddr"; st,ctl-reg = <
DDR_MSTR
DDR_MRCTRL0
DDR_MRCTRL1
DDR_DERATEEN
DDR_DERATEINT
DDR_PWRCTL
DDR_PWRTMG
DDR_HWLPCTL
DDR_RFSHCTL0
DDR_RFSHCTL3
DDR_CRCPARCTL0
DDR_ZQCTL0
DDR_DFITMG0
DDR_DFITMG1
DDR_DFILPCFG0
DDR_DFIUPD0
DDR_DFIUPD1
DDR_DFIUPD2
DDR_DFIPHYMSTR
DDR_ODTMAP
DDR_DBG0
DDR_DBG1
DDR_DBGCMD
DDR_POISONCFG
DDR_PCCFG
>;
reg = <0x5A003000 0x550 st,ctl-timing = <
0x5A004000 0x234>; DDR_RFSHTMG
DDR_DRAMTMG0
DDR_DRAMTMG1
DDR_DRAMTMG2
DDR_DRAMTMG3
DDR_DRAMTMG4
DDR_DRAMTMG5
DDR_DRAMTMG6
DDR_DRAMTMG7
DDR_DRAMTMG8
DDR_DRAMTMG14
DDR_ODTCFG
>;
clocks = <&rcc AXIDCG>, st,ctl-map = <
<&rcc DDRC1>, DDR_ADDRMAP1
<&rcc DDRC2>, DDR_ADDRMAP2
<&rcc DDRPHYC>, DDR_ADDRMAP3
<&rcc DDRCAPB>, DDR_ADDRMAP4
<&rcc DDRPHYCAPB>; DDR_ADDRMAP5
DDR_ADDRMAP6
DDR_ADDRMAP9
DDR_ADDRMAP10
DDR_ADDRMAP11
>;
clock-names = "axidcg", st,ctl-perf = <
"ddrc1", DDR_SCHED
"ddrc2", DDR_SCHED1
"ddrphyc", DDR_PERFHPR1
"ddrcapb", DDR_PERFLPR1
"ddrphycapb"; DDR_PERFWR1
DDR_PCFGR_0
DDR_PCFGW_0
DDR_PCFGQOS0_0
DDR_PCFGQOS1_0
DDR_PCFGWQOS0_0
DDR_PCFGWQOS1_0
DDR_PCFGR_1
DDR_PCFGW_1
DDR_PCFGQOS0_1
DDR_PCFGQOS1_1
DDR_PCFGWQOS0_1
DDR_PCFGWQOS1_1
>;
st,mem-name = DDR_MEM_NAME; st,phy-reg = <
st,mem-speed = <DDR_MEM_SPEED>; DDR_PGCR
st,mem-size = <DDR_MEM_SIZE>; DDR_ACIOCR
DDR_DXCCR
DDR_DSGCR
DDR_DCR
DDR_ODTCR
DDR_ZQ0CR1
DDR_DX0GCR
DDR_DX1GCR
DDR_DX2GCR
DDR_DX3GCR
>;
st,ctl-reg = < st,phy-timing = <
DDR_MSTR DDR_PTR0
DDR_MRCTRL0 DDR_PTR1
DDR_MRCTRL1 DDR_PTR2
DDR_DERATEEN DDR_DTPR0
DDR_DERATEINT DDR_DTPR1
DDR_PWRCTL DDR_DTPR2
DDR_PWRTMG DDR_MR0
DDR_HWLPCTL DDR_MR1
DDR_RFSHCTL0 DDR_MR2
DDR_RFSHCTL3 DDR_MR3
DDR_CRCPARCTL0 >;
DDR_ZQCTL0
DDR_DFITMG0
DDR_DFITMG1
DDR_DFILPCFG0
DDR_DFIUPD0
DDR_DFIUPD1
DDR_DFIUPD2
DDR_DFIPHYMSTR
DDR_ODTMAP
DDR_DBG0
DDR_DBG1
DDR_DBGCMD
DDR_POISONCFG
DDR_PCCFG
>;
st,ctl-timing = < st,phy-cal = <
DDR_RFSHTMG DDR_DX0DLLCR
DDR_DRAMTMG0 DDR_DX0DQTR
DDR_DRAMTMG1 DDR_DX0DQSTR
DDR_DRAMTMG2 DDR_DX1DLLCR
DDR_DRAMTMG3 DDR_DX1DQTR
DDR_DRAMTMG4 DDR_DX1DQSTR
DDR_DRAMTMG5 DDR_DX2DLLCR
DDR_DRAMTMG6 DDR_DX2DQTR
DDR_DRAMTMG7 DDR_DX2DQSTR
DDR_DRAMTMG8 DDR_DX3DLLCR
DDR_DRAMTMG14 DDR_DX3DQTR
DDR_ODTCFG DDR_DX3DQSTR
>; >;
st,ctl-map = <
DDR_ADDRMAP1
DDR_ADDRMAP2
DDR_ADDRMAP3
DDR_ADDRMAP4
DDR_ADDRMAP5
DDR_ADDRMAP6
DDR_ADDRMAP9
DDR_ADDRMAP10
DDR_ADDRMAP11
>;
st,ctl-perf = <
DDR_SCHED
DDR_SCHED1
DDR_PERFHPR1
DDR_PERFLPR1
DDR_PERFWR1
DDR_PCFGR_0
DDR_PCFGW_0
DDR_PCFGQOS0_0
DDR_PCFGQOS1_0
DDR_PCFGWQOS0_0
DDR_PCFGWQOS1_0
DDR_PCFGR_1
DDR_PCFGW_1
DDR_PCFGQOS0_1
DDR_PCFGQOS1_1
DDR_PCFGWQOS0_1
DDR_PCFGWQOS1_1
>;
st,phy-reg = <
DDR_PGCR
DDR_ACIOCR
DDR_DXCCR
DDR_DSGCR
DDR_DCR
DDR_ODTCR
DDR_ZQ0CR1
DDR_DX0GCR
DDR_DX1GCR
DDR_DX2GCR
DDR_DX3GCR
>;
st,phy-timing = <
DDR_PTR0
DDR_PTR1
DDR_PTR2
DDR_DTPR0
DDR_DTPR1
DDR_DTPR2
DDR_MR0
DDR_MR1
DDR_MR2
DDR_MR3
>;
st,phy-cal = <
DDR_DX0DLLCR
DDR_DX0DQTR
DDR_DX0DQSTR
DDR_DX1DLLCR
DDR_DX1DQTR
DDR_DX1DQSTR
DDR_DX2DLLCR
DDR_DX2DQTR
DDR_DX2DQSTR
DDR_DX3DLLCR
DDR_DX3DQTR
DDR_DX3DQSTR
>;
status = "okay";
};
};
}; };

18
fdts/stm32mp151.dtsi
View file

@ -358,6 +358,24 @@
status = "disabled"; status = "disabled";
}; };
ddr: ddr@5a003000{
compatible = "st,stm32mp1-ddr";
reg = <0x5A003000 0x550 0x5A004000 0x234>;
clocks = <&rcc AXIDCG>,
<&rcc DDRC1>,
<&rcc DDRC2>,
<&rcc DDRPHYC>,
<&rcc DDRCAPB>,
<&rcc DDRPHYCAPB>;
clock-names = "axidcg",
"ddrc1",
"ddrc2",
"ddrphyc",
"ddrcapb",
"ddrphycapb";
status = "okay";
};
usbphyc: usbphyc@5a006000 { usbphyc: usbphyc@5a006000 {
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;