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feat(tc): configure UART for TC4 FPGA

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TC4 FPGA have a UART clock of 4000000 so modify the value
of TC_UARTCLK for TC4.

Change-Id: I8de84d58bce8b7277bf356136a5185c008ab4c28
Signed-off-by: Jagdish Gediya <jagdish.gediya@arm.com>
Signed-off-by: Icen.Zeyada <Icen.Zeyada2@arm.com>
This commit is contained in:
Jagdish Gediya 2024-06-28 11:22:37 +00:00 • committed by Icen.Zeyada
parent 79e11f5654
commit 84ca47a8ac
1 changed files with 5 additions and 2 deletions
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7
plat/arm/board/tc/include/platform_def.h
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@ -448,9 +448,12 @@
#if TARGET_PLATFORM <= 2
#define TC_UARTCLK 5000000
#elif TARGET_PLATFORM >= 3
#elif TARGET_PLATFORM == 3
#define TC_UARTCLK 3750000
#endif /* TARGET_PLATFORM >= 3 */
#elif TARGET_PLATFORM == 4
#define TC_UARTCLK 4000000
#endif /* TARGET_PLATFORM <=2 */
#if TARGET_FLAVOUR_FVP
#define PLAT_ARM_BOOT_UART_BASE TC_UART1