From 84ca47a8ac03821cfd4dbe902c0ae71621e2f12f Mon Sep 17 00:00:00 2001 From: Jagdish Gediya Date: Fri, 28 Jun 2024 11:22:37 +0000 Subject: [PATCH] feat(tc): configure UART for TC4 FPGA TC4 FPGA have a UART clock of 4000000 so modify the value of TC_UARTCLK for TC4. Change-Id: I8de84d58bce8b7277bf356136a5185c008ab4c28 Signed-off-by: Jagdish Gediya Signed-off-by: Icen.Zeyada --- plat/arm/board/tc/include/platform_def.h | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/plat/arm/board/tc/include/platform_def.h b/plat/arm/board/tc/include/platform_def.h index ff7940244..c6bcf454a 100644 --- a/plat/arm/board/tc/include/platform_def.h +++ b/plat/arm/board/tc/include/platform_def.h @@ -448,9 +448,12 @@ #if TARGET_PLATFORM <= 2 #define TC_UARTCLK 5000000 -#elif TARGET_PLATFORM >= 3 +#elif TARGET_PLATFORM == 3 #define TC_UARTCLK 3750000 -#endif /* TARGET_PLATFORM >= 3 */ +#elif TARGET_PLATFORM == 4 +#define TC_UARTCLK 4000000 +#endif /* TARGET_PLATFORM <=2 */ + #if TARGET_FLAVOUR_FVP #define PLAT_ARM_BOOT_UART_BASE TC_UART1