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Apply variant 4 mitigation for Neoverse N1

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This patch applies the new MSR instruction to directly set the
PSTATE.SSBS bit which controls speculative loads. This new instruction
is available at Neoverse N1 core so it's utilised.

Change-Id: Iee18a8b042c90fdb72d2b98f364dcfbb17510728
Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>
This commit is contained in:
John Tsichritzis 2019-03-04 16:41:26 +00:00
parent 620d9832f9
commit 8074448f09
2 changed files with 9 additions and 0 deletions
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5
include/arch/aarch64/arch.h
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@ -843,4 +843,9 @@
#define DIT S3_3_C4_C2_5 #define DIT S3_3_C4_C2_5
#define DIT_BIT BIT(24) #define DIT_BIT BIT(24)
/*******************************************************************************
* Armv8.5 - new MSR encoding to directly access PSTATE.SSBS field
******************************************************************************/
#define SSBS S3_3_C4_C2_6
#endif /* ARCH_H */ #endif /* ARCH_H */

4
lib/cpus/aarch64/neoverse_n1.S
View file

@ -46,6 +46,10 @@ endfunc check_errata_1043202
func neoverse_n1_reset_func func neoverse_n1_reset_func
mov x19, x30 mov x19, x30
/* Disables speculative loads */
msr SSBS, xzr
bl cpu_get_rev_var bl cpu_get_rev_var
mov x18, x0 mov x18, x0