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https://github.com/ARM-software/arm-trusted-firmware.git
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8074448f09
This patch applies the new MSR instruction to directly set the PSTATE.SSBS bit which controls speculative loads. This new instruction is available at Neoverse N1 core so it's utilised. Change-Id: Iee18a8b042c90fdb72d2b98f364dcfbb17510728 Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>
140 lines
3.3 KiB
ArmAsm
140 lines
3.3 KiB
ArmAsm
/*
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* Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <arch.h>
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#include <asm_macros.S>
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#include <neoverse_n1.h>
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#include <cpuamu.h>
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#include <cpu_macros.S>
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/* --------------------------------------------------
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* Errata Workaround for Neoverse N1 Errata
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* This applies to revision r0p0 and r1p0 of Neoverse N1.
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* Inputs:
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* x0: variant[4:7] and revision[0:3] of current cpu.
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* Shall clobber: x0-x17
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* --------------------------------------------------
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*/
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func errata_n1_1043202_wa
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/* Compare x0 against revision r1p0 */
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mov x17, x30
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bl check_errata_1043202
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cbz x0, 1f
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/* Apply instruction patching sequence */
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ldr x0, =0x0
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msr CPUPSELR_EL3, x0
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ldr x0, =0xF3BF8F2F
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msr CPUPOR_EL3, x0
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ldr x0, =0xFFFFFFFF
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msr CPUPMR_EL3, x0
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ldr x0, =0x800200071
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msr CPUPCR_EL3, x0
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isb
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1:
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ret x17
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endfunc errata_n1_1043202_wa
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func check_errata_1043202
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/* Applies to r0p0 and r1p0 */
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mov x1, #0x10
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b cpu_rev_var_ls
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endfunc check_errata_1043202
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func neoverse_n1_reset_func
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mov x19, x30
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/* Disables speculative loads */
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msr SSBS, xzr
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bl cpu_get_rev_var
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mov x18, x0
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#if ERRATA_N1_1043202
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mov x0, x18
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bl errata_n1_1043202_wa
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#endif
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#if ENABLE_AMU
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/* Make sure accesses from EL0/EL1 and EL2 are not trapped to EL3 */
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mrs x0, actlr_el3
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orr x0, x0, #NEOVERSE_N1_ACTLR_AMEN_BIT
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msr actlr_el3, x0
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isb
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/* Make sure accesses from EL0/EL1 are not trapped to EL2 */
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mrs x0, actlr_el2
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orr x0, x0, #NEOVERSE_N1_ACTLR_AMEN_BIT
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msr actlr_el2, x0
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isb
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/* Enable group0 counters */
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mov x0, #NEOVERSE_N1_AMU_GROUP0_MASK
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msr CPUAMCNTENSET_EL0, x0
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isb
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#endif
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ret x19
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endfunc neoverse_n1_reset_func
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/* ---------------------------------------------
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* HW will do the cache maintenance while powering down
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* ---------------------------------------------
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*/
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func neoverse_n1_core_pwr_dwn
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/* ---------------------------------------------
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* Enable CPU power down bit in power control register
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* ---------------------------------------------
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*/
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mrs x0, NEOVERSE_N1_CPUPWRCTLR_EL1
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orr x0, x0, #NEOVERSE_N1_CORE_PWRDN_EN_MASK
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msr NEOVERSE_N1_CPUPWRCTLR_EL1, x0
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isb
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ret
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endfunc neoverse_n1_core_pwr_dwn
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#if REPORT_ERRATA
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/*
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* Errata printing function for Neoverse N1. Must follow AAPCS.
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*/
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func neoverse_n1_errata_report
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stp x8, x30, [sp, #-16]!
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bl cpu_get_rev_var
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mov x8, x0
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/*
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* Report all errata. The revision-variant information is passed to
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* checking functions of each errata.
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*/
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report_errata ERRATA_N1_1043202, neoverse_n1, 1043202
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ldp x8, x30, [sp], #16
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ret
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endfunc neoverse_n1_errata_report
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#endif
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/* ---------------------------------------------
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* This function provides neoverse_n1 specific
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* register information for crash reporting.
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* It needs to return with x6 pointing to
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* a list of register names in ascii and
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* x8 - x15 having values of registers to be
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* reported.
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* ---------------------------------------------
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*/
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.section .rodata.neoverse_n1_regs, "aS"
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neoverse_n1_regs: /* The ascii list of register names to be reported */
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.asciz "cpuectlr_el1", ""
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func neoverse_n1_cpu_reg_dump
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adr x6, neoverse_n1_regs
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mrs x8, NEOVERSE_N1_CPUECTLR_EL1
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ret
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endfunc neoverse_n1_cpu_reg_dump
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declare_cpu_ops neoverse_n1, NEOVERSE_N1_MIDR, \
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neoverse_n1_reset_func, \
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neoverse_n1_core_pwr_dwn
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