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fix(tc): enable Last-level cache (LLC) for tc4

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EXTLLC bit in CPUECTLR_EL1(for non-gelas cpus) and in CPUECTLR2_EL1
register for gelas cpu enables external Last-level cache in the system,

External LLC is present on TC4 systems in MCN but it is not enabled in
CPU registers so enable it.

On TC4, Gelas vs Non-Gelas CPUs have different bits to enable EXTLLC
so take care of that as well.

Change-Id: Ic6a74b4af110a3c34d19131676e51901ea2bf6e3
Signed-off-by: Jagdish Gediya <jagdish.gediya@arm.com>
Signed-off-by: Icen.Zeyada <Icen.Zeyada2@arm.com>
This commit is contained in:
Jagdish Gediya 2024-07-05 11:15:15 +00:00 • committed by Icen.Zeyada
parent 001f22cdd4
commit 7b41acaf72
2 changed files with 9 additions and 2 deletions
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1
include/lib/cpus/aarch64/cortex_gelas.h
View file

@ -15,6 +15,7 @@
* CPU Extended Control register specific definitions
******************************************************************************/
#define CORTEX_GELAS_IMP_CPUECTLR_EL1 S3_0_C15_C1_5
#define CPUECTLR2_EL1_EXTLLC_BIT 10
/*******************************************************************************
* CPU Power Control register specific definitions

10
plat/arm/board/tc/include/tc_helpers.S
View file

@ -9,6 +9,8 @@
#include <platform_def.h>
#include <cpu_macros.S>
#include <cortex_gelas.h>
#define TC_HANDLER(rev) plat_reset_handler_tc##rev
#define PLAT_RESET_HANDLER(rev) TC_HANDLER(rev)
@ -57,8 +59,11 @@ func mark_extllc_presence
mov_imm x0, (MCN_CONFIG_ADDR(0))
ldr w1, [x0]
ubfx x1, x1, #MCN_CONFIG_SLC_PRESENT_BIT, #1
sysreg_bitfield_insert_from_gpr CPUECTLR_EL1, x1, \
CPUECTLR_EL1_EXTLLC_BIT, 1
jump_if_cpu_midr CORTEX_GELAS_MIDR, GELAS
sysreg_bitfield_insert_from_gpr CPUECTLR_EL1, x1, CPUECTLR_EL1_EXTLLC_BIT, 1
ret
GELAS:
sysreg_bitfield_insert_from_gpr CORTEX_GELAS_IMP_CPUECTLR_EL1, x1, CPUECTLR2_EL1_EXTLLC_BIT, 1
#endif
ret
endfunc mark_extllc_presence
@ -83,6 +88,7 @@ endfunc TC_HANDLER(3)
func TC_HANDLER(4)
mov x9, lr
bl mark_extllc_presence
bl enable_dsu_pmu_el1_access
mov lr, x9
ret