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feat(st-ddr): add STM32MP2 driver
Add driver to support DDR on STM32MP2 platform. It drives the DDR PHY and its firmware, as well as the DDR controller. Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com> Signed-off-by: Maxime Méré <maxime.mere@foss.st.com> Change-Id: I93de2db1b9378d5654e76b3bf6f3407d80bc4ca5
This commit is contained in:
Nicolas Le Bayon
Maxime Méré
parent
d596023bff
commit
79629b1a79
41 changed files with 18361 additions and 31 deletions
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@ -4,12 +4,524 @@
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <errno.h>
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#include <arch_helpers.h>
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#include <common/debug.h>
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#include <drivers/delay_timer.h>
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#include <drivers/st/stm32mp2_ddr.h>
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#include <drivers/st/stm32mp2_ddr_helpers.h>
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#include <drivers/st/stm32mp2_ddr_regs.h>
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#include <drivers/st/stm32mp_ddr.h>
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#include <lib/mmio.h>
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#include <platform_def.h>
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/* HW idle period (unit: Multiples of 32 DFI clock cycles) */
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#define HW_IDLE_PERIOD 0x3U
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static enum stm32mp2_ddr_sr_mode saved_ddr_sr_mode;
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#pragma weak stm32_ddrdbg_get_base
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uintptr_t stm32_ddrdbg_get_base(void)
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{
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return 0U;
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}
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static void set_qd1_qd3_update_conditions(struct stm32mp_ddrctl *ctl)
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{
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mmio_setbits_32((uintptr_t)&ctl->dbg1, DDRCTRL_DBG1_DIS_DQ);
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stm32mp_ddr_set_qd3_update_conditions(ctl);
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}
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static void unset_qd1_qd3_update_conditions(struct stm32mp_ddrctl *ctl)
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{
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stm32mp_ddr_unset_qd3_update_conditions(ctl);
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mmio_clrbits_32((uintptr_t)&ctl->dbg1, DDRCTRL_DBG1_DIS_DQ);
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}
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static void wait_dfi_init_complete(struct stm32mp_ddrctl *ctl)
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{
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uint64_t timeout;
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uint32_t dfistat;
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timeout = timeout_init_us(DDR_TIMEOUT_US_1S);
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do {
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dfistat = mmio_read_32((uintptr_t)&ctl->dfistat);
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VERBOSE("[0x%lx] dfistat = 0x%x ", (uintptr_t)&ctl->dfistat, dfistat);
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if (timeout_elapsed(timeout)) {
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panic();
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}
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} while ((dfistat & DDRCTRL_DFISTAT_DFI_INIT_COMPLETE) == 0U);
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VERBOSE("[0x%lx] dfistat = 0x%x\n", (uintptr_t)&ctl->dfistat, dfistat);
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}
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static void disable_dfi_low_power_interface(struct stm32mp_ddrctl *ctl)
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{
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uint64_t timeout;
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uint32_t dfistat;
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uint32_t stat;
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mmio_clrbits_32((uintptr_t)&ctl->dfilpcfg0, DDRCTRL_DFILPCFG0_DFI_LP_EN_SR);
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timeout = timeout_init_us(DDR_TIMEOUT_US_1S);
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do {
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dfistat = mmio_read_32((uintptr_t)&ctl->dfistat);
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stat = mmio_read_32((uintptr_t)&ctl->stat);
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VERBOSE("[0x%lx] dfistat = 0x%x ", (uintptr_t)&ctl->dfistat, dfistat);
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VERBOSE("[0x%lx] stat = 0x%x ", (uintptr_t)&ctl->stat, stat);
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if (timeout_elapsed(timeout)) {
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panic();
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}
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} while (((dfistat & DDRCTRL_DFISTAT_DFI_LP_ACK) != 0U) ||
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((stat & DDRCTRL_STAT_OPERATING_MODE_MASK) == DDRCTRL_STAT_OPERATING_MODE_SR));
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VERBOSE("[0x%lx] dfistat = 0x%x\n", (uintptr_t)&ctl->dfistat, dfistat);
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VERBOSE("[0x%lx] stat = 0x%x\n", (uintptr_t)&ctl->stat, stat);
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}
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void ddr_activate_controller(struct stm32mp_ddrctl *ctl, bool sr_entry)
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{
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/*
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* Manage quasi-dynamic registers modification
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* dfimisc.dfi_frequency : Group 1
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* dfimisc.dfi_init_complete_en and dfimisc.dfi_init_start : Group 3
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*/
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set_qd1_qd3_update_conditions(ctl);
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if (sr_entry) {
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mmio_setbits_32((uintptr_t)&ctl->dfimisc, DDRCTRL_DFIMISC_DFI_FREQUENCY);
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} else {
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mmio_clrbits_32((uintptr_t)&ctl->dfimisc, DDRCTRL_DFIMISC_DFI_FREQUENCY);
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}
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mmio_setbits_32((uintptr_t)&ctl->dfimisc, DDRCTRL_DFIMISC_DFI_INIT_START);
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mmio_clrbits_32((uintptr_t)&ctl->dfimisc, DDRCTRL_DFIMISC_DFI_INIT_START);
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wait_dfi_init_complete(ctl);
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udelay(DDR_DELAY_1US);
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if (sr_entry) {
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mmio_clrbits_32((uintptr_t)&ctl->dfimisc, DDRCTRL_DFIMISC_DFI_INIT_COMPLETE_EN);
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} else {
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mmio_setbits_32((uintptr_t)&ctl->dfimisc, DDRCTRL_DFIMISC_DFI_INIT_COMPLETE_EN);
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}
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udelay(DDR_DELAY_1US);
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unset_qd1_qd3_update_conditions(ctl);
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}
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#if STM32MP_LPDDR4_TYPE
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static void disable_phy_ddc(void)
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{
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/* Enable APB access to internal CSR registers */
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mmio_write_32(stm32mp_ddrphyc_base() + DDRPHY_APBONLY0_MICROCONTMUXSEL, 0U);
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mmio_write_32(stm32mp_ddrphyc_base() + DDRPHY_DRTUB0_UCCLKHCLKENABLES,
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DDRPHY_DRTUB0_UCCLKHCLKENABLES_UCCLKEN |
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DDRPHY_DRTUB0_UCCLKHCLKENABLES_HCLKEN);
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/* Disable DRAM drift compensation */
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mmio_write_32(stm32mp_ddrphyc_base() + DDRPHY_INITENG0_P0_SEQ0BDISABLEFLAG6, 0xFFFFU);
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/* Disable APB access to internal CSR registers */
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mmio_write_32(stm32mp_ddrphyc_base() + DDRPHY_DRTUB0_UCCLKHCLKENABLES,
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DDRPHY_DRTUB0_UCCLKHCLKENABLES_HCLKEN);
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mmio_write_32(stm32mp_ddrphyc_base() + DDRPHY_APBONLY0_MICROCONTMUXSEL,
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DDRPHY_APBONLY0_MICROCONTMUXSEL_MICROCONTMUXSEL);
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}
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#endif /* STM32MP_LPDDR4_TYPE */
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void ddr_wait_lp3_mode(bool sr_entry)
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{
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uint64_t timeout;
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bool repeat_loop = false;
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/* Enable APB access to internal CSR registers */
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mmio_write_32(stm32mp_ddrphyc_base() + DDRPHY_APBONLY0_MICROCONTMUXSEL, 0U);
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mmio_write_32(stm32mp_ddrphyc_base() + DDRPHY_DRTUB0_UCCLKHCLKENABLES,
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DDRPHY_DRTUB0_UCCLKHCLKENABLES_UCCLKEN |
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DDRPHY_DRTUB0_UCCLKHCLKENABLES_HCLKEN);
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timeout = timeout_init_us(DDR_TIMEOUT_US_1S);
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do {
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uint16_t phyinlpx = mmio_read_32(stm32mp_ddrphyc_base() +
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DDRPHY_INITENG0_P0_PHYINLPX);
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if (timeout_elapsed(timeout)) {
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panic();
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}
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if (sr_entry) {
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repeat_loop = (phyinlpx & DDRPHY_INITENG0_P0_PHYINLPX_PHYINLP3) == 0U;
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} else {
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repeat_loop = (phyinlpx & DDRPHY_INITENG0_P0_PHYINLPX_PHYINLP3) != 0U;
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}
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} while (repeat_loop);
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/* Disable APB access to internal CSR registers */
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#if STM32MP_DDR3_TYPE || STM32MP_DDR4_TYPE
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mmio_write_32(stm32mp_ddrphyc_base() + DDRPHY_DRTUB0_UCCLKHCLKENABLES, 0U);
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#else /* STM32MP_LPDDR4_TYPE */
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mmio_write_32(stm32mp_ddrphyc_base() + DDRPHY_DRTUB0_UCCLKHCLKENABLES,
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DDRPHY_DRTUB0_UCCLKHCLKENABLES_HCLKEN);
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#endif /* STM32MP_DDR3_TYPE || STM32MP_DDR4_TYPE */
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mmio_write_32(stm32mp_ddrphyc_base() + DDRPHY_APBONLY0_MICROCONTMUXSEL,
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DDRPHY_APBONLY0_MICROCONTMUXSEL_MICROCONTMUXSEL);
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}
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static int sr_loop(bool is_entry)
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{
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uint32_t type;
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uint32_t state __maybe_unused;
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uint64_t timeout = timeout_init_us(DDR_TIMEOUT_US_1S);
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bool repeat_loop = false;
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/*
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* Wait for DDRCTRL to be out of or back to "normal/mission mode".
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* Consider also SRPD mode for LPDDR4 only.
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*/
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do {
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type = mmio_read_32(stm32mp_ddrctrl_base() + DDRCTRL_STAT) &
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DDRCTRL_STAT_SELFREF_TYPE_MASK;
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#if STM32MP_LPDDR4_TYPE
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state = mmio_read_32(stm32mp_ddrctrl_base() + DDRCTRL_STAT) &
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DDRCTRL_STAT_SELFREF_STATE_MASK;
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#endif /* STM32MP_LPDDR4_TYPE */
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if (timeout_elapsed(timeout)) {
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return -ETIMEDOUT;
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}
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if (is_entry) {
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#if STM32MP_LPDDR4_TYPE
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repeat_loop = (type == 0x0U) || (state != DDRCTRL_STAT_SELFREF_STATE_SRPD);
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#else /* !STM32MP_LPDDR4_TYPE */
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repeat_loop = (type == 0x0U);
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#endif /* STM32MP_LPDDR4_TYPE */
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} else {
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#if STM32MP_LPDDR4_TYPE
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repeat_loop = (type != 0x0U) || (state != 0x0U);
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#else /* !STM32MP_LPDDR4_TYPE */
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repeat_loop = (type != 0x0U);
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#endif /* STM32MP_LPDDR4_TYPE */
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}
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} while (repeat_loop);
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return 0;
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}
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static int sr_entry_loop(void)
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{
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return sr_loop(true);
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}
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int ddr_sr_exit_loop(void)
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{
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return sr_loop(false);
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}
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static int sr_ssr_set(void)
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{
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uintptr_t ddrctrl_base = stm32mp_ddrctrl_base();
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/*
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* Disable Clock disable with LP modes
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* (used in RUN mode for LPDDR2 with specific timing).
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*/
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mmio_clrbits_32(ddrctrl_base + DDRCTRL_PWRCTL, DDRCTRL_PWRCTL_EN_DFI_DRAM_CLK_DISABLE);
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/* Disable automatic Self-Refresh mode */
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mmio_clrbits_32(ddrctrl_base + DDRCTRL_PWRCTL, DDRCTRL_PWRCTL_SELFREF_EN);
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mmio_write_32(stm32_ddrdbg_get_base() + DDRDBG_LP_DISABLE,
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DDRDBG_LP_DISABLE_LPI_XPI_DISABLE | DDRDBG_LP_DISABLE_LPI_DDRC_DISABLE);
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return 0;
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}
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static int sr_ssr_entry(bool standby)
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{
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uintptr_t ddrctrl_base = stm32mp_ddrctrl_base();
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uintptr_t rcc_base = stm32mp_rcc_base();
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if (stm32mp_ddr_disable_axi_port((struct stm32mp_ddrctl *)ddrctrl_base) != 0) {
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panic();
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}
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#if STM32MP_LPDDR4_TYPE
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if (standby) {
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/* Disable DRAM drift compensation */
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disable_phy_ddc();
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}
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#endif /* STM32MP_LPDDR4_TYPE */
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disable_dfi_low_power_interface((struct stm32mp_ddrctl *)ddrctrl_base);
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/* SW self refresh entry prequested */
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mmio_setbits_32(ddrctrl_base + DDRCTRL_PWRCTL, DDRCTRL_PWRCTL_SELFREF_SW);
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#if STM32MP_LPDDR4_TYPE
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mmio_clrbits_32(ddrctrl_base + DDRCTRL_PWRCTL, DDRCTRL_PWRCTL_STAY_IN_SELFREF);
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#endif /* STM32MP_LPDDR4_TYPE */
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if (sr_entry_loop() != 0) {
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return -1;
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}
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ddr_activate_controller((struct stm32mp_ddrctl *)ddrctrl_base, true);
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/* Poll on ddrphy_initeng0_phyinlpx.phyinlp3 = 1 */
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ddr_wait_lp3_mode(true);
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if (standby) {
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mmio_clrbits_32(stm32mp_pwr_base() + PWR_CR11, PWR_CR11_DDRRETDIS);
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}
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mmio_clrsetbits_32(rcc_base + RCC_DDRCPCFGR, RCC_DDRCPCFGR_DDRCPLPEN,
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RCC_DDRCPCFGR_DDRCPEN);
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mmio_setbits_32(rcc_base + RCC_DDRPHYCCFGR, RCC_DDRPHYCCFGR_DDRPHYCEN);
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mmio_setbits_32(rcc_base + RCC_DDRITFCFGR, RCC_DDRITFCFGR_DDRPHYDLP);
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return 0;
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}
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static int sr_ssr_exit(void)
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{
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uintptr_t ddrctrl_base = stm32mp_ddrctrl_base();
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uintptr_t rcc_base = stm32mp_rcc_base();
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mmio_setbits_32(rcc_base + RCC_DDRCPCFGR,
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RCC_DDRCPCFGR_DDRCPLPEN | RCC_DDRCPCFGR_DDRCPEN);
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mmio_clrbits_32(rcc_base + RCC_DDRITFCFGR, RCC_DDRITFCFGR_DDRPHYDLP);
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mmio_setbits_32(rcc_base + RCC_DDRPHYCCFGR, RCC_DDRPHYCCFGR_DDRPHYCEN);
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udelay(DDR_DELAY_1US);
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ddr_activate_controller((struct stm32mp_ddrctl *)ddrctrl_base, false);
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/* Poll on ddrphy_initeng0_phyinlpx.phyinlp3 = 0 */
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ddr_wait_lp3_mode(false);
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/* SW self refresh exit prequested */
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mmio_clrbits_32(ddrctrl_base + DDRCTRL_PWRCTL, DDRCTRL_PWRCTL_SELFREF_SW);
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if (ddr_sr_exit_loop() != 0) {
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return -1;
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}
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/* Re-enable DFI low-power interface */
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mmio_setbits_32(ddrctrl_base + DDRCTRL_DFILPCFG0, DDRCTRL_DFILPCFG0_DFI_LP_EN_SR);
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stm32mp_ddr_enable_axi_port((struct stm32mp_ddrctl *)ddrctrl_base);
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return 0;
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}
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static int sr_hsr_set(void)
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{
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uintptr_t ddrctrl_base = stm32mp_ddrctrl_base();
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mmio_clrsetbits_32(stm32mp_rcc_base() + RCC_DDRITFCFGR,
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RCC_DDRITFCFGR_DDRCKMOD_MASK, RCC_DDRITFCFGR_DDRCKMOD_HSR);
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/*
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* manage quasi-dynamic registers modification
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* hwlpctl.hw_lp_en : Group 2
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*/
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if (stm32mp_ddr_sw_selfref_entry((struct stm32mp_ddrctl *)ddrctrl_base) != 0) {
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panic();
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}
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stm32mp_ddr_start_sw_done((struct stm32mp_ddrctl *)ddrctrl_base);
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mmio_write_32(ddrctrl_base + DDRCTRL_HWLPCTL,
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DDRCTRL_HWLPCTL_HW_LP_EN | DDRCTRL_HWLPCTL_HW_LP_EXIT_IDLE_EN |
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(HW_IDLE_PERIOD << DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_SHIFT));
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stm32mp_ddr_wait_sw_done_ack((struct stm32mp_ddrctl *)ddrctrl_base);
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stm32mp_ddr_sw_selfref_exit((struct stm32mp_ddrctl *)ddrctrl_base);
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return 0;
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}
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static int sr_hsr_entry(void)
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{
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mmio_write_32(stm32mp_rcc_base() + RCC_DDRCPCFGR, RCC_DDRCPCFGR_DDRCPLPEN);
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return sr_entry_loop(); /* read_data should be equal to 0x223 */
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}
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static int sr_hsr_exit(void)
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{
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mmio_write_32(stm32mp_rcc_base() + RCC_DDRCPCFGR,
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RCC_DDRCPCFGR_DDRCPLPEN | RCC_DDRCPCFGR_DDRCPEN);
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/* TODO: check if ddr_sr_exit_loop() is needed here */
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return 0;
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}
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static int sr_asr_set(void)
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{
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mmio_write_32(stm32_ddrdbg_get_base() + DDRDBG_LP_DISABLE, 0U);
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return 0;
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}
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static int sr_asr_entry(void)
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{
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/*
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* Automatically enter into self refresh when there is no ddr traffic
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* for the delay programmed into SYSCONF_DDRC_AUTO_SR_DELAY register.
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* Default value is 0x20 (unit: Multiples of 32 DFI clock cycles).
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*/
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return sr_entry_loop();
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}
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static int sr_asr_exit(void)
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{
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return ddr_sr_exit_loop();
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}
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uint32_t ddr_get_io_calibration_val(void)
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{
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/* TODO create related service */
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return 0U;
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}
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int ddr_sr_entry(bool standby)
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{
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int ret = -EINVAL;
|
||||
|
||||
switch (saved_ddr_sr_mode) {
|
||||
case DDR_SSR_MODE:
|
||||
ret = sr_ssr_entry(standby);
|
||||
break;
|
||||
case DDR_HSR_MODE:
|
||||
ret = sr_hsr_entry();
|
||||
break;
|
||||
case DDR_ASR_MODE:
|
||||
ret = sr_asr_entry();
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
int ddr_sr_exit(void)
|
||||
{
|
||||
int ret = -EINVAL;
|
||||
|
||||
switch (saved_ddr_sr_mode) {
|
||||
case DDR_SSR_MODE:
|
||||
ret = sr_ssr_exit();
|
||||
break;
|
||||
case DDR_HSR_MODE:
|
||||
ret = sr_hsr_exit();
|
||||
break;
|
||||
case DDR_ASR_MODE:
|
||||
ret = sr_asr_exit();
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
enum stm32mp2_ddr_sr_mode ddr_read_sr_mode(void)
|
||||
{
|
||||
uint32_t pwrctl = mmio_read_32(stm32mp_ddrctrl_base() + DDRCTRL_PWRCTL);
|
||||
enum stm32mp2_ddr_sr_mode mode = DDR_SR_MODE_INVALID;
|
||||
|
||||
switch (pwrctl & (DDRCTRL_PWRCTL_EN_DFI_DRAM_CLK_DISABLE |
|
||||
DDRCTRL_PWRCTL_SELFREF_EN)) {
|
||||
case 0U:
|
||||
mode = DDR_SSR_MODE;
|
||||
break;
|
||||
case DDRCTRL_PWRCTL_EN_DFI_DRAM_CLK_DISABLE:
|
||||
mode = DDR_HSR_MODE;
|
||||
break;
|
||||
case DDRCTRL_PWRCTL_EN_DFI_DRAM_CLK_DISABLE | DDRCTRL_PWRCTL_SELFREF_EN:
|
||||
mode = DDR_ASR_MODE;
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
return mode;
|
||||
}
|
||||
|
||||
void ddr_set_sr_mode(enum stm32mp2_ddr_sr_mode mode)
|
||||
{
|
||||
int ret = -EINVAL;
|
||||
|
||||
if (mode == saved_ddr_sr_mode) {
|
||||
return;
|
||||
}
|
||||
|
||||
switch (mode) {
|
||||
case DDR_SSR_MODE:
|
||||
ret = sr_ssr_set();
|
||||
break;
|
||||
case DDR_HSR_MODE:
|
||||
ret = sr_hsr_set();
|
||||
break;
|
||||
case DDR_ASR_MODE:
|
||||
ret = sr_asr_set();
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
if (ret != 0) {
|
||||
ERROR("Unknown Self Refresh mode\n");
|
||||
panic();
|
||||
}
|
||||
|
||||
saved_ddr_sr_mode = mode;
|
||||
}
|
||||
|
||||
void ddr_save_sr_mode(void)
|
||||
{
|
||||
saved_ddr_sr_mode = ddr_read_sr_mode();
|
||||
}
|
||||
|
||||
void ddr_restore_sr_mode(void)
|
||||
{
|
||||
ddr_set_sr_mode(saved_ddr_sr_mode);
|
||||
}
|
||||
|
||||
void ddr_sub_system_clk_init(void)
|
||||
{
|
||||
mmio_write_32(stm32mp_rcc_base() + RCC_DDRCPCFGR,
|
||||
RCC_DDRCPCFGR_DDRCPEN | RCC_DDRCPCFGR_DDRCPLPEN);
|
||||
}
|
||||
|
||||
void ddr_sub_system_clk_off(void)
|
||||
{
|
||||
uintptr_t rcc_base = stm32mp_rcc_base();
|
||||
|
||||
/* Clear DDR IO retention */
|
||||
mmio_clrbits_32(stm32mp_pwr_base() + PWR_CR11, PWR_CR11_DDRRETDIS);
|
||||
|
||||
/* Reset DDR sub system */
|
||||
mmio_write_32(rcc_base + RCC_DDRCPCFGR, RCC_DDRCPCFGR_DDRCPRST);
|
||||
mmio_write_32(rcc_base + RCC_DDRITFCFGR, RCC_DDRITFCFGR_DDRRST);
|
||||
mmio_write_32(rcc_base + RCC_DDRPHYCAPBCFGR, RCC_DDRPHYCAPBCFGR_DDRPHYCAPBRST);
|
||||
mmio_write_32(rcc_base + RCC_DDRCAPBCFGR, RCC_DDRCAPBCFGR_DDRCAPBRST);
|
||||
|
||||
/* Deactivate clocks and PLL2 */
|
||||
mmio_clrbits_32(rcc_base + RCC_DDRPHYCCFGR, RCC_DDRPHYCCFGR_DDRPHYCEN);
|
||||
mmio_clrbits_32(rcc_base + RCC_PLL2CFGR1, RCC_PLL2CFGR1_PLLEN);
|
||||
}
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue