diff --git a/drivers/st/ddr/phy/firmware/include/mnpmusrammsgblock_ddr3.h b/drivers/st/ddr/phy/firmware/include/mnpmusrammsgblock_ddr3.h new file mode 100644 index 000000000..936b73c0b --- /dev/null +++ b/drivers/st/ddr/phy/firmware/include/mnpmusrammsgblock_ddr3.h @@ -0,0 +1,935 @@ +/* + * Copyright (C) 2021-2024, STMicroelectronics - All Rights Reserved + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef MNPMUSRAMMSGBLOCK_DDR3_H +#define MNPMUSRAMMSGBLOCK_DDR3_H + +/* + * DDR3U_1D training firmware message block structure + * + * Please refer to the Training Firmware App Note for futher information about + * the usage for Message Block. + */ +struct pmu_smb_ddr_1d { + uint8_t reserved00; /* + * Byte offset 0x00, CSR Addr 0x54000, Direction=In + * reserved00[0:4] RFU, must be zero + * + * reserved00[5] = Train vrefDAC0 During Read Deskew + * 0x1 = Read Deskew will begin by enabling and roughly + * training the phy's per-lane reference voltages. + * Training the vrefDACs CSRs will increase the maximum 1D + * training time by around half a millisecond, but will + * improve 1D training accuracy on systems with + * significant voltage-offsets between lane read eyes. + * 0x0 = Read Deskew will assume the messageblock's + * phyVref setting will work for all lanes. + * + * reserved00[6] = Enable High Effort WrDQ1D + * 0x1 = WrDQ1D will conditionally retry training at + * several extra RxClkDly Timings. This will increase the + * maximum 1D training time by up to 4 extra iterations of + * WrDQ1D. This is only required in systems that suffer + * from very large, asymmetric eye-collapse when receiving + * PRBS patterns. + * 0x0 = WrDQ1D assume rxClkDly values found by SI + * Friendly RdDqs1D will work for receiving PRBS patterns + * + * reserved00[7] = Optimize for the special hard macros in + * TSMC28. + * 0x1 = set if the phy being trained was manufactured in + * any TSMC28 process node. + * 0x0 = otherwise, when not training a TSMC28 phy, leave + * this field as 0. + */ + uint8_t msgmisc; /* + * Byte offset 0x01, CSR Addr 0x54000, Direction=In + * Contains various global options for training. + * + * Bit fields: + * + * msgmisc[0] = MTESTEnable + * 0x1 = Pulse primary digital test output bump at the end + * of each major training stage. This enables observation + * of training stage completion by observing the digital + * test output. + * 0x0 = Do not pulse primary digital test output bump + * + * msgmisc[1] = SimulationOnlyReset + * 0x1 = Verilog only simulation option to shorten + * duration of DRAM reset pulse length to 1ns. + * Must never be set to 1 in silicon. + * 0x0 = Use reset pulse length specified by JEDEC + * standard. + * + * msgmisc[2] = SimulationOnlyTraining + * 0x1 = Verilog only simulation option to shorten the + * duration of the training steps by performing fewer + * iterations. + * Must never be set to 1 in silicon. + * 0x0 = Use standard training duration. + * + * msgmisc[3] = RFU, must be zero + * + * msgmisc[4] = Suppress streaming messages, including + * assertions, regardless of hdtctrl setting. + * Stage Completion messages, as well as training completion + * and error messages are still sent depending on hdtctrl + * setting. + * + * msgmisc[5] = PerByteMaxRdLat + * 0x1 = Each DBYTE will return dfi_rddata_valid at the + * lowest possible latency. This may result in unaligned + * data between bytes to be returned to the DFI. + * 0x0 = Every DBYTE will return dfi_rddata_valid + * simultaneously. This will ensure that data bytes will + * return aligned accesses to the DFI. + * + * msgmisc[6] = PartialRank (DDR3 UDIMM and DDR4 UDIMM only, + * otherwise RFU, must be zero) + * 0x1 = Support rank populated with a subset of byte, but + * where even-odd pair of rank support all the byte + * 0x0 = All rank populated with all the byte (tyical + * configuration) + * + * msgmisc[7] RFU, must be zero + * + * Notes: + * + * - SimulationOnlyReset and SimulationOnlyTraining can be + * used to speed up simulation run times, and must never + * be used in real silicon. Some VIPs may have checks on + * DRAM reset parameters that may need to be disabled when + * using SimulationOnlyReset. + */ + uint16_t pmurevision; /* + * Byte offset 0x02, CSR Addr 0x54001, Direction=Out + * PMU firmware revision ID + * After training is run, this address will contain the + * revision ID of the firmware. + * Please reference this revision ID when filing support + * cases. + */ + uint8_t pstate; /* + * Byte offset 0x04, CSR Addr 0x54002, Direction=In + * Must be set to the target pstate to be trained + * 0x0 = pstate 0 + * 0x1 = pstate 1 + * 0x2 = pstate 2 + * 0x3 = pstate 3 + * All other encodings are reserved + */ + uint8_t pllbypassen; /* + * Byte offset 0x05, CSR Addr 0x54002, Direction=In + * Set according to whether target pstate uses PHY PLL + * bypass + * 0x0 = PHY PLL is enabled for target pstate + * 0x1 = PHY PLL is bypassed for target pstate + */ + uint16_t dramfreq; /* + * Byte offset 0x06, CSR Addr 0x54003, Direction=In + * DDR data rate for the target pstate in units of MT/s. + * For example enter 0x0640 for DDR1600. + */ + uint8_t dfifreqratio; /* + * Byte offset 0x08, CSR Addr 0x54004, Direction=In + * Frequency ratio betwen DfiCtlClk and SDRAM memclk. + * 0x1 = 1:1 + * 0x2 = 1:2 + * 0x4 = 1:4 + */ + uint8_t bpznresval; /* + * Byte offset 0x09, CSR Addr 0x54004, Direction=In + * Overwrite the value of precision resistor connected to + * Phy BP_ZN + * 0x00 = Do not program. Use current CSR value. + * 0xf0 = 240 Ohm + * 0x78 = 120 Ohm + * 0x28 = 40 Ohm + * All other values are reserved. + * It is recommended to set this to 0x00. + */ + uint8_t phyodtimpedance; /* + * Byte offset 0x0a, CSR Addr 0x54005, Direction=In + * Must be programmed to the termination impedance in ohms + * used by PHY during reads. + * + * 0x0 = Firmware skips programming (must be manually + * programmed by user prior to training start) + * + * See PHY databook for legal termination impedance values. + * + * For digital simulation, any legal value can be used. For + * silicon, the users must determine the correct value + * through SI simulation or other methods. + */ + uint8_t phydrvimpedance; /* + * Byte offset 0x0b, CSR Addr 0x54005, Direction=In + * Must be programmed to the driver impedance in ohms used + * by PHY during writes for all DBYTE drivers + * (DQ/DM/DBI/DQS). + * + * 0x0 = Firmware skips programming (must be manually + * programmed by user prior to training start) + * + * See PHY databook for legal R_on driver impedance values. + * + * For digital simulation, any value can be used that is not + * Hi-Z. For silicon, the users must determine the correct + * value through SI simulation or other methods. + */ + uint8_t phyvref; /* + * Byte offset 0x0c, CSR Addr 0x54006, Direction=In + * Must be programmed with the Vref level to be used by the + * PHY during reads + * + * The units of this field are a percentage of VDDQ + * according to the following equation: + * + * Receiver Vref = VDDQ*phyvref[6:0]/128 + * + * For example to set Vref at 0.75*VDDQ, set this field to + * 0x60. + * + * For digital simulation, any legal value can be used. For + * silicon, the users must calculate the analytical Vref by + * using the impedances, terminations, and series resistance + * present in the system. + */ + uint8_t dramtype; /* + * Byte offset 0x0d, CSR Addr 0x54006, Direction=In + * Module Type: + * 0x01 = DDR3 unbuffered + * 0x02 = Reserved + * 0x03 = Reserved + * 0x04 = Reserved + * 0x05 = Reserved + */ + uint8_t disableddbyte; /* + * Byte offset 0x0e, CSR Addr 0x54007, Direction=In + * Bitmap to indicate which Dbyte are not connected (for + * DByte 0 to 7): + * Set disableddbyte[i] to 1 only to specify that DByte is + * not need to be trained (DByte 8 can be disabled via + * enableddqs setting) + */ + uint8_t enableddqs; /* + * Byte offset 0x0f, CSR Addr 0x54007, Direction=In + * Total number of DQ bits enabled in PHY + */ + uint8_t cspresent; /* + * Byte offset 0x10, CSR Addr 0x54008, Direction=In + * Indicates presence of DRAM at each chip select for PHY. + * Each bit corresponds to a logical CS. + * + * If the bit is set to 1, the CS is connected to DRAM. + * If the bit is set to 0, the CS is not connected to DRAM. + * + * cspresent[0] = CS0 is populated with DRAM + * cspresent[1] = CS1 is populated with DRAM + * cspresent[2] = CS2 is populated with DRAM + * cspresent[3] = CS3 is populated with DRAM + * cspresent[7:4] = Reserved (must be programmed to 0) + */ + uint8_t cspresentd0; /* + * Byte offset 0x11, CSR Addr 0x54008, Direction=In + * The CS signals from field cspresent that are routed to + * DIMM connector 0 + */ + uint8_t cspresentd1; /* + * Byte offset 0x12, CSR Addr 0x54009, Direction=In + * The CS signals from field cspresent that are routed to + * DIMM connector 1 + */ + uint8_t addrmirror; /* + * Byte offset 0x13, CSR Addr 0x54009, Direction=In + * Corresponds to CS[3:0] + * 1 = Address Mirror. + * 0 = No Address Mirror. + */ + uint8_t cstestfail; /* + * Byte offset 0x14, CSR Addr 0x5400a, Direction=Out + * This field will be set if training fails on any rank. + * 0x0 = No failures + * non-zero = one or more ranks failed training + */ + uint8_t phycfg; /* + * Byte offset 0x15, CSR Addr 0x5400a, Direction=In + * Additional mode bits. + * + * Bit fields: + * [0] SlowAccessMode: + * 1 = 2T Address Timing. + * 0 = 1T Address Timing. + * [7-1] RFU, must be zero + * + * WARNING: In case of DDR4 Geardown Mode (mr3[A3] == 1), + * phycfg[0] must be 0. + */ + uint16_t sequencectrl; /* + * Byte offset 0x16, CSR Addr 0x5400b, Direction=In + * Controls the training steps to be run. Each bit + * corresponds to a training step. + * + * If the bit is set to 1, the training step will run. + * If the bit is set to 0, the training step will be + * skipped. + * + * Training step to bit mapping: + * sequencectrl[0] = Run DevInit - Device/phy + * initialization. Should always be set. + * sequencectrl[1] = Run WrLvl - Write leveling + * sequencectrl[2] = Run RxEn - Read gate training + * sequencectrl[3] = Run RdDQS1D - 1d read dqs training + * sequencectrl[4] = Run WrDQ1D - 1d write dq training + * sequencectrl[5] = RFU, must be zero + * sequencectrl[6] = RFU, must be zero + * sequencectrl[7] = RFU, must be zero + * sequencectrl[8] = Run RdDeskew - Per lane read dq deskew + * training + * sequencectrl[9] = Run MxRdLat - Max read latency training + * sequencectrl[10] = RFU, must be zero + * sequencectrl[11] = RFU, must be zero + * sequencectrl[12] = RFU, must be zero + * sequencectrl[13] = RFU, must be zero + * sequencectrl[15-14] = RFU, must be zero + */ + uint8_t hdtctrl; /* + * Byte offset 0x18, CSR Addr 0x5400c, Direction=In + * To control the total number of debug messages, a + * verbosity subfield (hdtctrl, Hardware Debug Trace + * Control) exists in the message block. Every message has a + * verbosity level associated with it, and as the hdtctrl + * value is increased, less important s messages stop being + * sent through the mailboxes. The meanings of several major + * hdtctrl thresholds are explained below: + * + * 0x04 = Maximal debug messages (e.g., Eye contours) + * 0x05 = Detailed debug messages (e.g. Eye delays) + * 0x0A = Coarse debug messages (e.g. rank information) + * 0xC8 = Stage completion + * 0xC9 = Assertion messages + * 0xFF = Firmware completion messages only + */ + uint8_t reserved19; /* Byte offset 0x19, CSR Addr 0x5400c, Direction=N/A */ + uint8_t reserved1a; /* Byte offset 0x1a, CSR Addr 0x5400d, Direction=N/A */ + uint8_t share2dvrefresult; /* + * Byte offset 0x1b, CSR Addr 0x5400d, Direction=In + * Bitmap that designates the phy's vref source for every + * pstate + * If share2dvrefresult[x] = 0, then after 2D training, + * pstate x will continue using the phyVref provided in + * pstate x's 1D messageblock. + * If share2dvrefresult[x] = 1, then after 2D training, + * pstate x will use the per-lane VrefDAC0/1 CSRs trained by + * 2d training. + */ + uint8_t reserved1c; /* Byte offset 0x1c, CSR Addr 0x5400e, Direction=N/A */ + uint8_t reserved1d; /* Byte offset 0x1d, CSR Addr 0x5400e, Direction=N/A */ + uint8_t reserved1e; /* + * Byte offset 0x1e, CSR Addr 0x5400f, Direction=In + * Input for constraining the range of vref(DQ) values + * training will collect data for, usually reducing training + * time. However, too large of a voltage range may cause + * longer 2D training times while too small of a voltage + * range may truncate passing regions. When in doubt, leave + * this field set to 0. + * Used by 2D training in: Rd2D, Wr2D + * + * reserved1E[0-3]: Rd2D Voltage Range + * 0 = Training will search all phy vref(DQ) settings + * 1 = limit to +/-2 %VDDQ from phyVref + * 2 = limit to +/-4 %VDDQ from phyVref + * . . . + * 15 = limit to +/-30% VDDQ from phyVref + * + * reserved1E[4-7]: Wr2D Voltage Range + * 0 = Training will search all dram vref(DQ) settings + * 1 = limit to +/-2 %VDDQ from mr6 + * 2 = limit to +/-4 %VDDQ from mr6 + * . . . + * 15 = limit to +/-30% VDDQ from mr6 + */ + uint8_t reserved1f; /* + * Byte offset 0x1f, CSR Addr 0x5400f, Direction=In + * Extended training option: + * + * reserved1F[1:0]: Configured RxClkDly offset try during + * WrDq1D high-effort (i.e., when reserved00[6] is set) + * 0: -8, +8, -16, +16 + * 1: -4, +4, -8, +8, -12, +12, -16, +16 + * 2: -2, +2, -4, +4, -6, +6, -8, +8 + * 3: -2, +2, -4, +4, -6, +6, -8, +8, -10, +10, -12, +12, + * -14, +14, -16, +16 + * + * reserved1F[2]: When set, execute again WrDq1D after + * RdDqs1D PRBS + * + * reserved1F[3]: When set redo RdDeskew with PRBS after + * (first) WrDqs1D + * + * reserved1F[7:4]: This field is reserved and must be + * programmed to 0x00. + */ + uint8_t reserved20; /* + * Byte offset 0x20, CSR Addr 0x54010, Direction=In + * This field is reserved and must be programmed to 0x00, + * excepted for Reserved: + * Reserved MREP assume raising edge is found when + * reserved20[3:0]+3 consecutive 1 are received during MREP + * fine delay swept; reserved20[6:0] thus permits to + * increase tolerance for noisy system. And if reserved20[7] + * is set, MREP training is failing if no raising edge is + * found (otherwise the raising edge is assume close to + * delay 0). + */ + uint8_t reserved21; /* + * Byte offset 0x21, CSR Addr 0x54010, Direction=In + * This field is reserved and must be programmed to 0x00, + * excepted for Reserved: + * Reserved DWL assume raising edge is found when + * reserved21[3:0]+3 consecutive 1 are received during DWL + * fine delay swept; reserved21[6:0] thus permits to + * increase tolerance for noisy system. And if reserved21[7] + * is set, DWL training is failing if no raising edge is + * found (otherwise the raising edge is assume close to + * delay 0). + */ + uint16_t phyconfigoverride; /* + * Byte offset 0x22, CSR Addr 0x54011, Direction=In + * Override PhyConfig csr. + * 0x0: Use hardware csr value for PhyConfing + * (recommended) + * Other values: Use value for PhyConfig instead of + * Hardware value. + */ + uint8_t dfimrlmargin; /* + * Byte offset 0x24, CSR Addr 0x54012, Direction=In + * Margin added to smallest passing trained DFI Max Read + * Latency value, in units of DFI clocks. Recommended to be + * >= 1. + */ + int8_t cdd_rr_3_2; /* + * Byte offset 0x25, CSR Addr 0x54012, Direction=Out + * This is a signed integer value. + * Read to read critical delay difference from cs 3 to cs 2. + */ + int8_t cdd_rr_3_1; /* + * Byte offset 0x26, CSR Addr 0x54013, Direction=Out + * This is a signed integer value. + * Read to read critical delay difference from cs 3 to cs 1. + */ + int8_t cdd_rr_3_0; /* + * Byte offset 0x27, CSR Addr 0x54013, Direction=Out + * This is a signed integer value. + * Read to read critical delay difference from cs 3 to cs 0. + */ + int8_t cdd_rr_2_3; /* + * Byte offset 0x28, CSR Addr 0x54014, Direction=Out + * This is a signed integer value. + * Read to read critical delay difference from cs 2 to cs 3. + */ + int8_t cdd_rr_2_1; /* + * Byte offset 0x29, CSR Addr 0x54014, Direction=Out + * This is a signed integer value. + * Read to read critical delay difference from cs 2 to cs 1. + */ + int8_t cdd_rr_2_0; /* + * Byte offset 0x2a, CSR Addr 0x54015, Direction=Out + * This is a signed integer value. + * Read to read critical delay difference from cs 2 to cs 0. + */ + int8_t cdd_rr_1_3; /* + * Byte offset 0x2b, CSR Addr 0x54015, Direction=Out + * This is a signed integer value. + * Read to read critical delay difference from cs 1 to cs 3. + */ + int8_t cdd_rr_1_2; /* + * Byte offset 0x2c, CSR Addr 0x54016, Direction=Out + * This is a signed integer value. + * Read to read critical delay difference from cs 1 to cs 2. + */ + int8_t cdd_rr_1_0; /* + * Byte offset 0x2d, CSR Addr 0x54016, Direction=Out + * This is a signed integer value. + * Read to read critical delay difference from cs 1 to cs 0. + */ + int8_t cdd_rr_0_3; /* + * Byte offset 0x2e, CSR Addr 0x54017, Direction=Out + * This is a signed integer value. + * Read to read critical delay difference from cs 0 to cs 3. + */ + int8_t cdd_rr_0_2; /* + * Byte offset 0x2f, CSR Addr 0x54017, Direction=Out + * This is a signed integer value. + * Read to read critical delay difference from cs 0 to cs 2. + */ + int8_t cdd_rr_0_1; /* + * Byte offset 0x30, CSR Addr 0x54018, Direction=Out + * This is a signed integer value. + * Read to read critical delay difference from cs 0 to cs 1. + */ + int8_t cdd_ww_3_2; /* + * Byte offset 0x31, CSR Addr 0x54018, Direction=Out + * This is a signed integer value. + * Write to write critical delay difference from cs 3 to cs + * 2. + */ + int8_t cdd_ww_3_1; /* + * Byte offset 0x32, CSR Addr 0x54019, Direction=Out + * This is a signed integer value. + * Write to write critical delay difference from cs 3 to cs + * 1. + */ + int8_t cdd_ww_3_0; /* + * Byte offset 0x33, CSR Addr 0x54019, Direction=Out + * This is a signed integer value. + * Write to write critical delay difference from cs 3 to cs + * 0. + */ + int8_t cdd_ww_2_3; /* + * Byte offset 0x34, CSR Addr 0x5401a, Direction=Out + * This is a signed integer value. + * Write to write critical delay difference from cs 2 to cs + * 3. + */ + int8_t cdd_ww_2_1; /* + * Byte offset 0x35, CSR Addr 0x5401a, Direction=Out + * This is a signed integer value. + * Write to write critical delay difference from cs 2 to cs + * 1. + */ + int8_t cdd_ww_2_0; /* + * Byte offset 0x36, CSR Addr 0x5401b, Direction=Out + * This is a signed integer value. + * Write to write critical delay difference from cs 2 to cs + * 0. + */ + int8_t cdd_ww_1_3; /* + * Byte offset 0x37, CSR Addr 0x5401b, Direction=Out + * This is a signed integer value. + * Write to write critical delay difference from cs 1 to cs + * 3. + */ + int8_t cdd_ww_1_2; /* + * Byte offset 0x38, CSR Addr 0x5401c, Direction=Out + * This is a signed integer value. + * Write to write critical delay difference from cs 1 to cs + * 2. + */ + int8_t cdd_ww_1_0; /* + * Byte offset 0x39, CSR Addr 0x5401c, Direction=Out + * This is a signed integer value. + * Write to write critical delay difference from cs 1 to cs + * 0. + */ + int8_t cdd_ww_0_3; /* + * Byte offset 0x3a, CSR Addr 0x5401d, Direction=Out + * This is a signed integer value. + * Write to write critical delay difference from cs 0 to cs + * 3. + */ + int8_t cdd_ww_0_2; /* + * Byte offset 0x3b, CSR Addr 0x5401d, Direction=Out + * This is a signed integer value. + * Write to write critical delay difference from cs 0 to cs + * 2. + */ + int8_t cdd_ww_0_1; /* + * Byte offset 0x3c, CSR Addr 0x5401e, Direction=Out + * This is a signed integer value. + * Write to write critical delay difference from cs 0 to cs + * 1. + */ + int8_t cdd_rw_3_3; /* + * Byte offset 0x3d, CSR Addr 0x5401e, Direction=Out + * This is a signed integer value. + * Read to write critical delay difference from cs 3 to + * cs 3. + */ + int8_t cdd_rw_3_2; /* + * Byte offset 0x3e, CSR Addr 0x5401f, Direction=Out + * This is a signed integer value. + * Read to write critical delay difference from cs 3 to + * cs 2. + */ + int8_t cdd_rw_3_1; /* + * Byte offset 0x3f, CSR Addr 0x5401f, Direction=Out + * This is a signed integer value. + * Read to write critical delay difference from cs 3 to + * cs 1. + */ + int8_t cdd_rw_3_0; /* + * Byte offset 0x40, CSR Addr 0x54020, Direction=Out + * This is a signed integer value. + * Read to write critical delay difference from cs 3 to + * cs 0. + */ + int8_t cdd_rw_2_3; /* + * Byte offset 0x41, CSR Addr 0x54020, Direction=Out + * This is a signed integer value. + * Read to write critical delay difference from cs 2 to + * cs 3. + */ + int8_t cdd_rw_2_2; /* + * Byte offset 0x42, CSR Addr 0x54021, Direction=Out + * This is a signed integer value. + * Read to write critical delay difference from cs 2 to + * cs 2. + */ + int8_t cdd_rw_2_1; /* + * Byte offset 0x43, CSR Addr 0x54021, Direction=Out + * This is a signed integer value. + * Read to write critical delay difference from cs 2 to + * cs 1. + */ + int8_t cdd_rw_2_0; /* + * Byte offset 0x44, CSR Addr 0x54022, Direction=Out + * This is a signed integer value. + * Read to write critical delay difference from cs 2 to + * cs 0. + */ + int8_t cdd_rw_1_3; /* + * Byte offset 0x45, CSR Addr 0x54022, Direction=Out + * This is a signed integer value. + * Read to write critical delay difference from cs 1 to + * cs 3. + */ + int8_t cdd_rw_1_2; /* + * Byte offset 0x46, CSR Addr 0x54023, Direction=Out + * This is a signed integer value. + * Read to write critical delay difference from cs 1 to + * cs 2. + */ + int8_t cdd_rw_1_1; /* + * Byte offset 0x47, CSR Addr 0x54023, Direction=Out + * This is a signed integer value. + * Read to write critical delay difference from cs 1 to + * cs 1. + */ + int8_t cdd_rw_1_0; /* + * Byte offset 0x48, CSR Addr 0x54024, Direction=Out + * This is a signed integer value. + * Read to write critical delay difference from cs 1 to + * cs 0. + */ + int8_t cdd_rw_0_3; /* + * Byte offset 0x49, CSR Addr 0x54024, Direction=Out + * This is a signed integer value. + * Read to write critical delay difference from cs 0 to + * cs 3. + */ + int8_t cdd_rw_0_2; /* + * Byte offset 0x4a, CSR Addr 0x54025, Direction=Out + * This is a signed integer value. + * Read to write critical delay difference from cs 0 to + * cs 2. + */ + int8_t cdd_rw_0_1; /* + * Byte offset 0x4b, CSR Addr 0x54025, Direction=Out + * This is a signed integer value. + * Read to write critical delay difference from cs 0 to + * cs 1. + */ + int8_t cdd_rw_0_0; /* + * Byte offset 0x4c, CSR Addr 0x54026, Direction=Out + * This is a signed integer value. + * Read to write critical delay difference from cs 0 to + * cs 0. + */ + int8_t cdd_wr_3_3; /* + * Byte offset 0x4d, CSR Addr 0x54026, Direction=Out + * This is a signed integer value. + * Write to read critical delay difference from cs 3 to + * cs 3. + */ + int8_t cdd_wr_3_2; /* + * Byte offset 0x4e, CSR Addr 0x54027, Direction=Out + * This is a signed integer value. + * Write to read critical delay difference from cs 3 to + * cs 2. + */ + int8_t cdd_wr_3_1; /* + * Byte offset 0x4f, CSR Addr 0x54027, Direction=Out + * This is a signed integer value. + * Write to read critical delay difference from cs 3 to + * cs 1. + */ + int8_t cdd_wr_3_0; /* + * Byte offset 0x50, CSR Addr 0x54028, Direction=Out + * This is a signed integer value. + * Write to read critical delay difference from cs 3 to + * cs 0. + */ + int8_t cdd_wr_2_3; /* + * Byte offset 0x51, CSR Addr 0x54028, Direction=Out + * This is a signed integer value. + * Write to read critical delay difference from cs 2 to + * cs 3. + */ + int8_t cdd_wr_2_2; /* + * Byte offset 0x52, CSR Addr 0x54029, Direction=Out + * This is a signed integer value. + * Write to read critical delay difference from cs 2 to + * cs 2. + */ + int8_t cdd_wr_2_1; /* + * Byte offset 0x53, CSR Addr 0x54029, Direction=Out + * This is a signed integer value. + * Write to read critical delay difference from cs 2 to + * cs 1. + */ + int8_t cdd_wr_2_0; /* + * Byte offset 0x54, CSR Addr 0x5402a, Direction=Out + * This is a signed integer value. + * Write to read critical delay difference from cs 2 to + * cs 0. + */ + int8_t cdd_wr_1_3; /* + * Byte offset 0x55, CSR Addr 0x5402a, Direction=Out + * This is a signed integer value. + * Write to read critical delay difference from cs 1 to + * cs 3. + */ + int8_t cdd_wr_1_2; /* + * Byte offset 0x56, CSR Addr 0x5402b, Direction=Out + * This is a signed integer value. + * Write to read critical delay difference from cs 1 to + * cs 2. + */ + int8_t cdd_wr_1_1; /* + * Byte offset 0x57, CSR Addr 0x5402b, Direction=Out + * This is a signed integer value. + * Write to read critical delay difference from cs 1 to + * cs 1. + */ + int8_t cdd_wr_1_0; /* + * Byte offset 0x58, CSR Addr 0x5402c, Direction=Out + * This is a signed integer value. + * Write to read critical delay difference from cs 1 to + * cs 0. + */ + int8_t cdd_wr_0_3; /* + * Byte offset 0x59, CSR Addr 0x5402c, Direction=Out + * This is a signed integer value. + * Write to read critical delay difference from cs 0 to + * cs 3. + */ + int8_t cdd_wr_0_2; /* + * Byte offset 0x5a, CSR Addr 0x5402d, Direction=Out + * This is a signed integer value. + * Write to read critical delay difference from cs 0 to + * cs 2. + */ + int8_t cdd_wr_0_1; /* + * Byte offset 0x5b, CSR Addr 0x5402d, Direction=Out + * This is a signed integer value. + * Write to read critical delay difference from cs 0 to + * cs 1. + */ + int8_t cdd_wr_0_0; /* + * Byte offset 0x5c, CSR Addr 0x5402e, Direction=Out + * This is a signed integer value. + * Write to read critical delay difference from cs 0 to + * cs 0. + */ + uint8_t reserved5d; /* + * Byte offset 0x5d, CSR Addr 0x5402e, Direction=In + * This field is reserved and must be programmed to 0x00, + * excepted for DDR4: + * By default, if this parameter is 0, the offset applied at + * the end of DDR4 RxEn training resulting in the trained + * RxEnDly is 3/8 of the RX preamble width; if reserved5D is + * non zero, this offset is used instead (in fine step). + */ + uint16_t mr0; /* + * Byte offset 0x5e, CSR Addr 0x5402f, Direction=In + * Value of DDR mode register mr0 for all ranks for current + * pstate. + */ + uint16_t mr1; /* + * Byte offset 0x60, CSR Addr 0x54030, Direction=In + * Value of DDR mode register mr1 for all ranks for current + * pstate. + */ + uint16_t mr2; /* + * Byte offset 0x62, CSR Addr 0x54031, Direction=In + * Value of DDR mode register mr2 for all ranks for current + * pstate. + */ + uint8_t reserved64; /* + * Byte offset 0x64, CSR Addr 0x54032, Direction=In + * Reserved64[0] = protect memory reset + * 0x0 = dfi_reset_n cannot control CP_MEMRESET_L to + * devices after training. (Default value) + * 0x1 = dfi_reset_n can control CP_MEMRESET_L to + * devices after training. + * + * Reserved64[7:1] RFU, must be zero + */ + uint8_t reserved65; /* + * Byte offset 0x65, CSR Addr 0x54032, Direction=N/A + * This field is reserved and must be programmed to 0x00. + */ + uint8_t reserved66; /* + * Byte offset 0x66, CSR Addr 0x54033, Direction=N/A + * This field is reserved and must be programmed to 0x00. + */ + uint8_t reserved67; /* + * Byte offset 0x67, CSR Addr 0x54033, Direction=N/A + * This field is reserved and must be programmed to 0x00. + */ + uint8_t reserved68; /* + * Byte offset 0x68, CSR Addr 0x54034, Direction=N/A + * This field is reserved and must be programmed to 0x00. + */ + uint8_t reserved69; /* + * Byte offset 0x69, CSR Addr 0x54034, Direction=N/A + * This field is reserved and must be programmed to 0x00. + */ + uint8_t reserved6a; /* + * Byte offset 0x6a, CSR Addr 0x54035, Direction=N/A + * This field is reserved and must be programmed to 0x00. + */ + uint8_t reserved6b; /* + * Byte offset 0x6b, CSR Addr 0x54035, Direction=N/A + * This field is reserved and must be programmed to 0x00. + */ + uint8_t reserved6c; /* + * Byte offset 0x6c, CSR Addr 0x54036, Direction=N/A + * This field is reserved and must be programmed to 0x00. + */ + uint8_t reserved6d; /* + * Byte offset 0x6d, CSR Addr 0x54036, Direction=N/A + * This field is reserved and must be programmed to 0x00. + */ + uint8_t reserved6e; /* + * Byte offset 0x6e, CSR Addr 0x54037, Direction=N/A + * This field is reserved and must be programmed to 0x00. + */ + uint8_t reserved6f; /* + * Byte offset 0x6f, CSR Addr 0x54037, Direction=N/A + * This field is reserved and must be programmed to 0x00. + */ + uint8_t reserved70; /* + * Byte offset 0x70, CSR Addr 0x54038, Direction=N/A + * This field is reserved and must be programmed to 0x00. + */ + uint8_t reserved71; /* + * Byte offset 0x71, CSR Addr 0x54038, Direction=N/A + * This field is reserved and must be programmed to 0x00. + */ + uint8_t reserved72; /* + * Byte offset 0x72, CSR Addr 0x54039, Direction=N/A + * This field is reserved and must be programmed to 0x00. + */ + uint8_t reserved73; /* + * Byte offset 0x73, CSR Addr 0x54039, Direction=N/A + * This field is reserved and must be programmed to 0x00. + */ + uint8_t acsmodtctrl0; /* + * Byte offset 0x74, CSR Addr 0x5403a, Direction=In + * Odt pattern for accesses targeting rank 0. [3:0] is used + * for write ODT [7:4] is used for read ODT + */ + uint8_t acsmodtctrl1; /* + * Byte offset 0x75, CSR Addr 0x5403a, Direction=In + * Odt pattern for accesses targeting rank 1. [3:0] is used + * for write ODT [7:4] is used for read ODT + */ + uint8_t acsmodtctrl2; /* + * Byte offset 0x76, CSR Addr 0x5403b, Direction=In + * Odt pattern for accesses targeting rank 2. [3:0] is used + * for write ODT [7:4] is used for read ODT + */ + uint8_t acsmodtctrl3; /* + * Byte offset 0x77, CSR Addr 0x5403b, Direction=In + * Odt pattern for accesses targeting rank 3. [3:0] is used + * for write ODT [7:4] is used for read ODT + */ + uint8_t acsmodtctrl4; /* + * Byte offset 0x78, CSR Addr 0x5403c, Direction=In + * This field is reserved and must be programmed to 0x00. + */ + uint8_t acsmodtctrl5; /* + * Byte offset 0x79, CSR Addr 0x5403c, Direction=In + * This field is reserved and must be programmed to 0x00. + */ + uint8_t acsmodtctrl6; /* + * Byte offset 0x7a, CSR Addr 0x5403d, Direction=In + * This field is reserved and must be programmed to 0x00. + */ + uint8_t acsmodtctrl7; /* + * Byte offset 0x7b, CSR Addr 0x5403d, Direction=In + * This field is reserved and must be programmed to 0x00. + */ + uint8_t reserved7c; /* + * Byte offset 0x7c, CSR Addr 0x5403e, Direction=N/A + * This field is reserved and must be programmed to 0x00. + */ + uint8_t reserved7d; /* + * Byte offset 0x7d, CSR Addr 0x5403e, Direction=N/A + * This field is reserved and must be programmed to 0x00. + */ + uint8_t reserved7e; /* + * Byte offset 0x7e, CSR Addr 0x5403f, Direction=N/A + * This field is reserved and must be programmed to 0x00. + */ + uint8_t reserved7f; /* + * Byte offset 0x7f, CSR Addr 0x5403f, Direction=N/A + * This field is reserved and must be programmed to 0x00. + */ + uint8_t reserved80; /* + * Byte offset 0x80, CSR Addr 0x54040, Direction=N/A + * This field is reserved and must be programmed to 0x00. + */ + uint8_t reserved81; /* + * Byte offset 0x81, CSR Addr 0x54040, Direction=N/A + * This field is reserved and must be programmed to 0x00. + */ + uint8_t reserved82; /* + * Byte offset 0x82, CSR Addr 0x54041, Direction=N/A + * This field is reserved and must be programmed to 0x00. + */ + uint8_t reserved83; /* + * Byte offset 0x83, CSR Addr 0x54041, Direction=N/A + * This field is reserved and must be programmed to 0x00. + */ + uint8_t reserved84; /* Byte offset 0x84, CSR Addr 0x54042, Direction=N/A */ + uint8_t reserved85; /* Byte offset 0x85, CSR Addr 0x54042, Direction=N/A */ + uint8_t reserved86; /* Byte offset 0x86, CSR Addr 0x54043, Direction=N/A */ + uint8_t reserved87; /* Byte offset 0x87, CSR Addr 0x54043, Direction=N/A */ + uint8_t reserved88; /* Byte offset 0x88, CSR Addr 0x54044, Direction=N/A */ + uint8_t reserved89; /* Byte offset 0x89, CSR Addr 0x54044, Direction=N/A */ + uint8_t reserved8a; /* Byte offset 0x8a, CSR Addr 0x54045, Direction=N/A */ + uint8_t reserved8b; /* Byte offset 0x8b, CSR Addr 0x54045, Direction=N/A */ + uint8_t reserved8c; /* Byte offset 0x8c, CSR Addr 0x54046, Direction=N/A */ + uint8_t reserved8d; /* Byte offset 0x8d, CSR Addr 0x54046, Direction=N/A */ + uint8_t reserved8e; /* Byte offset 0x8e, CSR Addr 0x54047, Direction=N/A */ + uint8_t reserved8f; /* Byte offset 0x8f, CSR Addr 0x54047, Direction=N/A */ + uint8_t reserved90; /* Byte offset 0x90, CSR Addr 0x54048, Direction=N/A */ + uint8_t reserved91; /* Byte offset 0x91, CSR Addr 0x54048, Direction=N/A */ + uint8_t reserved92; /* Byte offset 0x92, CSR Addr 0x54049, Direction=N/A */ + uint8_t reserved93; /* Byte offset 0x93, CSR Addr 0x54049, Direction=N/A */ + uint8_t reserved94; /* Byte offset 0x94, CSR Addr 0x5404a, Direction=N/A */ + uint8_t reserved95; /* Byte offset 0x95, CSR Addr 0x5404a, Direction=N/A */ + uint8_t reserved96; /* Byte offset 0x96, CSR Addr 0x5404b, Direction=N/A */ + uint8_t reserved97; /* Byte offset 0x97, CSR Addr 0x5404b, Direction=N/A */ + uint8_t reserved98; /* Byte offset 0x98, CSR Addr 0x5404c, Direction=N/A */ + uint8_t reserved99; /* Byte offset 0x99, CSR Addr 0x5404c, Direction=N/A */ + uint8_t reserved9a; /* Byte offset 0x9a, CSR Addr 0x5404d, Direction=N/A */ + uint8_t reserved9b; /* Byte offset 0x9b, CSR Addr 0x5404d, Direction=N/A */ + uint8_t reserved9c; /* Byte offset 0x9c, CSR Addr 0x5404e, Direction=N/A */ + uint8_t reserved9d; /* Byte offset 0x9d, CSR Addr 0x5404e, Direction=N/A */ + uint8_t reserved9e; /* Byte offset 0x9e, CSR Addr 0x5404f, Direction=N/A */ + uint8_t reserved9f; /* Byte offset 0x9f, CSR Addr 0x5404f, Direction=N/A */ + uint8_t reserveda0; /* Byte offset 0xa0, CSR Addr 0x54050, Direction=N/A */ + uint8_t reserveda1; /* Byte offset 0xa1, CSR Addr 0x54050, Direction=N/A */ + uint8_t reserveda2; /* Byte offset 0xa2, CSR Addr 0x54051, Direction=N/A */ + uint8_t reserveda3; /* Byte offset 0xa3, CSR Addr 0x54051, Direction=N/A */ +} __packed __aligned(2); + +#endif /* MNPMUSRAMMSGBLOCK_DDR3_H */ diff --git a/drivers/st/ddr/phy/firmware/include/mnpmusrammsgblock_ddr4.h b/drivers/st/ddr/phy/firmware/include/mnpmusrammsgblock_ddr4.h new file mode 100644 index 000000000..384650e41 --- /dev/null +++ b/drivers/st/ddr/phy/firmware/include/mnpmusrammsgblock_ddr4.h @@ -0,0 +1,2203 @@ +/* + * Copyright (C) 2021-2024, STMicroelectronics - All Rights Reserved + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef MNPMUSRAMMSGBLOCK_DDR4_H +#define MNPMUSRAMMSGBLOCK_DDR4_H + +/* DDR4U_1D training firmware message block structure + * + * Please refer to the Training Firmware App Note for futher information about + * the usage for Message Block. + */ +struct pmu_smb_ddr_1d { + uint8_t reserved00; /* + * Byte offset 0x00, CSR Addr 0x54000, Direction=In + * reserved00[0:4] RFU, must be zero + * + * reserved00[5] = Train vrefDAC0 During Read Deskew + * 0x1 = Read Deskew will begin by enabling and roughly + * training the phy's per-lane reference voltages. + * Training the vrefDACs CSRs will increase the maximum 1D + * training time by around half a millisecond, but will + * improve 1D training accuracy on systems with + * significant voltage-offsets between lane read eyes. + * 0x0 = Read Deskew will assume the messageblock's + * phyVref setting will work for all lanes. + * + * reserved00[6] = Enable High Effort WrDQ1D + * 0x1 = WrDQ1D will conditionally retry training at + * several extra RxClkDly Timings. This will increase the + * maximum 1D training time by up to 4 extra iterations of + * WrDQ1D. This is only required in systems that suffer + * from very large, asymmetric eye-collapse when receiving + * PRBS patterns. + * 0x0 = WrDQ1D assume rxClkDly values found by SI + * Friendly RdDqs1D will work for receiving PRBS patterns + * + * reserved00[7] = Optimize for the special hard macros in + * TSMC28. + * 0x1 = set if the phy being trained was manufactured in + * any TSMC28 process node. + * 0x0 = otherwise, when not training a TSMC28 phy, leave + * this field as 0. + */ + uint8_t msgmisc; /* + * Byte offset 0x01, CSR Addr 0x54000, Direction=In + * Contains various global options for training. + * + * Bit fields: + * + * msgmisc[0] = MTESTEnable + * 0x1 = Pulse primary digital test output bump at the end + * of each major training stage. This enables observation + * of training stage completion by observing the digital + * test output. + * 0x0 = Do not pulse primary digital test output bump + * + * msgmisc[1] = SimulationOnlyReset + * 0x1 = Verilog only simulation option to shorten + * duration of DRAM reset pulse length to 1ns. + * Must never be set to 1 in silicon. + * 0x0 = Use reset pulse length specified by JEDEC + * standard. + * + * msgmisc[2] = SimulationOnlyTraining + * 0x1 = Verilog only simulation option to shorten the + * duration of the training steps by performing fewer + * iterations. + * Must never be set to 1 in silicon. + * 0x0 = Use standard training duration. + * + * msgmisc[3] = RFU, must be zero + * 0x1 = Program user characterized Vref DQ values per + * DDR4 DRAM device. The message block vrefdqr*nib* fields + * must be populated with the desired per device Vref DQs + * when using this option. Note: this option is not + * applicable in 2D training because these values are + * explicitly trained in 2D. + * 0x0 = Program Vref DQ for all DDR4 devices with the + * single value provided in mr6 message block field + * + * msgmisc[4] = Suppress streaming messages, including + * assertions, regardless of hdtctrl setting. + * Stage Completion messages, as well as training completion + * and error messages are still sent depending on hdtctrl + * setting. + * + * msgmisc[5] = PerByteMaxRdLat + * 0x1 = Each DBYTE will return dfi_rddata_valid at the + * lowest possible latency. This may result in unaligned + * data between bytes to be returned to the DFI. + * 0x0 = Every DBYTE will return dfi_rddata_valid + * simultaneously. This will ensure that data bytes will + * return aligned accesses to the DFI. + * + * msgmisc[6] = PartialRank (DDR3 UDIMM and DDR4 UDIMM only, + * otherwise RFU, must be zero) + * 0x1 = Support rank populated with a subset of byte, but + * where even-odd pair of rank support all the byte + * 0x0 = All rank populated with all the byte (tyical + * configuration) + * + * msgmisc[7] RFU, must be zero + * + * Notes: + * + * - SimulationOnlyReset and SimulationOnlyTraining can be + * used to speed up simulation run times, and must never + * be used in real silicon. Some VIPs may have checks on + * DRAM reset parameters that may need to be disabled when + * using SimulationOnlyReset. + */ + uint16_t pmurevision; /* + * Byte offset 0x02, CSR Addr 0x54001, Direction=Out + * PMU firmware revision ID + * After training is run, this address will contain the + * revision ID of the firmware. + * Please reference this revision ID when filing support + * cases. + */ + uint8_t pstate; /* + * Byte offset 0x04, CSR Addr 0x54002, Direction=In + * Must be set to the target pstate to be trained + * 0x0 = pstate 0 + * 0x1 = pstate 1 + * 0x2 = pstate 2 + * 0x3 = pstate 3 + * All other encodings are reserved + */ + uint8_t pllbypassen; /* + * Byte offset 0x05, CSR Addr 0x54002, Direction=In + * Set according to whether target pstate uses PHY PLL + * bypass + * 0x0 = PHY PLL is enabled for target pstate + * 0x1 = PHY PLL is bypassed for target pstate + */ + uint16_t dramfreq; /* + * Byte offset 0x06, CSR Addr 0x54003, Direction=In + * DDR data rate for the target pstate in units of MT/s. + * For example enter 0x0640 for DDR1600. + */ + uint8_t dfifreqratio; /* + * Byte offset 0x08, CSR Addr 0x54004, Direction=In + * Frequency ratio betwen DfiCtlClk and SDRAM memclk. + * 0x1 = 1:1 + * 0x2 = 1:2 + * 0x4 = 1:4 + */ + uint8_t bpznresval; /* + * Byte offset 0x09, CSR Addr 0x54004, Direction=In + * Overwrite the value of precision resistor connected to + * Phy BP_ZN + * 0x00 = Do not program. Use current CSR value. + * 0xf0 = 240 Ohm + * 0x78 = 120 Ohm + * 0x28 = 40 Ohm + * All other values are reserved. + * It is recommended to set this to 0x00. + */ + uint8_t phyodtimpedance; /* + * Byte offset 0x0a, CSR Addr 0x54005, Direction=In + * Must be programmed to the termination impedance in ohms + * used by PHY during reads. + * + * 0x0 = Firmware skips programming (must be manually + * programmed by user prior to training start) + * + * See PHY databook for legal termination impedance values. + * + * For digital simulation, any legal value can be used. For + * silicon, the users must determine the correct value + * through SI simulation or other methods. + */ + uint8_t phydrvimpedance; /* + * Byte offset 0x0b, CSR Addr 0x54005, Direction=In + * Must be programmed to the driver impedance in ohms used + * by PHY during writes for all DBYTE drivers + * (DQ/DM/DBI/DQS). + * + * 0x0 = Firmware skips programming (must be manually + * programmed by user prior to training start) + * + * See PHY databook for legal R_on driver impedance values. + * + * For digital simulation, any value can be used that is not + * Hi-Z. For silicon, the users must determine the correct + * value through SI simulation or other methods. + */ + uint8_t phyvref; /* + * Byte offset 0x0c, CSR Addr 0x54006, Direction=In + * Must be programmed with the Vref level to be used by the + * PHY during reads + * + * The units of this field are a percentage of VDDQ + * according to the following equation: + * + * Receiver Vref = VDDQ*phyvref[6:0]/128 + * + * For example to set Vref at 0.75*VDDQ, set this field to + * 0x60. + * + * For digital simulation, any legal value can be used. For + * silicon, the users must calculate the analytical Vref by + * using the impedances, terminations, and series resistance + * present in the system. + */ + uint8_t dramtype; /* + * Byte offset 0x0d, CSR Addr 0x54006, Direction=In + * Module Type: + * 0x01 = Reserved + * 0x02 = DDR4 unbuffered + * 0x03 = Reserved + * 0x04 = Reserved + * 0x05 = Reserved + */ + uint8_t disableddbyte; /* + * Byte offset 0x0e, CSR Addr 0x54007, Direction=In + * Bitmap to indicate which Dbyte are not connected (for + * DByte 0 to 7): + * Set disableddbyte[i] to 1 only to specify that DByte is + * not need to be trained (DByte 8 can be disabled via + * enableddqs setting) + */ + uint8_t enableddqs; /* + * Byte offset 0x0f, CSR Addr 0x54007, Direction=In + * Total number of DQ bits enabled in PHY + */ + uint8_t cspresent; /* + * Byte offset 0x10, CSR Addr 0x54008, Direction=In + * Indicates presence of DRAM at each chip select for PHY. + * Each bit corresponds to a logical CS. + * + * If the bit is set to 1, the CS is connected to DRAM. + * If the bit is set to 0, the CS is not connected to DRAM. + * + * cspresent[0] = CS0 is populated with DRAM + * cspresent[1] = CS1 is populated with DRAM + * cspresent[2] = CS2 is populated with DRAM + * cspresent[3] = CS3 is populated with DRAM + * cspresent[7:4] = Reserved (must be programmed to 0) + */ + uint8_t cspresentd0; /* + * Byte offset 0x11, CSR Addr 0x54008, Direction=In + * The CS signals from field cspresent that are routed to + * DIMM connector 0 + */ + uint8_t cspresentd1; /* + * Byte offset 0x12, CSR Addr 0x54009, Direction=In + * The CS signals from field cspresent that are routed to + * DIMM connector 1 + */ + uint8_t addrmirror; /* + * Byte offset 0x13, CSR Addr 0x54009, Direction=In + * Corresponds to CS[3:0] + * 1 = Address Mirror. + * 0 = No Address Mirror. + */ + uint8_t cstestfail; /* + * Byte offset 0x14, CSR Addr 0x5400a, Direction=Out + * This field will be set if training fails on any rank. + * 0x0 = No failures + * non-zero = one or more ranks failed training + */ + uint8_t phycfg; /* + * Byte offset 0x15, CSR Addr 0x5400a, Direction=In + * Additional mode bits. + * + * Bit fields: + * [0] SlowAccessMode: + * 1 = 2T Address Timing. + * 0 = 1T Address Timing. + * [7-1] RFU, must be zero + * + * WARNING: In case of DDR4 Geardown Mode (mr3[A3] == 1), + * phycfg[0] must be 0. + */ + uint16_t sequencectrl; /* + * Byte offset 0x16, CSR Addr 0x5400b, Direction=In + * Controls the training steps to be run. Each bit + * corresponds to a training step. + * + * If the bit is set to 1, the training step will run. + * If the bit is set to 0, the training step will be + * skipped. + * + * Training step to bit mapping: + * sequencectrl[0] = Run DevInit - Device/phy + * initialization. Should always be set. + * sequencectrl[1] = Run WrLvl - Write leveling + * sequencectrl[2] = Run RxEn - Read gate training + * sequencectrl[3] = Run RdDQS1D - 1d read dqs training + * sequencectrl[4] = Run WrDQ1D - 1d write dq training + * sequencectrl[5] = RFU, must be zero + * sequencectrl[6] = RFU, must be zero + * sequencectrl[7] = RFU, must be zero + * sequencectrl[8] = Run RdDeskew - Per lane read dq deskew + * training + * sequencectrl[9] = Run MxRdLat - Max read latency training + * sequencectrl[10] = Run Reserved + * sequencectrl[11] = Run Reserved + * sequencectrl[12] = Run Reserved + * sequencectrl[13] = Run Reserved + * sequencectrl[15-14] = RFU, must be zero + */ + uint8_t hdtctrl; /* + * Byte offset 0x18, CSR Addr 0x5400c, Direction=In + * To control the total number of debug messages, a + * verbosity subfield (hdtctrl, Hardware Debug Trace + * Control) exists in the message block. Every message has a + * verbosity level associated with it, and as the hdtctrl + * value is increased, less important s messages stop being + * sent through the mailboxes. The meanings of several major + * hdtctrl thresholds are explained below: + * + * 0x04 = Maximal debug messages (e.g., Eye contours) + * 0x05 = Detailed debug messages (e.g. Eye delays) + * 0x0A = Coarse debug messages (e.g. rank information) + * 0xC8 = Stage completion + * 0xC9 = Assertion messages + * 0xFF = Firmware completion messages only + */ + uint8_t reserved19; /* Byte offset 0x19, CSR Addr 0x5400c, Direction=N/A */ + uint8_t reserved1a; /* Byte offset 0x1a, CSR Addr 0x5400d, Direction=N/A */ + uint8_t share2dvrefresult; /* + * Byte offset 0x1b, CSR Addr 0x5400d, Direction=In + * Bitmap that designates the phy's vref source for every + * pstate + * If share2dvrefresult[x] = 0, then after 2D training, + * pstate x will continue using the phyVref provided in + * pstate x's 1D messageblock. + * If share2dvrefresult[x] = 1, then after 2D training, + * pstate x will use the per-lane VrefDAC0/1 CSRs trained by + * 2d training. + */ + uint8_t reserved1c; /* Byte offset 0x1c, CSR Addr 0x5400e, Direction=N/A */ + uint8_t reserved1d; /* Byte offset 0x1d, CSR Addr 0x5400e, Direction=N/A */ + uint8_t reserved1e; /* + * Byte offset 0x1e, CSR Addr 0x5400f, Direction=In + * Input for constraining the range of vref(DQ) values + * training will collect data for, usually reducing training + * time. However, too large of a voltage range may cause + * longer 2D training times while too small of a voltage + * range may truncate passing regions. When in doubt, leave + * this field set to 0. + * Used by 2D training in: Rd2D, Wr2D + * + * reserved1E[0-3]: Rd2D Voltage Range + * 0 = Training will search all phy vref(DQ) settings + * 1 = limit to +/-2 %VDDQ from phyVref + * 2 = limit to +/-4 %VDDQ from phyVref + * . . . + * 15 = limit to +/-30% VDDQ from phyVref + * + * reserved1E[4-7]: Wr2D Voltage Range + * 0 = Training will search all dram vref(DQ) settings + * 1 = limit to +/-2 %VDDQ from mr6 + * 2 = limit to +/-4 %VDDQ from mr6 + * . . . + * 15 = limit to +/-30% VDDQ from mr6 + */ + uint8_t reserved1f; /* + * Byte offset 0x1f, CSR Addr 0x5400f, Direction=In + * Extended training option: + * + * reserved1F[1:0]: Configured RxClkDly offset try during + * WrDq1D high-effort (i.e., when reserved00[6] is set) + * 0: -8, +8, -16, +16 + * 1: -4, +4, -8, +8, -12, +12, -16, +16 + * 2: -2, +2, -4, +4, -6, +6, -8, +8 + * 3: -2, +2, -4, +4, -6, +6, -8, +8, -10, +10, -12, +12, + * -14, +14, -16, +16 + * + * reserved1F[2]: When set, execute again WrDq1D after + * RdDqs1D PRBS + * reserved1F[3]: When set redo RdDeskew with PRBS after + * (first) WrDqs1D + * reserved1F[7:4]: This field is reserved and must be + * programmed to 0x00. + */ + uint8_t reserved20; /* + * Byte offset 0x20, CSR Addr 0x54010, Direction=In + * This field is reserved and must be programmed to 0x00, + * excepted for Reserved: + * Reserved MREP assume raising edge is found when + * reserved20[3:0]+3 consecutive 1 are received during MREP + * fine delay swept; reserved20[6:0] thus permits to + * increase tolerance for noisy system. And if reserved20[7] + * is set, MREP training is failing if no raising edge is + * found (otherwise the raising edge is assume close to + * delay 0). + */ + uint8_t reserved21; /* + * Byte offset 0x21, CSR Addr 0x54010, Direction=In + * This field is reserved and must be programmed to 0x00, + * excepted for Reserved: + * Reserved DWL assume raising edge is found when + * reserved21[3:0]+3 consecutive 1 are received during DWL + * fine delay swept; reserved21[6:0] thus permits to + * increase tolerance for noisy system. And if reserved21[7] + * is set, DWL training is failing if no raising edge is + * found (otherwise the raising edge is assume close to + * delay 0). + */ + uint16_t phyconfigoverride; /* + * Byte offset 0x22, CSR Addr 0x54011, Direction=In + * Override PhyConfig csr. + * 0x0: Use hardware csr value for PhyConfing + * (recommended) + * Other values: Use value for PhyConfig instead of + * Hardware value. + */ + uint8_t dfimrlmargin; /* + * Byte offset 0x24, CSR Addr 0x54012, Direction=In + * Margin added to smallest passing trained DFI Max Read + * Latency value, in units of DFI clocks. Recommended to be + * >= 1. + */ + int8_t cdd_rr_3_2; /* + * Byte offset 0x25, CSR Addr 0x54012, Direction=Out + * This is a signed integer value. + * Read to read critical delay difference from cs 3 to cs 2. + */ + int8_t cdd_rr_3_1; /* + * Byte offset 0x26, CSR Addr 0x54013, Direction=Out + * This is a signed integer value. + * Read to read critical delay difference from cs 3 to cs 1. + */ + int8_t cdd_rr_3_0; /* + * Byte offset 0x27, CSR Addr 0x54013, Direction=Out + * This is a signed integer value. + * Read to read critical delay difference from cs 3 to cs 0. + */ + int8_t cdd_rr_2_3; /* + * Byte offset 0x28, CSR Addr 0x54014, Direction=Out + * This is a signed integer value. + * Read to read critical delay difference from cs 2 to cs 3. + */ + int8_t cdd_rr_2_1; /* + * Byte offset 0x29, CSR Addr 0x54014, Direction=Out + * This is a signed integer value. + * Read to read critical delay difference from cs 2 to cs 1. + */ + int8_t cdd_rr_2_0; /* + * Byte offset 0x2a, CSR Addr 0x54015, Direction=Out + * This is a signed integer value. + * Read to read critical delay difference from cs 2 to cs 0. + */ + int8_t cdd_rr_1_3; /* + * Byte offset 0x2b, CSR Addr 0x54015, Direction=Out + * This is a signed integer value. + * Read to read critical delay difference from cs 1 to cs 3. + */ + int8_t cdd_rr_1_2; /* + * Byte offset 0x2c, CSR Addr 0x54016, Direction=Out + * This is a signed integer value. + * Read to read critical delay difference from cs 1 to cs 2. + */ + int8_t cdd_rr_1_0; /* + * Byte offset 0x2d, CSR Addr 0x54016, Direction=Out + * This is a signed integer value. + * Read to read critical delay difference from cs 1 to cs 0. + */ + int8_t cdd_rr_0_3; /* + * Byte offset 0x2e, CSR Addr 0x54017, Direction=Out + * This is a signed integer value. + * Read to read critical delay difference from cs 0 to cs 3. + */ + int8_t cdd_rr_0_2; /* + * Byte offset 0x2f, CSR Addr 0x54017, Direction=Out + * This is a signed integer value. + * Read to read critical delay difference from cs 0 to cs 2. + */ + int8_t cdd_rr_0_1; /* + * Byte offset 0x30, CSR Addr 0x54018, Direction=Out + * This is a signed integer value. + * Read to read critical delay difference from cs 0 to cs 1. + */ + int8_t cdd_ww_3_2; /* + * Byte offset 0x31, CSR Addr 0x54018, Direction=Out + * This is a signed integer value. + * Write to write critical delay difference from cs 3 to cs + * 2. + */ + int8_t cdd_ww_3_1; /* + * Byte offset 0x32, CSR Addr 0x54019, Direction=Out + * This is a signed integer value. + * Write to write critical delay difference from cs 3 to cs + * 1. + */ + int8_t cdd_ww_3_0; /* + * Byte offset 0x33, CSR Addr 0x54019, Direction=Out + * This is a signed integer value. + * Write to write critical delay difference from cs 3 to cs + * 0. + */ + int8_t cdd_ww_2_3; /* + * Byte offset 0x34, CSR Addr 0x5401a, Direction=Out + * This is a signed integer value. + * Write to write critical delay difference from cs 2 to cs + * 3. + */ + int8_t cdd_ww_2_1; /* + * Byte offset 0x35, CSR Addr 0x5401a, Direction=Out + * This is a signed integer value. + * Write to write critical delay difference from cs 2 to cs + * 1. + */ + int8_t cdd_ww_2_0; /* + * Byte offset 0x36, CSR Addr 0x5401b, Direction=Out + * This is a signed integer value. + * Write to write critical delay difference from cs 2 to cs + * 0. + */ + int8_t cdd_ww_1_3; /* + * Byte offset 0x37, CSR Addr 0x5401b, Direction=Out + * This is a signed integer value. + * Write to write critical delay difference from cs 1 to cs + * 3. + */ + int8_t cdd_ww_1_2; /* + * Byte offset 0x38, CSR Addr 0x5401c, Direction=Out + * This is a signed integer value. + * Write to write critical delay difference from cs 1 to cs + * 2. + */ + int8_t cdd_ww_1_0; /* + * Byte offset 0x39, CSR Addr 0x5401c, Direction=Out + * This is a signed integer value. + * Write to write critical delay difference from cs 1 to cs + * 0. + */ + int8_t cdd_ww_0_3; /* + * Byte offset 0x3a, CSR Addr 0x5401d, Direction=Out + * This is a signed integer value. + * Write to write critical delay difference from cs 0 to cs + * 3. + */ + int8_t cdd_ww_0_2; /* + * Byte offset 0x3b, CSR Addr 0x5401d, Direction=Out + * This is a signed integer value. + * Write to write critical delay difference from cs 0 to cs + * 2. + */ + int8_t cdd_ww_0_1; /* + * Byte offset 0x3c, CSR Addr 0x5401e, Direction=Out + * This is a signed integer value. + * Write to write critical delay difference from cs 0 to cs + * 1. + */ + int8_t cdd_rw_3_3; /* + * Byte offset 0x3d, CSR Addr 0x5401e, Direction=Out + * This is a signed integer value. + * Read to write critical delay difference from cs 3 to + * cs 3. + */ + int8_t cdd_rw_3_2; /* + * Byte offset 0x3e, CSR Addr 0x5401f, Direction=Out + * This is a signed integer value. + * Read to write critical delay difference from cs 3 to + * cs 2. + */ + int8_t cdd_rw_3_1; /* + * Byte offset 0x3f, CSR Addr 0x5401f, Direction=Out + * This is a signed integer value. + * Read to write critical delay difference from cs 3 to + * cs 1. + */ + int8_t cdd_rw_3_0; /* + * Byte offset 0x40, CSR Addr 0x54020, Direction=Out + * This is a signed integer value. + * Read to write critical delay difference from cs 3 to + * cs 0. + */ + int8_t cdd_rw_2_3; /* + * Byte offset 0x41, CSR Addr 0x54020, Direction=Out + * This is a signed integer value. + * Read to write critical delay difference from cs 2 to + * cs 3. + */ + int8_t cdd_rw_2_2; /* + * Byte offset 0x42, CSR Addr 0x54021, Direction=Out + * This is a signed integer value. + * Read to write critical delay difference from cs 2 to + * cs 2. + */ + int8_t cdd_rw_2_1; /* + * Byte offset 0x43, CSR Addr 0x54021, Direction=Out + * This is a signed integer value. + * Read to write critical delay difference from cs 2 to + * cs 1. + */ + int8_t cdd_rw_2_0; /* + * Byte offset 0x44, CSR Addr 0x54022, Direction=Out + * This is a signed integer value. + * Read to write critical delay difference from cs 2 to + * cs 0. + */ + int8_t cdd_rw_1_3; /* + * Byte offset 0x45, CSR Addr 0x54022, Direction=Out + * This is a signed integer value. + * Read to write critical delay difference from cs 1 to + * cs 3. + */ + int8_t cdd_rw_1_2; /* + * Byte offset 0x46, CSR Addr 0x54023, Direction=Out + * This is a signed integer value. + * Read to write critical delay difference from cs 1 to + * cs 2. + */ + int8_t cdd_rw_1_1; /* + * Byte offset 0x47, CSR Addr 0x54023, Direction=Out + * This is a signed integer value. + * Read to write critical delay difference from cs 1 to + * cs 1. + */ + int8_t cdd_rw_1_0; /* + * Byte offset 0x48, CSR Addr 0x54024, Direction=Out + * This is a signed integer value. + * Read to write critical delay difference from cs 1 to + * cs 0. + */ + int8_t cdd_rw_0_3; /* + * Byte offset 0x49, CSR Addr 0x54024, Direction=Out + * This is a signed integer value. + * Read to write critical delay difference from cs 0 to + * cs 3. + */ + int8_t cdd_rw_0_2; /* + * Byte offset 0x4a, CSR Addr 0x54025, Direction=Out + * This is a signed integer value. + * Read to write critical delay difference from cs 0 to + * cs 2. + */ + int8_t cdd_rw_0_1; /* + * Byte offset 0x4b, CSR Addr 0x54025, Direction=Out + * This is a signed integer value. + * Read to write critical delay difference from cs 0 to + * cs 1. + */ + int8_t cdd_rw_0_0; /* + * Byte offset 0x4c, CSR Addr 0x54026, Direction=Out + * This is a signed integer value. + * Read to write critical delay difference from cs 0 to + * cs 0. + */ + int8_t cdd_wr_3_3; /* + * Byte offset 0x4d, CSR Addr 0x54026, Direction=Out + * This is a signed integer value. + * Write to read critical delay difference from cs 3 to + * cs 3. + */ + int8_t cdd_wr_3_2; /* + * Byte offset 0x4e, CSR Addr 0x54027, Direction=Out + * This is a signed integer value. + * Write to read critical delay difference from cs 3 to + * cs 2. + */ + int8_t cdd_wr_3_1; /* + * Byte offset 0x4f, CSR Addr 0x54027, Direction=Out + * This is a signed integer value. + * Write to read critical delay difference from cs 3 to + * cs 1. + */ + int8_t cdd_wr_3_0; /* + * Byte offset 0x50, CSR Addr 0x54028, Direction=Out + * This is a signed integer value. + * Write to read critical delay difference from cs 3 to + * cs 0. + */ + int8_t cdd_wr_2_3; /* + * Byte offset 0x51, CSR Addr 0x54028, Direction=Out + * This is a signed integer value. + * Write to read critical delay difference from cs 2 to + * cs 3. + */ + int8_t cdd_wr_2_2; /* + * Byte offset 0x52, CSR Addr 0x54029, Direction=Out + * This is a signed integer value. + * Write to read critical delay difference from cs 2 to + * cs 2. + */ + int8_t cdd_wr_2_1; /* + * Byte offset 0x53, CSR Addr 0x54029, Direction=Out + * This is a signed integer value. + * Write to read critical delay difference from cs 2 to + * cs 1. + */ + int8_t cdd_wr_2_0; /* + * Byte offset 0x54, CSR Addr 0x5402a, Direction=Out + * This is a signed integer value. + * Write to read critical delay difference from cs 2 to + * cs 0. + */ + int8_t cdd_wr_1_3; /* + * Byte offset 0x55, CSR Addr 0x5402a, Direction=Out + * This is a signed integer value. + * Write to read critical delay difference from cs 1 to + * cs 3. + */ + int8_t cdd_wr_1_2; /* + * Byte offset 0x56, CSR Addr 0x5402b, Direction=Out + * This is a signed integer value. + * Write to read critical delay difference from cs 1 to + * cs 2. + */ + int8_t cdd_wr_1_1; /* + * Byte offset 0x57, CSR Addr 0x5402b, Direction=Out + * This is a signed integer value. + * Write to read critical delay difference from cs 1 to + * cs 1. + */ + int8_t cdd_wr_1_0; /* + * Byte offset 0x58, CSR Addr 0x5402c, Direction=Out + * This is a signed integer value. + * Write to read critical delay difference from cs 1 to + * cs 0. + */ + int8_t cdd_wr_0_3; /* + * Byte offset 0x59, CSR Addr 0x5402c, Direction=Out + * This is a signed integer value. + * Write to read critical delay difference from cs 0 to + * cs 3. + */ + int8_t cdd_wr_0_2; /* + * Byte offset 0x5a, CSR Addr 0x5402d, Direction=Out + * This is a signed integer value. + * Write to read critical delay difference from cs 0 to + * cs 2. + */ + int8_t cdd_wr_0_1; /* + * Byte offset 0x5b, CSR Addr 0x5402d, Direction=Out + * This is a signed integer value. + * Write to read critical delay difference from cs 0 to + * cs 1. + */ + int8_t cdd_wr_0_0; /* + * Byte offset 0x5c, CSR Addr 0x5402e, Direction=Out + * This is a signed integer value. + * Write to read critical delay difference from cs 0 to + * cs 0. + */ + uint8_t reserved5d; /* + * Byte offset 0x5d, CSR Addr 0x5402e, Direction=In + * This field is reserved and must be programmed to 0x00, + * excepted for DDR4: + * By default, if this parameter is 0, the offset applied at + * the end of DDR4 RxEn training resulting in the trained + * RxEnDly is 3/8 of the RX preamble width; if reserved5D is + * non zero, this offset is used instead (in fine step). + */ + uint16_t mr0; /* + * Byte offset 0x5e, CSR Addr 0x5402f, Direction=In + * Value of DDR mode register mr0 for all ranks for current + * pstate. + */ + uint16_t mr1; /* + * Byte offset 0x60, CSR Addr 0x54030, Direction=In + * Value of DDR mode register mr1 for all ranks for current + * pstate. + */ + uint16_t mr2; /* + * Byte offset 0x62, CSR Addr 0x54031, Direction=In + * Value of DDR mode register mr2 for all ranks for current + * pstate. + */ + uint16_t mr3; /* + * Byte offset 0x64, CSR Addr 0x54032, Direction=In + * Value of DDR mode register mr3 for all ranks for current + * pstate. + */ + uint16_t mr4; /* + * Byte offset 0x66, CSR Addr 0x54033, Direction=In + * Value of DDR mode register mr4 for all ranks for current + * pstate. + */ + uint16_t mr5; /* + * Byte offset 0x68, CSR Addr 0x54034, Direction=In + * Value of DDR mode register mr5 for all ranks for current + * pstate. + */ + uint16_t mr6; /* + * Byte offset 0x6a, CSR Addr 0x54035, Direction=In + * Value of DDR mode register mr6 for all ranks for current + * pstate. Note: The initial VrefDq value and range must be + * set in A6:A0. + */ + uint8_t x16present; /* + * Byte offset 0x6c, CSR Addr 0x54036, Direction=In + * X16 device map. Corresponds to CS[3:0]. + * x16present[0] = CS0 is populated with X16 devices + * x16present[1] = CS1 is populated with X16 devices + * x16present[2] = CS2 is populated with X16 devices + * x16present[3] = CS3 is populated with X16 devices + * x16present[7:4] = Reserved (must be programmed to 0) + * + * Ranks may not contain mixed device types. + */ + uint8_t cssetupgddec; /* + * Byte offset 0x6d, CSR Addr 0x54036, Direction=In + * controls timing of chip select signals when DDR4 + * gear-down mode is active + * 0 - Leave delay of chip select timing group signal + * the same both before and after gear-down sync occurs + * 1 - Add 1UI of delay to chip select timing group + * signals when geardown-mode is active. This allows CS + * signals to have equal setup and hold time in gear-down + * mode + */ + uint16_t rtt_nom_wr_park0; /* + * Byte offset 0x6e, CSR Addr 0x54037, Direction=In + * Optional RTT_NOM, RTT_WR and RTT_PARK values for rank 0 + * DRAM: + * rtt_nom_wr_park0[0] = 1: Option is enable (otherwise, + * remaining bit fields are don't care) + * rtt_nom_wr_park0[5:3]: Optional RTT_NOM value to be used + * in mr1[10:8] for rank 0 + * rtt_nom_wr_park0[11:9]: Optional RTT_WR value to be used + * in mr2[11:9] for rank 0 + * rtt_nom_wr_park0[8:6]: Optional RTT_PARK value to be used + * in mr5[8:6] for rank 0 + */ + uint16_t rtt_nom_wr_park1; /* + * Byte offset 0x70, CSR Addr 0x54038, Direction=In + * Optional RTT_NOM, RTT_WR and RTT_PARK values for rank 1 + * DRAM: + * rtt_nom_wr_park1[0] = 1: Option is enable (otherwise, + * remaining bit fields are don't care) + * rtt_nom_wr_park1[5:3]: Optional RTT_NOM value to be used + * in mr1[10:8] for rank 1 + * rtt_nom_wr_park1[11:9]: Optional RTT_WR value to be used + * in mr2[11:9] for rank 1 + * rtt_nom_wr_park1[8:6]: Optional RTT_PARK value to be used + * in mr5[8:6] for rank 1 + */ + uint16_t rtt_nom_wr_park2; /* + * Byte offset 0x72, CSR Addr 0x54039, Direction=In + * Optional RTT_NOM, RTT_WR and RTT_PARK values for rank 2 + * DRAM: + * rtt_nom_wr_park2[0] = 1: Option is enable (otherwise, + * remaining bit fields are don't care) + * rtt_nom_wr_park2[5:3]: Optional RTT_NOM value to be used + * in mr1[10:8] for rank 2 + * rtt_nom_wr_park2[11:9]: Optional RTT_WR value to be used + * in mr2[11:9] for rank 2 + * rtt_nom_wr_park2[8:6]: Optional RTT_PARK value to be used + * in mr5[8:6] for rank 2 + */ + uint16_t rtt_nom_wr_park3; /* + * Byte offset 0x74, CSR Addr 0x5403a, Direction=In + * Optional RTT_NOM, RTT_WR and RTT_PARK values for rank 3 + * DRAM: + * rtt_nom_wr_park3[0] = 1: Option is enable (otherwise, + * remaining bit fields are don't care) + * rtt_nom_wr_park3[5:3]: Optional RTT_NOM value to be used + * in mr1[10:8] for rank 3 + * rtt_nom_wr_park3[11:9]: Optional RTT_WR value to be used + * in mr2[11:9] for rank 3 + * rtt_nom_wr_park3[8:6]: Optional RTT_PARK value to be used + * in mr5[8:6] for rank 3 + */ + uint16_t rtt_nom_wr_park4; /* + * Byte offset 0x76, CSR Addr 0x5403b, Direction=In + * Optional RTT_NOM, RTT_WR and RTT_PARK values for rank 4 + * DRAM: + * rtt_nom_wr_park4[0] = 1: Option is enable (otherwise, + * remaining bit fields are don't care) + * rtt_nom_wr_park4[5:3]: Optional RTT_NOM value to be used + * in mr1[10:8] for rank 4 + * rtt_nom_wr_park4[11:9]: Optional RTT_WR value to be used + * in mr2[11:9] for rank 4 + * rtt_nom_wr_park4[8:6]: Optional RTT_PARK value to be used + * in mr5[8:6] for rank 4 + */ + uint16_t rtt_nom_wr_park5; /* + * Byte offset 0x78, CSR Addr 0x5403c, Direction=In + * Optional RTT_NOM, RTT_WR and RTT_PARK values for rank 5 + * DRAM: + * rtt_nom_wr_park5[0] = 1: Option is enable (otherwise, + * remaining bit fields are don't care) + * rtt_nom_wr_park5[5:3]: Optional RTT_NOM value to be used + * in mr1[10:8] for rank 5 + * rtt_nom_wr_park5[11:9]: Optional RTT_WR value to be used + * in mr2[11:9] for rank 5 + * rtt_nom_wr_park5[8:6]: Optional RTT_PARK value to be used + * in mr5[8:6] for rank 5 + */ + uint16_t rtt_nom_wr_park6; /* + * Byte offset 0x7a, CSR Addr 0x5403d, Direction=In + * Optional RTT_NOM, RTT_WR and RTT_PARK values for rank 6 + * DRAM: + * rtt_nom_wr_park6[0] = 1: Option is enable (otherwise, + * remaining bit fields are don't care) + * rtt_nom_wr_park6[5:3]: Optional RTT_NOM value to be used + * in mr1[10:8] for rank 6 + * rtt_nom_wr_park6[11:9]: Optional RTT_WR value to be used + * in mr2[11:9] for rank 6 + * rtt_nom_wr_park6[8:6]: Optional RTT_PARK value to be used + * in mr5[8:6] for rank 6 + */ + uint16_t rtt_nom_wr_park7; /* + * Byte offset 0x7c, CSR Addr 0x5403e, Direction=In + * Optional RTT_NOM, RTT_WR and RTT_PARK values for rank 7 + * DRAM: + * rtt_nom_wr_park7[0] = 1: Option is enable (otherwise, + * remaining bit fields are don't care) + * rtt_nom_wr_park7[5:3]: Optional RTT_NOM value to be used + * in mr1[10:8] for rank 7 + * rtt_nom_wr_park7[11:9]: Optional RTT_WR value to be used + * in mr2[11:9] for rank 7 + * rtt_nom_wr_park7[8:6]: Optional RTT_PARK value to be used + * in mr5[8:6] for rank 7 + */ + uint8_t acsmodtctrl0; /* + * Byte offset 0x7e, CSR Addr 0x5403f, Direction=In + * Odt pattern for accesses targeting rank 0. [3:0] is used + * for write ODT [7:4] is used for read ODT + */ + uint8_t acsmodtctrl1; /* + * Byte offset 0x7f, CSR Addr 0x5403f, Direction=In + * Odt pattern for accesses targeting rank 1. [3:0] is used + * for write ODT [7:4] is used for read ODT + */ + uint8_t acsmodtctrl2; /* + * Byte offset 0x80, CSR Addr 0x54040, Direction=In + * Odt pattern for accesses targeting rank 2. [3:0] is used + * for write ODT [7:4] is used for read ODT + */ + uint8_t acsmodtctrl3; /* + * Byte offset 0x81, CSR Addr 0x54040, Direction=In + * Odt pattern for accesses targeting rank 3. [3:0] is used + * for write ODT [7:4] is used for read ODT + */ + uint8_t acsmodtctrl4; /* + * Byte offset 0x82, CSR Addr 0x54041, Direction=In + * Odt pattern for accesses targeting rank 4. [3:0] is used + * for write ODT [7:4] is used for read ODT + */ + uint8_t acsmodtctrl5; /* + * Byte offset 0x83, CSR Addr 0x54041, Direction=In + * Odt pattern for accesses targeting rank 5. [3:0] is used + * for write ODT [7:4] is used for read ODT + */ + uint8_t acsmodtctrl6; /* + * Byte offset 0x84, CSR Addr 0x54042, Direction=In + * Odt pattern for accesses targeting rank 6. [3:0] is used + * for write ODT [7:4] is used for read ODT + */ + uint8_t acsmodtctrl7; /* + * Byte offset 0x85, CSR Addr 0x54042, Direction=In + * Odt pattern for accesses targeting rank 7. [3:0] is used + * for write ODT [7:4] is used for read ODT + */ + uint8_t vrefdqr0nib0; /* + * Byte offset 0x86, CSR Addr 0x54043, Direction=InOut + * VrefDq for rank 0 nibble 0. Specifies mr6[6:0] + */ + uint8_t vrefdqr0nib1; /* + * Byte offset 0x87, CSR Addr 0x54043, Direction=InOut + * VrefDq for rank 0 nibble 1. Specifies mr6[6:0]. + * Identical to vrefdqr0nib0 for x8 or x16 devices. + */ + uint8_t vrefdqr0nib2; /* + * Byte offset 0x88, CSR Addr 0x54044, Direction=InOut + * VrefDq for rank 0 nibble 2. Specifies mr6[6:0]. + * Identical to vrefdqr0nib0 for x16 devices. + */ + uint8_t vrefdqr0nib3; /* + * Byte offset 0x89, CSR Addr 0x54044, Direction=InOut + * VrefDq for rank 0 nibble 3. Specifies mr6[6:0]. + * Identical to vrefdqr0nib0 for x16 devices, or + * vrefdqr0nib2 for x8 devices. + */ + uint8_t vrefdqr0nib4; /* + * Byte offset 0x8a, CSR Addr 0x54045, Direction=InOut + * VrefDq for rank 0 nibble 4. Specifies mr6[6:0] + */ + uint8_t vrefdqr0nib5; /* + * Byte offset 0x8b, CSR Addr 0x54045, Direction=InOut + * VrefDq for rank 0 nibble 5. Specifies mr6[6:0]. + * Identical to vrefdqr0nib4 for x8 or x16 devices. + */ + uint8_t vrefdqr0nib6; /* + * Byte offset 0x8c, CSR Addr 0x54046, Direction=InOut + * VrefDq for rank 0 nibble 6. Specifies mr6[6:0]. + * Identical to vrefdqr0nib4 for x16 devices. + */ + uint8_t vrefdqr0nib7; /* + * Byte offset 0x8d, CSR Addr 0x54046, Direction=InOut + * VrefDq for rank 0 nibble 7. Specifies mr6[6:0]. + * Identical to vrefdqr0nib4 for x16 devices, + * or vrefdqr0nib6 for x8 devices. + */ + uint8_t vrefdqr0nib8; /* + * Byte offset 0x8e, CSR Addr 0x54047, Direction=InOut + * VrefDq for rank 0 nibble 8. Specifies mr6[6:0] + */ + uint8_t vrefdqr0nib9; /* + * Byte offset 0x8f, CSR Addr 0x54047, Direction=InOut + * VrefDq for rank 0 nibble 9. Specifies mr6[6:0]. + * Identical to vrefdqr0nib8 for x8 or x16 devices. + */ + uint8_t vrefdqr0nib10; /* + * Byte offset 0x90, CSR Addr 0x54048, Direction=InOut + * VrefDq for rank 0 nibble 10. Specifies mr6[6:0]. + * Identical to vrefdqr0nib8 for x16 devices. + */ + uint8_t vrefdqr0nib11; /* + * Byte offset 0x91, CSR Addr 0x54048, Direction=InOut + * VrefDq for rank 0 nibble 11. Specifies mr6[6:0]. + * Identical to vrefdqr0nib8 for x16 devices, + * or vrefdqr0nib10 for x8 devices. + */ + uint8_t vrefdqr0nib12; /* + * Byte offset 0x92, CSR Addr 0x54049, Direction=InOut + * VrefDq for rank 0 nibble 12. Specifies mr6[6:0] + */ + uint8_t vrefdqr0nib13; /* + * Byte offset 0x93, CSR Addr 0x54049, Direction=InOut + * VrefDq for rank 0 nibble 13. Specifies mr6[6:0]. + * Identical to vrefdqr0nib12 for x8 or x16 devices. + */ + uint8_t vrefdqr0nib14; /* + * Byte offset 0x94, CSR Addr 0x5404a, Direction=InOut + * VrefDq for rank 0 nibble 14. Specifies mr6[6:0]. + * Identical to vrefdqr0nib12 for x16 devices. + */ + uint8_t vrefdqr0nib15; /* + * Byte offset 0x95, CSR Addr 0x5404a, Direction=InOut + * VrefDq for rank 0 nibble 15. Specifies mr6[6:0]. + * Identical to vrefdqr0nib12 for x16 devices, + * or vrefdqr0nib14 for x8 devices. + */ + uint8_t vrefdqr0nib16; /* + * Byte offset 0x96, CSR Addr 0x5404b, Direction=InOut + * VrefDq for rank 0 nibble 16. Specifies mr6[6:0] + */ + uint8_t vrefdqr0nib17; /* + * Byte offset 0x97, CSR Addr 0x5404b, Direction=InOut + * VrefDq for rank 0 nibble 17. Specifies mr6[6:0]. + * Identical to vrefdqr0nib16 for x8 or x16 devices. + */ + uint8_t vrefdqr0nib18; /* + * Byte offset 0x98, CSR Addr 0x5404c, Direction=InOut + * VrefDq for rank 0 nibble 18. Specifies mr6[6:0]. + * Identical to vrefdqr0nib16 for x16 devices. + */ + uint8_t vrefdqr0nib19; /* + * Byte offset 0x99, CSR Addr 0x5404c, Direction=InOut + * VrefDq for rank 0 nibble 19. Specifies mr6[6:0]. + * Identical to vrefdqr0nib16 for x16 devices, + * or vrefdqr0nib18 for x8 devices. + */ + uint8_t vrefdqr1nib0; /* + * Byte offset 0x9a, CSR Addr 0x5404d, Direction=InOut + * VrefDq for rank 1 nibble 0. Specifies mr6[6:0] + */ + uint8_t vrefdqr1nib1; /* + * Byte offset 0x9b, CSR Addr 0x5404d, Direction=InOut + * VrefDq for rank 1 nibble 1. Specifies mr6[6:0]. + * Identical to vrefdqr1nib0 for x8 or x16 devices. + */ + uint8_t vrefdqr1nib2; /* + * Byte offset 0x9c, CSR Addr 0x5404e, Direction=InOut + * VrefDq for rank 1 nibble 2. Specifies mr6[6:0]. + * Identical to vrefdqr1nib0 for x16 devices. + */ + uint8_t vrefdqr1nib3; /* + * Byte offset 0x9d, CSR Addr 0x5404e, Direction=InOut + * VrefDq for rank 1 nibble 3. Specifies mr6[6:0]. + * Identical to vrefdqr1nib0 for x16 devices, + * or vrefdqr1nib2 for x8 devices. + */ + uint8_t vrefdqr1nib4; /* + * Byte offset 0x9e, CSR Addr 0x5404f, Direction=InOut + * VrefDq for rank 1 nibble 4. Specifies mr6[6:0] + */ + uint8_t vrefdqr1nib5; /* + * Byte offset 0x9f, CSR Addr 0x5404f, Direction=InOut + * VrefDq for rank 1 nibble 5. Specifies mr6[6:0]. + * Identical to vrefdqr1nib4 for x8 or x16 devices. + */ + uint8_t vrefdqr1nib6; /* + * Byte offset 0xa0, CSR Addr 0x54050, Direction=InOut + * VrefDq for rank 1 nibble 6. Specifies mr6[6:0]. + * Identical to vrefdqr1nib4 for x16 devices. + */ + uint8_t vrefdqr1nib7; /* + * Byte offset 0xa1, CSR Addr 0x54050, Direction=InOut + * VrefDq for rank 1 nibble 7. Specifies mr6[6:0]. + * Identical to vrefdqr1nib4 for x16 devices, + * or vrefdqr1nib6 for x8 devices. + */ + uint8_t vrefdqr1nib8; /* + * Byte offset 0xa2, CSR Addr 0x54051, Direction=InOut + * VrefDq for rank 1 nibble 8. Specifies mr6[6:0] + */ + uint8_t vrefdqr1nib9; /* + * Byte offset 0xa3, CSR Addr 0x54051, Direction=InOut + * VrefDq for rank 1 nibble 9. Specifies mr6[6:0]. + * Identical to vrefdqr1nib8 for x8 or x16 devices. + */ + uint8_t vrefdqr1nib10; /* + * Byte offset 0xa4, CSR Addr 0x54052, Direction=InOut + * VrefDq for rank 1 nibble 10. Specifies mr6[6:0]. + * Identical to vrefdqr1nib8 for x16 devices. + */ + uint8_t vrefdqr1nib11; /* + * Byte offset 0xa5, CSR Addr 0x54052, Direction=InOut + * VrefDq for rank 1 nibble 11. Specifies mr6[6:0]. + * Identical to vrefdqr1nib8 for x16 devices, + * or vrefdqr1nib10 for x8 devices. + */ + uint8_t vrefdqr1nib12; /* + * Byte offset 0xa6, CSR Addr 0x54053, Direction=InOut + * VrefDq for rank 1 nibble 12. Specifies mr6[6:0] + */ + uint8_t vrefdqr1nib13; /* + * Byte offset 0xa7, CSR Addr 0x54053, Direction=InOut + * VrefDq for rank 1 nibble 13. Specifies mr6[6:0]. + * Identical to vrefdqr1nib12 for x8 or x16 devices. + */ + uint8_t vrefdqr1nib14; /* + * Byte offset 0xa8, CSR Addr 0x54054, Direction=InOut + * VrefDq for rank 1 nibble 14. Specifies mr6[6:0]. + * Identical to vrefdqr1nib12 for x16 devices. + */ + uint8_t vrefdqr1nib15; /* + * Byte offset 0xa9, CSR Addr 0x54054, Direction=InOut + * VrefDq for rank 1 nibble 15. Specifies mr6[6:0]. + * Identical to vrefdqr1nib12 for x16 devices, + * or vrefdqr1nib14 for x8 devices. + */ + uint8_t vrefdqr1nib16; /* + * Byte offset 0xaa, CSR Addr 0x54055, Direction=InOut + * VrefDq for rank 1 nibble 16. Specifies mr6[6:0] + */ + uint8_t vrefdqr1nib17; /* + * Byte offset 0xab, CSR Addr 0x54055, Direction=InOut + * VrefDq for rank 1 nibble 17. Specifies mr6[6:0]. + * Identical to vrefdqr1nib16 for x8 or x16 devices. + */ + uint8_t vrefdqr1nib18; /* + * Byte offset 0xac, CSR Addr 0x54056, Direction=InOut + * VrefDq for rank 1 nibble 18. Specifies mr6[6:0]. + * Identical to vrefdqr1nib16 for x16 devices. + */ + uint8_t vrefdqr1nib19; /* + * Byte offset 0xad, CSR Addr 0x54056, Direction=InOut + * VrefDq for rank 1 nibble 19. Specifies mr6[6:0]. + * Identical to vrefdqr1nib16 for x16 devices, + * or vrefdqr1nib18 for x8 devices. + */ + uint8_t vrefdqr2nib0; /* + * Byte offset 0xae, CSR Addr 0x54057, Direction=InOut + * VrefDq for rank 2 nibble 0. Specifies mr6[6:0] + */ + uint8_t vrefdqr2nib1; /* + * Byte offset 0xaf, CSR Addr 0x54057, Direction=InOut + * VrefDq for rank 2 nibble 1. Specifies mr6[6:0]. + * Identical to vrefdqr2nib0 for x8 or x16 devices. + */ + uint8_t vrefdqr2nib2; /* + * Byte offset 0xb0, CSR Addr 0x54058, Direction=InOut + * VrefDq for rank 2 nibble 2. Specifies mr6[6:0]. + * Identical to vrefdqr2nib0 for x16 devices. + */ + uint8_t vrefdqr2nib3; /* + * Byte offset 0xb1, CSR Addr 0x54058, Direction=InOut + * VrefDq for rank 2 nibble 3. Specifies mr6[6:0]. + * Identical to vrefdqr2nib0 for x16 devices, + * or vrefdqr2nib2 for x8 devices. + */ + uint8_t vrefdqr2nib4; /* + * Byte offset 0xb2, CSR Addr 0x54059, Direction=InOut + * VrefDq for rank 2 nibble 4. Specifies mr6[6:0] + */ + uint8_t vrefdqr2nib5; /* + * Byte offset 0xb3, CSR Addr 0x54059, Direction=InOut + * VrefDq for rank 2 nibble 5. Specifies mr6[6:0]. + * Identical to vrefdqr2nib4 for x8 or x16 devices. + */ + uint8_t vrefdqr2nib6; /* + * Byte offset 0xb4, CSR Addr 0x5405a, Direction=InOut + * VrefDq for rank 2 nibble 6. Specifies mr6[6:0]. + * Identical to vrefdqr2nib4 for x16 devices. + */ + uint8_t vrefdqr2nib7; /* + * Byte offset 0xb5, CSR Addr 0x5405a, Direction=InOut + * VrefDq for rank 2 nibble 7. Specifies mr6[6:0]. + * Identical to vrefdqr2nib4 for x16 devices, + * or vrefdqr2nib6 for x8 devices. + */ + uint8_t vrefdqr2nib8; /* + * Byte offset 0xb6, CSR Addr 0x5405b, Direction=InOut + * VrefDq for rank 2 nibble 8. Specifies mr6[6:0] + */ + uint8_t vrefdqr2nib9; /* + * Byte offset 0xb7, CSR Addr 0x5405b, Direction=InOut + * VrefDq for rank 2 nibble 9. Specifies mr6[6:0]. + * Identical to vrefdqr2nib8 for x8 or x16 devices. + */ + uint8_t vrefdqr2nib10; /* + * Byte offset 0xb8, CSR Addr 0x5405c, Direction=InOut + * VrefDq for rank 2 nibble 10. Specifies mr6[6:0]. + * Identical to vrefdqr2nib8 for x16 devices. + */ + uint8_t vrefdqr2nib11; /* + * Byte offset 0xb9, CSR Addr 0x5405c, Direction=InOut + * VrefDq for rank 2 nibble 11. Specifies mr6[6:0]. + * Identical to vrefdqr2nib8 for x16 devices, + * or vrefdqr2nib10 for x8 devices. + */ + uint8_t vrefdqr2nib12; /* + * Byte offset 0xba, CSR Addr 0x5405d, Direction=InOut + * VrefDq for rank 2 nibble 12. Specifies mr6[6:0] + */ + uint8_t vrefdqr2nib13; /* + * Byte offset 0xbb, CSR Addr 0x5405d, Direction=InOut + * VrefDq for rank 2 nibble 13. Specifies mr6[6:0]. + * Identical to vrefdqr2nib12 for x8 or x16 devices. + */ + uint8_t vrefdqr2nib14; /* + * Byte offset 0xbc, CSR Addr 0x5405e, Direction=InOut + * VrefDq for rank 2 nibble 14. Specifies mr6[6:0]. + * Identical to vrefdqr2nib12 for x16 devices. + */ + uint8_t vrefdqr2nib15; /* + * Byte offset 0xbd, CSR Addr 0x5405e, Direction=InOut + * VrefDq for rank 2 nibble 15. Specifies mr6[6:0]. + * Identical to vrefdqr2nib12 for x16 devices, + * or vrefdqr2nib14 for x8 devices. + */ + uint8_t vrefdqr2nib16; /* + * Byte offset 0xbe, CSR Addr 0x5405f, Direction=InOut + * VrefDq for rank 2 nibble 16. Specifies mr6[6:0] + */ + uint8_t vrefdqr2nib17; /* + * Byte offset 0xbf, CSR Addr 0x5405f, Direction=InOut + * VrefDq for rank 2 nibble 17. Specifies mr6[6:0]. + * Identical to vrefdqr2nib16 for x8 or x16 devices. + */ + uint8_t vrefdqr2nib18; /* + * Byte offset 0xc0, CSR Addr 0x54060, Direction=InOut + * VrefDq for rank 2 nibble 18. Specifies mr6[6:0]. + * Identical to vrefdqr2nib16 for x16 devices. + */ + uint8_t vrefdqr2nib19; /* + * Byte offset 0xc1, CSR Addr 0x54060, Direction=InOut + * VrefDq for rank 2 nibble 19. Specifies mr6[6:0]. + * Identical to vrefdqr2nib16 for x16 devices, + * or vrefdqr2nib18 for x8 devices. + */ + uint8_t vrefdqr3nib0; /* + * Byte offset 0xc2, CSR Addr 0x54061, Direction=InOut + * VrefDq for rank 3 nibble 0. Specifies mr6[6:0] + */ + uint8_t vrefdqr3nib1; /* + * Byte offset 0xc3, CSR Addr 0x54061, Direction=InOut + * VrefDq for rank 3 nibble 1. Specifies mr6[6:0]. + * Identical to vrefdqr3nib0 for x8 or x16 devices. + */ + uint8_t vrefdqr3nib2; /* + * Byte offset 0xc4, CSR Addr 0x54062, Direction=InOut + * VrefDq for rank 3 nibble 2. Specifies mr6[6:0]. + * Identical to vrefdqr3nib0 for x16 devices. + */ + uint8_t vrefdqr3nib3; /* + * Byte offset 0xc5, CSR Addr 0x54062, Direction=InOut + * VrefDq for rank 3 nibble 3. Specifies mr6[6:0]. + * Identical to vrefdqr3nib0 for x16 devices, + * or vrefdqr3nib2 for x8 devices. + */ + uint8_t vrefdqr3nib4; /* + * Byte offset 0xc6, CSR Addr 0x54063, Direction=InOut + * VrefDq for rank 3 nibble 4. Specifies mr6[6:0] + */ + uint8_t vrefdqr3nib5; /* + * Byte offset 0xc7, CSR Addr 0x54063, Direction=InOut + * VrefDq for rank 3 nibble 5. Specifies mr6[6:0]. + * Identical to vrefdqr3nib4 for x8 or x16 devices. + */ + uint8_t vrefdqr3nib6; /* + * Byte offset 0xc8, CSR Addr 0x54064, Direction=InOut + * VrefDq for rank 3 nibble 6. Specifies mr6[6:0]. + * Identical to vrefdqr3nib4 for x16 devices. + */ + uint8_t vrefdqr3nib7; /* + * Byte offset 0xc9, CSR Addr 0x54064, Direction=InOut + * VrefDq for rank 3 nibble 7. Specifies mr6[6:0]. + * Identical to vrefdqr3nib4 for x16 devices, + * or vrefdqr3nib6 for x8 devices. + */ + uint8_t vrefdqr3nib8; /* + * Byte offset 0xca, CSR Addr 0x54065, Direction=InOut + * VrefDq for rank 3 nibble 8. Specifies mr6[6:0] + */ + uint8_t vrefdqr3nib9; /* + * Byte offset 0xcb, CSR Addr 0x54065, Direction=InOut + * VrefDq for rank 3 nibble 9. Specifies mr6[6:0]. + * Identical to vrefdqr3nib8 for x8 or x16 devices. + */ + uint8_t vrefdqr3nib10; /* + * Byte offset 0xcc, CSR Addr 0x54066, Direction=InOut + * VrefDq for rank 3 nibble 10. Specifies mr6[6:0]. + * Identical to vrefdqr3nib8 for x16 devices. + */ + uint8_t vrefdqr3nib11; /* + * Byte offset 0xcd, CSR Addr 0x54066, Direction=InOut + * VrefDq for rank 3 nibble 11. Specifies mr6[6:0]. + * Identical to vrefdqr3nib8 for x16 devices, + * or vrefdqr3nib10 for x8 devices. + */ + uint8_t vrefdqr3nib12; /* + * Byte offset 0xce, CSR Addr 0x54067, Direction=InOut + * VrefDq for rank 3 nibble 12. Specifies mr6[6:0] + */ + uint8_t vrefdqr3nib13; /* + * Byte offset 0xcf, CSR Addr 0x54067, Direction=InOut + * VrefDq for rank 3 nibble 13. Specifies mr6[6:0]. + * Identical to vrefdqr3nib12 for x8 or x16 devices. + */ + uint8_t vrefdqr3nib14; /* + * Byte offset 0xd0, CSR Addr 0x54068, Direction=InOut + * VrefDq for rank 3 nibble 14. Specifies mr6[6:0]. + * Identical to vrefdqr3nib12 for x16 devices. + */ + uint8_t vrefdqr3nib15; /* + * Byte offset 0xd1, CSR Addr 0x54068, Direction=InOut + * VrefDq for rank 3 nibble 15. Specifies mr6[6:0]. + * Identical to vrefdqr3nib12 for x16 devices, + * or vrefdqr3nib14 for x8 devices. + */ + uint8_t vrefdqr3nib16; /* + * Byte offset 0xd2, CSR Addr 0x54069, Direction=InOut + * VrefDq for rank 3 nibble 16. Specifies mr6[6:0] + */ + uint8_t vrefdqr3nib17; /* + * Byte offset 0xd3, CSR Addr 0x54069, Direction=InOut + * VrefDq for rank 3 nibble 17. Specifies mr6[6:0]. + * Identical to vrefdqr3nib16 for x8 or x16 devices. + */ + uint8_t vrefdqr3nib18; /* + * Byte offset 0xd4, CSR Addr 0x5406a, Direction=InOut + * VrefDq for rank 3 nibble 18. Specifies mr6[6:0]. + * Identical to vrefdqr3nib16 for x16 devices. + */ + uint8_t vrefdqr3nib19; /* + * Byte offset 0xd5, CSR Addr 0x5406a, Direction=InOut + * VrefDq for rank 3 nibble 19. Specifies mr6[6:0]. + * Identical to vrefdqr3nib16 for x16 devices, + * or vrefdqr3nib18 for x8 devices. + */ + uint8_t reservedd6; /* Byte offset 0xd6, CSR Addr 0x5406b, Direction=N/A */ + uint8_t reservedd7; /* Byte offset 0xd7, CSR Addr 0x5406b, Direction=N/A */ + uint8_t reservedd8; /* Byte offset 0xd8, CSR Addr 0x5406c, Direction=N/A */ + uint8_t reservedd9; /* Byte offset 0xd9, CSR Addr 0x5406c, Direction=N/A */ + uint8_t reservedda; /* Byte offset 0xda, CSR Addr 0x5406d, Direction=N/A */ + uint8_t reserveddb; /* Byte offset 0xdb, CSR Addr 0x5406d, Direction=N/A */ + uint8_t reserveddc; /* Byte offset 0xdc, CSR Addr 0x5406e, Direction=N/A */ + uint8_t reserveddd; /* Byte offset 0xdd, CSR Addr 0x5406e, Direction=N/A */ + uint8_t reservedde; /* Byte offset 0xde, CSR Addr 0x5406f, Direction=N/A */ + uint8_t reserveddf; /* Byte offset 0xdf, CSR Addr 0x5406f, Direction=N/A */ + uint8_t reservede0; /* Byte offset 0xe0, CSR Addr 0x54070, Direction=N/A */ + uint8_t reservede1; /* Byte offset 0xe1, CSR Addr 0x54070, Direction=N/A */ + uint8_t reservede2; /* Byte offset 0xe2, CSR Addr 0x54071, Direction=N/A */ + uint8_t reservede3; /* Byte offset 0xe3, CSR Addr 0x54071, Direction=N/A */ + uint8_t reservede4; /* Byte offset 0xe4, CSR Addr 0x54072, Direction=N/A */ + uint8_t reservede5; /* Byte offset 0xe5, CSR Addr 0x54072, Direction=N/A */ + uint8_t reservede6; /* Byte offset 0xe6, CSR Addr 0x54073, Direction=N/A */ + uint8_t reservede7; /* Byte offset 0xe7, CSR Addr 0x54073, Direction=N/A */ + uint8_t reservede8; /* Byte offset 0xe8, CSR Addr 0x54074, Direction=N/A */ + uint8_t reservede9; /* Byte offset 0xe9, CSR Addr 0x54074, Direction=N/A */ + uint8_t reservedea; /* Byte offset 0xea, CSR Addr 0x54075, Direction=N/A */ + uint8_t reservedeb; /* Byte offset 0xeb, CSR Addr 0x54075, Direction=N/A */ + uint8_t reservedec; /* Byte offset 0xec, CSR Addr 0x54076, Direction=N/A */ + uint8_t reserveded; /* Byte offset 0xed, CSR Addr 0x54076, Direction=N/A */ + uint8_t reservedee; /* Byte offset 0xee, CSR Addr 0x54077, Direction=N/A */ + uint8_t reservedef; /* Byte offset 0xef, CSR Addr 0x54077, Direction=N/A */ + uint8_t reservedf0; /* Byte offset 0xf0, CSR Addr 0x54078, Direction=N/A */ + uint8_t reservedf1; /* Byte offset 0xf1, CSR Addr 0x54078, Direction=N/A */ + uint8_t reservedf2; /* Byte offset 0xf2, CSR Addr 0x54079, Direction=N/A */ + uint8_t reservedf3; /* Byte offset 0xf3, CSR Addr 0x54079, Direction=N/A */ + uint8_t reservedf4; /* Byte offset 0xf4, CSR Addr 0x5407a, Direction=N/A */ + uint8_t reservedf5; /* Byte offset 0xf5, CSR Addr 0x5407a, Direction=N/A */ + uint8_t reservedf6; /* Byte offset 0xf6, CSR Addr 0x5407b, Direction=N/A */ + uint8_t reservedf7; /* Byte offset 0xf7, CSR Addr 0x5407b, Direction=N/A */ + uint8_t reservedf8; /* Byte offset 0xf8, CSR Addr 0x5407c, Direction=N/A */ + uint8_t reservedf9; /* Byte offset 0xf9, CSR Addr 0x5407c, Direction=N/A */ + uint8_t reservedfa; /* Byte offset 0xfa, CSR Addr 0x5407d, Direction=N/A */ + uint8_t reservedfb; /* Byte offset 0xfb, CSR Addr 0x5407d, Direction=N/A */ + uint8_t reservedfc; /* Byte offset 0xfc, CSR Addr 0x5407e, Direction=N/A */ + uint8_t reservedfd; /* Byte offset 0xfd, CSR Addr 0x5407e, Direction=N/A */ + uint8_t reservedfe; /* Byte offset 0xfe, CSR Addr 0x5407f, Direction=N/A */ + uint8_t reservedff; /* Byte offset 0xff, CSR Addr 0x5407f, Direction=N/A */ + uint8_t reserved100; /* Byte offset 0x100, CSR Addr 0x54080, Direction=N/A */ + uint8_t reserved101; /* Byte offset 0x101, CSR Addr 0x54080, Direction=N/A */ + uint8_t reserved102; /* Byte offset 0x102, CSR Addr 0x54081, Direction=N/A */ + uint8_t reserved103; /* Byte offset 0x103, CSR Addr 0x54081, Direction=N/A */ + uint8_t reserved104; /* Byte offset 0x104, CSR Addr 0x54082, Direction=N/A */ + uint8_t reserved105; /* Byte offset 0x105, CSR Addr 0x54082, Direction=N/A */ + uint8_t reserved106; /* Byte offset 0x106, CSR Addr 0x54083, Direction=N/A */ + uint8_t reserved107; /* Byte offset 0x107, CSR Addr 0x54083, Direction=N/A */ + uint8_t reserved108; /* Byte offset 0x108, CSR Addr 0x54084, Direction=N/A */ + uint8_t reserved109; /* Byte offset 0x109, CSR Addr 0x54084, Direction=N/A */ + uint8_t reserved10a; /* Byte offset 0x10a, CSR Addr 0x54085, Direction=N/A */ + uint8_t reserved10b; /* Byte offset 0x10b, CSR Addr 0x54085, Direction=N/A */ + uint8_t reserved10c; /* Byte offset 0x10c, CSR Addr 0x54086, Direction=N/A */ + uint8_t reserved10d; /* Byte offset 0x10d, CSR Addr 0x54086, Direction=N/A */ + uint8_t reserved10e; /* Byte offset 0x10e, CSR Addr 0x54087, Direction=N/A */ + uint8_t reserved10f; /* Byte offset 0x10f, CSR Addr 0x54087, Direction=N/A */ + uint8_t reserved110; /* Byte offset 0x110, CSR Addr 0x54088, Direction=N/A */ + uint8_t reserved111; /* Byte offset 0x111, CSR Addr 0x54088, Direction=N/A */ + uint8_t reserved112; /* Byte offset 0x112, CSR Addr 0x54089, Direction=N/A */ + uint8_t reserved113; /* Byte offset 0x113, CSR Addr 0x54089, Direction=N/A */ + uint8_t reserved114; /* Byte offset 0x114, CSR Addr 0x5408a, Direction=N/A */ + uint8_t reserved115; /* Byte offset 0x115, CSR Addr 0x5408a, Direction=N/A */ + uint8_t reserved116; /* Byte offset 0x116, CSR Addr 0x5408b, Direction=N/A */ + uint8_t reserved117; /* Byte offset 0x117, CSR Addr 0x5408b, Direction=N/A */ + uint8_t reserved118; /* Byte offset 0x118, CSR Addr 0x5408c, Direction=N/A */ + uint8_t reserved119; /* Byte offset 0x119, CSR Addr 0x5408c, Direction=N/A */ + uint8_t reserved11a; /* Byte offset 0x11a, CSR Addr 0x5408d, Direction=N/A */ + uint8_t reserved11b; /* Byte offset 0x11b, CSR Addr 0x5408d, Direction=N/A */ + uint8_t reserved11c; /* Byte offset 0x11c, CSR Addr 0x5408e, Direction=N/A */ + uint8_t reserved11d; /* Byte offset 0x11d, CSR Addr 0x5408e, Direction=N/A */ + uint8_t reserved11e; /* Byte offset 0x11e, CSR Addr 0x5408f, Direction=N/A */ + uint8_t reserved11f; /* Byte offset 0x11f, CSR Addr 0x5408f, Direction=N/A */ + uint8_t reserved120; /* Byte offset 0x120, CSR Addr 0x54090, Direction=N/A */ + uint8_t reserved121; /* Byte offset 0x121, CSR Addr 0x54090, Direction=N/A */ + uint8_t reserved122; /* Byte offset 0x122, CSR Addr 0x54091, Direction=N/A */ + uint8_t reserved123; /* Byte offset 0x123, CSR Addr 0x54091, Direction=N/A */ + uint8_t reserved124; /* Byte offset 0x124, CSR Addr 0x54092, Direction=N/A */ + uint8_t reserved125; /* Byte offset 0x125, CSR Addr 0x54092, Direction=N/A */ + uint8_t reserved126; /* Byte offset 0x126, CSR Addr 0x54093, Direction=N/A */ + uint8_t reserved127; /* Byte offset 0x127, CSR Addr 0x54093, Direction=N/A */ + uint8_t reserved128; /* Byte offset 0x128, CSR Addr 0x54094, Direction=N/A */ + uint8_t reserved129; /* Byte offset 0x129, CSR Addr 0x54094, Direction=N/A */ + uint8_t reserved12a; /* Byte offset 0x12a, CSR Addr 0x54095, Direction=N/A */ + uint8_t reserved12b; /* Byte offset 0x12b, CSR Addr 0x54095, Direction=N/A */ + uint8_t reserved12c; /* Byte offset 0x12c, CSR Addr 0x54096, Direction=N/A */ + uint8_t reserved12d; /* Byte offset 0x12d, CSR Addr 0x54096, Direction=N/A */ + uint8_t reserved12e; /* Byte offset 0x12e, CSR Addr 0x54097, Direction=N/A */ + uint8_t reserved12f; /* Byte offset 0x12f, CSR Addr 0x54097, Direction=N/A */ + uint8_t reserved130; /* Byte offset 0x130, CSR Addr 0x54098, Direction=N/A */ + uint8_t reserved131; /* Byte offset 0x131, CSR Addr 0x54098, Direction=N/A */ + uint8_t reserved132; /* Byte offset 0x132, CSR Addr 0x54099, Direction=N/A */ + uint8_t reserved133; /* Byte offset 0x133, CSR Addr 0x54099, Direction=N/A */ + uint8_t reserved134; /* Byte offset 0x134, CSR Addr 0x5409a, Direction=N/A */ + uint8_t reserved135; /* Byte offset 0x135, CSR Addr 0x5409a, Direction=N/A */ + uint8_t reserved136; /* Byte offset 0x136, CSR Addr 0x5409b, Direction=N/A */ + uint8_t reserved137; /* Byte offset 0x137, CSR Addr 0x5409b, Direction=N/A */ + uint8_t reserved138; /* Byte offset 0x138, CSR Addr 0x5409c, Direction=N/A */ + uint8_t reserved139; /* Byte offset 0x139, CSR Addr 0x5409c, Direction=N/A */ + uint8_t reserved13a; /* Byte offset 0x13a, CSR Addr 0x5409d, Direction=N/A */ + uint8_t reserved13b; /* Byte offset 0x13b, CSR Addr 0x5409d, Direction=N/A */ + uint8_t reserved13c; /* Byte offset 0x13c, CSR Addr 0x5409e, Direction=N/A */ + uint8_t reserved13d; /* Byte offset 0x13d, CSR Addr 0x5409e, Direction=N/A */ + uint8_t reserved13e; /* Byte offset 0x13e, CSR Addr 0x5409f, Direction=N/A */ + uint8_t reserved13f; /* Byte offset 0x13f, CSR Addr 0x5409f, Direction=N/A */ + uint8_t reserved140; /* Byte offset 0x140, CSR Addr 0x540a0, Direction=N/A */ + uint8_t reserved141; /* Byte offset 0x141, CSR Addr 0x540a0, Direction=N/A */ + uint8_t reserved142; /* Byte offset 0x142, CSR Addr 0x540a1, Direction=N/A */ + uint8_t reserved143; /* Byte offset 0x143, CSR Addr 0x540a1, Direction=N/A */ + uint8_t reserved144; /* Byte offset 0x144, CSR Addr 0x540a2, Direction=N/A */ + uint8_t reserved145; /* Byte offset 0x145, CSR Addr 0x540a2, Direction=N/A */ + uint8_t reserved146; /* Byte offset 0x146, CSR Addr 0x540a3, Direction=N/A */ + uint8_t reserved147; /* Byte offset 0x147, CSR Addr 0x540a3, Direction=N/A */ + uint8_t reserved148; /* Byte offset 0x148, CSR Addr 0x540a4, Direction=N/A */ + uint8_t reserved149; /* Byte offset 0x149, CSR Addr 0x540a4, Direction=N/A */ + uint8_t reserved14a; /* Byte offset 0x14a, CSR Addr 0x540a5, Direction=N/A */ + uint8_t reserved14b; /* Byte offset 0x14b, CSR Addr 0x540a5, Direction=N/A */ + uint8_t reserved14c; /* Byte offset 0x14c, CSR Addr 0x540a6, Direction=N/A */ + uint8_t reserved14d; /* Byte offset 0x14d, CSR Addr 0x540a6, Direction=N/A */ + uint8_t reserved14e; /* Byte offset 0x14e, CSR Addr 0x540a7, Direction=N/A */ + uint8_t reserved14f; /* Byte offset 0x14f, CSR Addr 0x540a7, Direction=N/A */ + uint8_t reserved150; /* Byte offset 0x150, CSR Addr 0x540a8, Direction=N/A */ + uint8_t reserved151; /* Byte offset 0x151, CSR Addr 0x540a8, Direction=N/A */ + uint8_t reserved152; /* Byte offset 0x152, CSR Addr 0x540a9, Direction=N/A */ + uint8_t reserved153; /* Byte offset 0x153, CSR Addr 0x540a9, Direction=N/A */ + uint8_t reserved154; /* Byte offset 0x154, CSR Addr 0x540aa, Direction=N/A */ + uint8_t reserved155; /* Byte offset 0x155, CSR Addr 0x540aa, Direction=N/A */ + uint8_t reserved156; /* Byte offset 0x156, CSR Addr 0x540ab, Direction=N/A */ + uint8_t reserved157; /* Byte offset 0x157, CSR Addr 0x540ab, Direction=N/A */ + uint8_t reserved158; /* Byte offset 0x158, CSR Addr 0x540ac, Direction=N/A */ + uint8_t reserved159; /* Byte offset 0x159, CSR Addr 0x540ac, Direction=N/A */ + uint8_t reserved15a; /* Byte offset 0x15a, CSR Addr 0x540ad, Direction=N/A */ + uint8_t reserved15b; /* Byte offset 0x15b, CSR Addr 0x540ad, Direction=N/A */ + uint8_t reserved15c; /* Byte offset 0x15c, CSR Addr 0x540ae, Direction=N/A */ + uint8_t reserved15d; /* Byte offset 0x15d, CSR Addr 0x540ae, Direction=N/A */ + uint8_t reserved15e; /* Byte offset 0x15e, CSR Addr 0x540af, Direction=N/A */ + uint8_t reserved15f; /* Byte offset 0x15f, CSR Addr 0x540af, Direction=N/A */ + uint8_t reserved160; /* Byte offset 0x160, CSR Addr 0x540b0, Direction=N/A */ + uint8_t reserved161; /* Byte offset 0x161, CSR Addr 0x540b0, Direction=N/A */ + uint8_t reserved162; /* Byte offset 0x162, CSR Addr 0x540b1, Direction=N/A */ + uint8_t reserved163; /* Byte offset 0x163, CSR Addr 0x540b1, Direction=N/A */ + uint8_t reserved164; /* Byte offset 0x164, CSR Addr 0x540b2, Direction=N/A */ + uint8_t reserved165; /* Byte offset 0x165, CSR Addr 0x540b2, Direction=N/A */ + uint8_t reserved166; /* Byte offset 0x166, CSR Addr 0x540b3, Direction=N/A */ + uint8_t reserved167; /* Byte offset 0x167, CSR Addr 0x540b3, Direction=N/A */ + uint8_t reserved168; /* Byte offset 0x168, CSR Addr 0x540b4, Direction=N/A */ + uint8_t reserved169; /* Byte offset 0x169, CSR Addr 0x540b4, Direction=N/A */ + uint8_t reserved16a; /* Byte offset 0x16a, CSR Addr 0x540b5, Direction=N/A */ + uint8_t reserved16b; /* Byte offset 0x16b, CSR Addr 0x540b5, Direction=N/A */ + uint8_t reserved16c; /* Byte offset 0x16c, CSR Addr 0x540b6, Direction=N/A */ + uint8_t reserved16d; /* Byte offset 0x16d, CSR Addr 0x540b6, Direction=N/A */ + uint8_t reserved16e; /* Byte offset 0x16e, CSR Addr 0x540b7, Direction=N/A */ + uint8_t reserved16f; /* Byte offset 0x16f, CSR Addr 0x540b7, Direction=N/A */ + uint8_t reserved170; /* Byte offset 0x170, CSR Addr 0x540b8, Direction=N/A */ + uint8_t reserved171; /* Byte offset 0x171, CSR Addr 0x540b8, Direction=N/A */ + uint8_t reserved172; /* Byte offset 0x172, CSR Addr 0x540b9, Direction=N/A */ + uint8_t reserved173; /* Byte offset 0x173, CSR Addr 0x540b9, Direction=N/A */ + uint8_t reserved174; /* Byte offset 0x174, CSR Addr 0x540ba, Direction=N/A */ + uint8_t reserved175; /* Byte offset 0x175, CSR Addr 0x540ba, Direction=N/A */ + uint8_t reserved176; /* Byte offset 0x176, CSR Addr 0x540bb, Direction=N/A */ + uint8_t reserved177; /* Byte offset 0x177, CSR Addr 0x540bb, Direction=N/A */ + uint8_t reserved178; /* Byte offset 0x178, CSR Addr 0x540bc, Direction=N/A */ + uint8_t reserved179; /* Byte offset 0x179, CSR Addr 0x540bc, Direction=N/A */ + uint8_t reserved17a; /* Byte offset 0x17a, CSR Addr 0x540bd, Direction=N/A */ + uint8_t reserved17b; /* Byte offset 0x17b, CSR Addr 0x540bd, Direction=N/A */ + uint8_t reserved17c; /* Byte offset 0x17c, CSR Addr 0x540be, Direction=N/A */ + uint8_t reserved17d; /* Byte offset 0x17d, CSR Addr 0x540be, Direction=N/A */ + uint8_t reserved17e; /* Byte offset 0x17e, CSR Addr 0x540bf, Direction=N/A */ + uint8_t reserved17f; /* Byte offset 0x17f, CSR Addr 0x540bf, Direction=N/A */ + uint8_t reserved180; /* Byte offset 0x180, CSR Addr 0x540c0, Direction=N/A */ + uint8_t reserved181; /* Byte offset 0x181, CSR Addr 0x540c0, Direction=N/A */ + uint8_t reserved182; /* Byte offset 0x182, CSR Addr 0x540c1, Direction=N/A */ + uint8_t reserved183; /* Byte offset 0x183, CSR Addr 0x540c1, Direction=N/A */ + uint8_t reserved184; /* Byte offset 0x184, CSR Addr 0x540c2, Direction=N/A */ + uint8_t reserved185; /* Byte offset 0x185, CSR Addr 0x540c2, Direction=N/A */ + uint8_t reserved186; /* Byte offset 0x186, CSR Addr 0x540c3, Direction=N/A */ + uint8_t reserved187; /* Byte offset 0x187, CSR Addr 0x540c3, Direction=N/A */ + uint8_t reserved188; /* Byte offset 0x188, CSR Addr 0x540c4, Direction=N/A */ + uint8_t reserved189; /* Byte offset 0x189, CSR Addr 0x540c4, Direction=N/A */ + uint8_t reserved18a; /* Byte offset 0x18a, CSR Addr 0x540c5, Direction=N/A */ + uint8_t reserved18b; /* Byte offset 0x18b, CSR Addr 0x540c5, Direction=N/A */ + uint8_t reserved18c; /* Byte offset 0x18c, CSR Addr 0x540c6, Direction=N/A */ + uint8_t reserved18d; /* Byte offset 0x18d, CSR Addr 0x540c6, Direction=N/A */ + uint8_t reserved18e; /* Byte offset 0x18e, CSR Addr 0x540c7, Direction=N/A */ + uint8_t reserved18f; /* Byte offset 0x18f, CSR Addr 0x540c7, Direction=N/A */ + uint8_t reserved190; /* Byte offset 0x190, CSR Addr 0x540c8, Direction=N/A */ + uint8_t reserved191; /* Byte offset 0x191, CSR Addr 0x540c8, Direction=N/A */ + uint8_t reserved192; /* Byte offset 0x192, CSR Addr 0x540c9, Direction=N/A */ + uint8_t reserved193; /* Byte offset 0x193, CSR Addr 0x540c9, Direction=N/A */ + uint8_t reserved194; /* Byte offset 0x194, CSR Addr 0x540ca, Direction=N/A */ + uint8_t reserved195; /* Byte offset 0x195, CSR Addr 0x540ca, Direction=N/A */ + uint8_t reserved196; /* Byte offset 0x196, CSR Addr 0x540cb, Direction=N/A */ + uint8_t reserved197; /* Byte offset 0x197, CSR Addr 0x540cb, Direction=N/A */ + uint8_t reserved198; /* Byte offset 0x198, CSR Addr 0x540cc, Direction=N/A */ + uint8_t reserved199; /* Byte offset 0x199, CSR Addr 0x540cc, Direction=N/A */ + uint8_t reserved19a; /* Byte offset 0x19a, CSR Addr 0x540cd, Direction=N/A */ + uint8_t reserved19b; /* Byte offset 0x19b, CSR Addr 0x540cd, Direction=N/A */ + uint8_t reserved19c; /* Byte offset 0x19c, CSR Addr 0x540ce, Direction=N/A */ + uint8_t reserved19d; /* Byte offset 0x19d, CSR Addr 0x540ce, Direction=N/A */ + uint8_t reserved19e; /* Byte offset 0x19e, CSR Addr 0x540cf, Direction=N/A */ + uint8_t reserved19f; /* Byte offset 0x19f, CSR Addr 0x540cf, Direction=N/A */ + uint8_t reserved1a0; /* Byte offset 0x1a0, CSR Addr 0x540d0, Direction=N/A */ + uint8_t reserved1a1; /* Byte offset 0x1a1, CSR Addr 0x540d0, Direction=N/A */ + uint8_t reserved1a2; /* Byte offset 0x1a2, CSR Addr 0x540d1, Direction=N/A */ + uint8_t reserved1a3; /* Byte offset 0x1a3, CSR Addr 0x540d1, Direction=N/A */ + uint8_t reserved1a4; /* Byte offset 0x1a4, CSR Addr 0x540d2, Direction=N/A */ + uint8_t reserved1a5; /* Byte offset 0x1a5, CSR Addr 0x540d2, Direction=N/A */ + uint8_t reserved1a6; /* Byte offset 0x1a6, CSR Addr 0x540d3, Direction=N/A */ + uint8_t reserved1a7; /* Byte offset 0x1a7, CSR Addr 0x540d3, Direction=N/A */ + uint8_t reserved1a8; /* Byte offset 0x1a8, CSR Addr 0x540d4, Direction=N/A */ + uint8_t reserved1a9; /* Byte offset 0x1a9, CSR Addr 0x540d4, Direction=N/A */ + uint8_t reserved1aa; /* Byte offset 0x1aa, CSR Addr 0x540d5, Direction=N/A */ + uint8_t reserved1ab; /* Byte offset 0x1ab, CSR Addr 0x540d5, Direction=N/A */ + uint8_t reserved1ac; /* Byte offset 0x1ac, CSR Addr 0x540d6, Direction=N/A */ + uint8_t reserved1ad; /* Byte offset 0x1ad, CSR Addr 0x540d6, Direction=N/A */ + uint8_t reserved1ae; /* Byte offset 0x1ae, CSR Addr 0x540d7, Direction=N/A */ + uint8_t reserved1af; /* Byte offset 0x1af, CSR Addr 0x540d7, Direction=N/A */ + uint8_t reserved1b0; /* Byte offset 0x1b0, CSR Addr 0x540d8, Direction=N/A */ + uint8_t reserved1b1; /* Byte offset 0x1b1, CSR Addr 0x540d8, Direction=N/A */ + uint8_t reserved1b2; /* Byte offset 0x1b2, CSR Addr 0x540d9, Direction=N/A */ + uint8_t reserved1b3; /* Byte offset 0x1b3, CSR Addr 0x540d9, Direction=N/A */ + uint8_t reserved1b4; /* Byte offset 0x1b4, CSR Addr 0x540da, Direction=N/A */ + uint8_t reserved1b5; /* Byte offset 0x1b5, CSR Addr 0x540da, Direction=N/A */ + uint8_t reserved1b6; /* Byte offset 0x1b6, CSR Addr 0x540db, Direction=N/A */ + uint8_t reserved1b7; /* Byte offset 0x1b7, CSR Addr 0x540db, Direction=N/A */ + uint8_t reserved1b8; /* Byte offset 0x1b8, CSR Addr 0x540dc, Direction=N/A */ + uint8_t reserved1b9; /* Byte offset 0x1b9, CSR Addr 0x540dc, Direction=N/A */ + uint8_t reserved1ba; /* Byte offset 0x1ba, CSR Addr 0x540dd, Direction=N/A */ + uint8_t reserved1bb; /* Byte offset 0x1bb, CSR Addr 0x540dd, Direction=N/A */ + uint8_t reserved1bc; /* Byte offset 0x1bc, CSR Addr 0x540de, Direction=N/A */ + uint8_t reserved1bd; /* Byte offset 0x1bd, CSR Addr 0x540de, Direction=N/A */ + uint8_t reserved1be; /* Byte offset 0x1be, CSR Addr 0x540df, Direction=N/A */ + uint8_t reserved1bf; /* Byte offset 0x1bf, CSR Addr 0x540df, Direction=N/A */ + uint8_t reserved1c0; /* Byte offset 0x1c0, CSR Addr 0x540e0, Direction=N/A */ + uint8_t reserved1c1; /* Byte offset 0x1c1, CSR Addr 0x540e0, Direction=N/A */ + uint8_t reserved1c2; /* Byte offset 0x1c2, CSR Addr 0x540e1, Direction=N/A */ + uint8_t reserved1c3; /* Byte offset 0x1c3, CSR Addr 0x540e1, Direction=N/A */ + uint8_t reserved1c4; /* Byte offset 0x1c4, CSR Addr 0x540e2, Direction=N/A */ + uint8_t reserved1c5; /* Byte offset 0x1c5, CSR Addr 0x540e2, Direction=N/A */ + uint8_t reserved1c6; /* Byte offset 0x1c6, CSR Addr 0x540e3, Direction=N/A */ + uint8_t reserved1c7; /* Byte offset 0x1c7, CSR Addr 0x540e3, Direction=N/A */ + uint8_t reserved1c8; /* Byte offset 0x1c8, CSR Addr 0x540e4, Direction=N/A */ + uint8_t reserved1c9; /* Byte offset 0x1c9, CSR Addr 0x540e4, Direction=N/A */ + uint8_t reserved1ca; /* Byte offset 0x1ca, CSR Addr 0x540e5, Direction=N/A */ + uint8_t reserved1cb; /* Byte offset 0x1cb, CSR Addr 0x540e5, Direction=N/A */ + uint8_t reserved1cc; /* Byte offset 0x1cc, CSR Addr 0x540e6, Direction=N/A */ + uint8_t reserved1cd; /* Byte offset 0x1cd, CSR Addr 0x540e6, Direction=N/A */ + uint8_t reserved1ce; /* Byte offset 0x1ce, CSR Addr 0x540e7, Direction=N/A */ + uint8_t reserved1cf; /* Byte offset 0x1cf, CSR Addr 0x540e7, Direction=N/A */ + uint8_t reserved1d0; /* Byte offset 0x1d0, CSR Addr 0x540e8, Direction=N/A */ + uint8_t reserved1d1; /* Byte offset 0x1d1, CSR Addr 0x540e8, Direction=N/A */ + uint8_t reserved1d2; /* Byte offset 0x1d2, CSR Addr 0x540e9, Direction=N/A */ + uint8_t reserved1d3; /* Byte offset 0x1d3, CSR Addr 0x540e9, Direction=N/A */ + uint8_t reserved1d4; /* Byte offset 0x1d4, CSR Addr 0x540ea, Direction=N/A */ + uint8_t reserved1d5; /* Byte offset 0x1d5, CSR Addr 0x540ea, Direction=N/A */ + uint8_t reserved1d6; /* Byte offset 0x1d6, CSR Addr 0x540eb, Direction=N/A */ + uint8_t reserved1d7; /* Byte offset 0x1d7, CSR Addr 0x540eb, Direction=N/A */ + uint8_t reserved1d8; /* Byte offset 0x1d8, CSR Addr 0x540ec, Direction=N/A */ + uint8_t reserved1d9; /* Byte offset 0x1d9, CSR Addr 0x540ec, Direction=N/A */ + uint8_t reserved1da; /* Byte offset 0x1da, CSR Addr 0x540ed, Direction=N/A */ + uint8_t reserved1db; /* Byte offset 0x1db, CSR Addr 0x540ed, Direction=N/A */ + uint8_t reserved1dc; /* Byte offset 0x1dc, CSR Addr 0x540ee, Direction=N/A */ + uint8_t reserved1dd; /* Byte offset 0x1dd, CSR Addr 0x540ee, Direction=N/A */ + uint8_t reserved1de; /* Byte offset 0x1de, CSR Addr 0x540ef, Direction=N/A */ + uint8_t reserved1df; /* Byte offset 0x1df, CSR Addr 0x540ef, Direction=N/A */ + uint8_t reserved1e0; /* Byte offset 0x1e0, CSR Addr 0x540f0, Direction=N/A */ + uint8_t reserved1e1; /* Byte offset 0x1e1, CSR Addr 0x540f0, Direction=N/A */ + uint8_t reserved1e2; /* Byte offset 0x1e2, CSR Addr 0x540f1, Direction=N/A */ + uint8_t reserved1e3; /* Byte offset 0x1e3, CSR Addr 0x540f1, Direction=N/A */ + uint8_t reserved1e4; /* Byte offset 0x1e4, CSR Addr 0x540f2, Direction=N/A */ + uint8_t reserved1e5; /* Byte offset 0x1e5, CSR Addr 0x540f2, Direction=N/A */ + uint8_t reserved1e6; /* Byte offset 0x1e6, CSR Addr 0x540f3, Direction=N/A */ + uint8_t reserved1e7; /* Byte offset 0x1e7, CSR Addr 0x540f3, Direction=N/A */ + uint8_t reserved1e8; /* Byte offset 0x1e8, CSR Addr 0x540f4, Direction=N/A */ + uint8_t reserved1e9; /* Byte offset 0x1e9, CSR Addr 0x540f4, Direction=N/A */ + uint8_t reserved1ea; /* Byte offset 0x1ea, CSR Addr 0x540f5, Direction=N/A */ + uint8_t reserved1eb; /* Byte offset 0x1eb, CSR Addr 0x540f5, Direction=N/A */ + uint8_t reserved1ec; /* Byte offset 0x1ec, CSR Addr 0x540f6, Direction=N/A */ + uint8_t reserved1ed; /* Byte offset 0x1ed, CSR Addr 0x540f6, Direction=N/A */ + uint8_t reserved1ee; /* Byte offset 0x1ee, CSR Addr 0x540f7, Direction=N/A */ + uint8_t reserved1ef; /* Byte offset 0x1ef, CSR Addr 0x540f7, Direction=N/A */ + uint8_t reserved1f0; /* Byte offset 0x1f0, CSR Addr 0x540f8, Direction=N/A */ + uint8_t reserved1f1; /* Byte offset 0x1f1, CSR Addr 0x540f8, Direction=N/A */ + uint8_t reserved1f2; /* Byte offset 0x1f2, CSR Addr 0x540f9, Direction=N/A */ + uint8_t reserved1f3; /* Byte offset 0x1f3, CSR Addr 0x540f9, Direction=N/A */ + uint8_t reserved1f4; /* Byte offset 0x1f4, CSR Addr 0x540fa, Direction=N/A */ + uint8_t reserved1f5; /* Byte offset 0x1f5, CSR Addr 0x540fa, Direction=N/A */ + uint8_t reserved1f6; /* Byte offset 0x1f6, CSR Addr 0x540fb, Direction=N/A */ + uint8_t reserved1f7; /* Byte offset 0x1f7, CSR Addr 0x540fb, Direction=N/A */ + uint8_t reserved1f8; /* Byte offset 0x1f8, CSR Addr 0x540fc, Direction=N/A */ + uint8_t reserved1f9; /* Byte offset 0x1f9, CSR Addr 0x540fc, Direction=N/A */ + uint8_t reserved1fa; /* Byte offset 0x1fa, CSR Addr 0x540fd, Direction=N/A */ + uint8_t reserved1fb; /* Byte offset 0x1fb, CSR Addr 0x540fd, Direction=N/A */ + uint8_t reserved1fc; /* Byte offset 0x1fc, CSR Addr 0x540fe, Direction=N/A */ + uint8_t reserved1fd; /* Byte offset 0x1fd, CSR Addr 0x540fe, Direction=N/A */ + uint8_t reserved1fe; /* Byte offset 0x1fe, CSR Addr 0x540ff, Direction=N/A */ + uint8_t reserved1ff; /* Byte offset 0x1ff, CSR Addr 0x540ff, Direction=N/A */ + uint8_t reserved200; /* Byte offset 0x200, CSR Addr 0x54100, Direction=N/A */ + uint8_t reserved201; /* Byte offset 0x201, CSR Addr 0x54100, Direction=N/A */ + uint8_t reserved202; /* Byte offset 0x202, CSR Addr 0x54101, Direction=N/A */ + uint8_t reserved203; /* Byte offset 0x203, CSR Addr 0x54101, Direction=N/A */ + uint8_t reserved204; /* Byte offset 0x204, CSR Addr 0x54102, Direction=N/A */ + uint8_t reserved205; /* Byte offset 0x205, CSR Addr 0x54102, Direction=N/A */ + uint8_t reserved206; /* Byte offset 0x206, CSR Addr 0x54103, Direction=N/A */ + uint8_t reserved207; /* Byte offset 0x207, CSR Addr 0x54103, Direction=N/A */ + uint8_t reserved208; /* Byte offset 0x208, CSR Addr 0x54104, Direction=N/A */ + uint8_t reserved209; /* Byte offset 0x209, CSR Addr 0x54104, Direction=N/A */ + uint8_t reserved20a; /* Byte offset 0x20a, CSR Addr 0x54105, Direction=N/A */ + uint8_t reserved20b; /* Byte offset 0x20b, CSR Addr 0x54105, Direction=N/A */ + uint8_t reserved20c; /* Byte offset 0x20c, CSR Addr 0x54106, Direction=N/A */ + uint8_t reserved20d; /* Byte offset 0x20d, CSR Addr 0x54106, Direction=N/A */ + uint8_t reserved20e; /* Byte offset 0x20e, CSR Addr 0x54107, Direction=N/A */ + uint8_t reserved20f; /* Byte offset 0x20f, CSR Addr 0x54107, Direction=N/A */ + uint8_t reserved210; /* Byte offset 0x210, CSR Addr 0x54108, Direction=N/A */ + uint8_t reserved211; /* Byte offset 0x211, CSR Addr 0x54108, Direction=N/A */ + uint8_t reserved212; /* Byte offset 0x212, CSR Addr 0x54109, Direction=N/A */ + uint8_t reserved213; /* Byte offset 0x213, CSR Addr 0x54109, Direction=N/A */ + uint8_t reserved214; /* Byte offset 0x214, CSR Addr 0x5410a, Direction=N/A */ + uint8_t reserved215; /* Byte offset 0x215, CSR Addr 0x5410a, Direction=N/A */ + uint8_t reserved216; /* Byte offset 0x216, CSR Addr 0x5410b, Direction=N/A */ + uint8_t reserved217; /* Byte offset 0x217, CSR Addr 0x5410b, Direction=N/A */ + uint8_t reserved218; /* Byte offset 0x218, CSR Addr 0x5410c, Direction=N/A */ + uint8_t reserved219; /* Byte offset 0x219, CSR Addr 0x5410c, Direction=N/A */ + uint8_t reserved21a; /* Byte offset 0x21a, CSR Addr 0x5410d, Direction=N/A */ + uint8_t reserved21b; /* Byte offset 0x21b, CSR Addr 0x5410d, Direction=N/A */ + uint8_t reserved21c; /* Byte offset 0x21c, CSR Addr 0x5410e, Direction=N/A */ + uint8_t reserved21d; /* Byte offset 0x21d, CSR Addr 0x5410e, Direction=N/A */ + uint8_t reserved21e; /* Byte offset 0x21e, CSR Addr 0x5410f, Direction=N/A */ + uint8_t reserved21f; /* Byte offset 0x21f, CSR Addr 0x5410f, Direction=N/A */ + uint8_t reserved220; /* Byte offset 0x220, CSR Addr 0x54110, Direction=N/A */ + uint8_t reserved221; /* Byte offset 0x221, CSR Addr 0x54110, Direction=N/A */ + uint8_t reserved222; /* Byte offset 0x222, CSR Addr 0x54111, Direction=N/A */ + uint8_t reserved223; /* Byte offset 0x223, CSR Addr 0x54111, Direction=N/A */ + uint8_t reserved224; /* Byte offset 0x224, CSR Addr 0x54112, Direction=N/A */ + uint8_t reserved225; /* Byte offset 0x225, CSR Addr 0x54112, Direction=N/A */ + uint8_t reserved226; /* Byte offset 0x226, CSR Addr 0x54113, Direction=N/A */ + uint8_t reserved227; /* Byte offset 0x227, CSR Addr 0x54113, Direction=N/A */ + uint8_t reserved228; /* Byte offset 0x228, CSR Addr 0x54114, Direction=N/A */ + uint8_t reserved229; /* Byte offset 0x229, CSR Addr 0x54114, Direction=N/A */ + uint8_t reserved22a; /* Byte offset 0x22a, CSR Addr 0x54115, Direction=N/A */ + uint8_t reserved22b; /* Byte offset 0x22b, CSR Addr 0x54115, Direction=N/A */ + uint8_t reserved22c; /* Byte offset 0x22c, CSR Addr 0x54116, Direction=N/A */ + uint8_t reserved22d; /* Byte offset 0x22d, CSR Addr 0x54116, Direction=N/A */ + uint8_t reserved22e; /* Byte offset 0x22e, CSR Addr 0x54117, Direction=N/A */ + uint8_t reserved22f; /* Byte offset 0x22f, CSR Addr 0x54117, Direction=N/A */ + uint8_t reserved230; /* Byte offset 0x230, CSR Addr 0x54118, Direction=N/A */ + uint8_t reserved231; /* Byte offset 0x231, CSR Addr 0x54118, Direction=N/A */ + uint8_t reserved232; /* Byte offset 0x232, CSR Addr 0x54119, Direction=N/A */ + uint8_t reserved233; /* Byte offset 0x233, CSR Addr 0x54119, Direction=N/A */ + uint8_t reserved234; /* Byte offset 0x234, CSR Addr 0x5411a, Direction=N/A */ + uint8_t reserved235; /* Byte offset 0x235, CSR Addr 0x5411a, Direction=N/A */ + uint8_t reserved236; /* Byte offset 0x236, CSR Addr 0x5411b, Direction=N/A */ + uint8_t reserved237; /* Byte offset 0x237, CSR Addr 0x5411b, Direction=N/A */ + uint8_t reserved238; /* Byte offset 0x238, CSR Addr 0x5411c, Direction=N/A */ + uint8_t reserved239; /* Byte offset 0x239, CSR Addr 0x5411c, Direction=N/A */ + uint8_t reserved23a; /* Byte offset 0x23a, CSR Addr 0x5411d, Direction=N/A */ + uint8_t reserved23b; /* Byte offset 0x23b, CSR Addr 0x5411d, Direction=N/A */ + uint8_t reserved23c; /* Byte offset 0x23c, CSR Addr 0x5411e, Direction=N/A */ + uint8_t reserved23d; /* Byte offset 0x23d, CSR Addr 0x5411e, Direction=N/A */ + uint8_t reserved23e; /* Byte offset 0x23e, CSR Addr 0x5411f, Direction=N/A */ + uint8_t reserved23f; /* Byte offset 0x23f, CSR Addr 0x5411f, Direction=N/A */ + uint8_t reserved240; /* Byte offset 0x240, CSR Addr 0x54120, Direction=N/A */ + uint8_t reserved241; /* Byte offset 0x241, CSR Addr 0x54120, Direction=N/A */ + uint8_t reserved242; /* Byte offset 0x242, CSR Addr 0x54121, Direction=N/A */ + uint8_t reserved243; /* Byte offset 0x243, CSR Addr 0x54121, Direction=N/A */ + uint8_t reserved244; /* Byte offset 0x244, CSR Addr 0x54122, Direction=N/A */ + uint8_t reserved245; /* Byte offset 0x245, CSR Addr 0x54122, Direction=N/A */ + uint8_t reserved246; /* Byte offset 0x246, CSR Addr 0x54123, Direction=N/A */ + uint8_t reserved247; /* Byte offset 0x247, CSR Addr 0x54123, Direction=N/A */ + uint8_t reserved248; /* Byte offset 0x248, CSR Addr 0x54124, Direction=N/A */ + uint8_t reserved249; /* Byte offset 0x249, CSR Addr 0x54124, Direction=N/A */ + uint8_t reserved24a; /* Byte offset 0x24a, CSR Addr 0x54125, Direction=N/A */ + uint8_t reserved24b; /* Byte offset 0x24b, CSR Addr 0x54125, Direction=N/A */ + uint8_t reserved24c; /* Byte offset 0x24c, CSR Addr 0x54126, Direction=N/A */ + uint8_t reserved24d; /* Byte offset 0x24d, CSR Addr 0x54126, Direction=N/A */ + uint8_t reserved24e; /* Byte offset 0x24e, CSR Addr 0x54127, Direction=N/A */ + uint8_t reserved24f; /* Byte offset 0x24f, CSR Addr 0x54127, Direction=N/A */ + uint8_t reserved250; /* Byte offset 0x250, CSR Addr 0x54128, Direction=N/A */ + uint8_t reserved251; /* Byte offset 0x251, CSR Addr 0x54128, Direction=N/A */ + uint8_t reserved252; /* Byte offset 0x252, CSR Addr 0x54129, Direction=N/A */ + uint8_t reserved253; /* Byte offset 0x253, CSR Addr 0x54129, Direction=N/A */ + uint8_t reserved254; /* Byte offset 0x254, CSR Addr 0x5412a, Direction=N/A */ + uint8_t reserved255; /* Byte offset 0x255, CSR Addr 0x5412a, Direction=N/A */ + uint8_t reserved256; /* Byte offset 0x256, CSR Addr 0x5412b, Direction=N/A */ + uint8_t reserved257; /* Byte offset 0x257, CSR Addr 0x5412b, Direction=N/A */ + uint8_t reserved258; /* Byte offset 0x258, CSR Addr 0x5412c, Direction=N/A */ + uint8_t reserved259; /* Byte offset 0x259, CSR Addr 0x5412c, Direction=N/A */ + uint8_t reserved25a; /* Byte offset 0x25a, CSR Addr 0x5412d, Direction=N/A */ + uint8_t reserved25b; /* Byte offset 0x25b, CSR Addr 0x5412d, Direction=N/A */ + uint8_t reserved25c; /* Byte offset 0x25c, CSR Addr 0x5412e, Direction=N/A */ + uint8_t reserved25d; /* Byte offset 0x25d, CSR Addr 0x5412e, Direction=N/A */ + uint8_t reserved25e; /* Byte offset 0x25e, CSR Addr 0x5412f, Direction=N/A */ + uint8_t reserved25f; /* Byte offset 0x25f, CSR Addr 0x5412f, Direction=N/A */ + uint8_t reserved260; /* Byte offset 0x260, CSR Addr 0x54130, Direction=N/A */ + uint8_t reserved261; /* Byte offset 0x261, CSR Addr 0x54130, Direction=N/A */ + uint8_t reserved262; /* Byte offset 0x262, CSR Addr 0x54131, Direction=N/A */ + uint8_t reserved263; /* Byte offset 0x263, CSR Addr 0x54131, Direction=N/A */ + uint8_t reserved264; /* Byte offset 0x264, CSR Addr 0x54132, Direction=N/A */ + uint8_t reserved265; /* Byte offset 0x265, CSR Addr 0x54132, Direction=N/A */ + uint8_t reserved266; /* Byte offset 0x266, CSR Addr 0x54133, Direction=N/A */ + uint8_t reserved267; /* Byte offset 0x267, CSR Addr 0x54133, Direction=N/A */ + uint8_t reserved268; /* Byte offset 0x268, CSR Addr 0x54134, Direction=N/A */ + uint8_t reserved269; /* Byte offset 0x269, CSR Addr 0x54134, Direction=N/A */ + uint8_t reserved26a; /* Byte offset 0x26a, CSR Addr 0x54135, Direction=N/A */ + uint8_t reserved26b; /* Byte offset 0x26b, CSR Addr 0x54135, Direction=N/A */ + uint8_t reserved26c; /* Byte offset 0x26c, CSR Addr 0x54136, Direction=N/A */ + uint8_t reserved26d; /* Byte offset 0x26d, CSR Addr 0x54136, Direction=N/A */ + uint8_t reserved26e; /* Byte offset 0x26e, CSR Addr 0x54137, Direction=N/A */ + uint8_t reserved26f; /* Byte offset 0x26f, CSR Addr 0x54137, Direction=N/A */ + uint8_t reserved270; /* Byte offset 0x270, CSR Addr 0x54138, Direction=N/A */ + uint8_t reserved271; /* Byte offset 0x271, CSR Addr 0x54138, Direction=N/A */ + uint8_t reserved272; /* Byte offset 0x272, CSR Addr 0x54139, Direction=N/A */ + uint8_t reserved273; /* Byte offset 0x273, CSR Addr 0x54139, Direction=N/A */ + uint8_t reserved274; /* Byte offset 0x274, CSR Addr 0x5413a, Direction=N/A */ + uint8_t reserved275; /* Byte offset 0x275, CSR Addr 0x5413a, Direction=N/A */ + uint8_t reserved276; /* Byte offset 0x276, CSR Addr 0x5413b, Direction=N/A */ + uint8_t reserved277; /* Byte offset 0x277, CSR Addr 0x5413b, Direction=N/A */ + uint8_t reserved278; /* Byte offset 0x278, CSR Addr 0x5413c, Direction=N/A */ + uint8_t reserved279; /* Byte offset 0x279, CSR Addr 0x5413c, Direction=N/A */ + uint8_t reserved27a; /* Byte offset 0x27a, CSR Addr 0x5413d, Direction=N/A */ + uint8_t reserved27b; /* Byte offset 0x27b, CSR Addr 0x5413d, Direction=N/A */ + uint8_t reserved27c; /* Byte offset 0x27c, CSR Addr 0x5413e, Direction=N/A */ + uint8_t reserved27d; /* Byte offset 0x27d, CSR Addr 0x5413e, Direction=N/A */ + uint8_t reserved27e; /* Byte offset 0x27e, CSR Addr 0x5413f, Direction=N/A */ + uint8_t reserved27f; /* Byte offset 0x27f, CSR Addr 0x5413f, Direction=N/A */ + uint8_t reserved280; /* Byte offset 0x280, CSR Addr 0x54140, Direction=N/A */ + uint8_t reserved281; /* Byte offset 0x281, CSR Addr 0x54140, Direction=N/A */ + uint8_t reserved282; /* Byte offset 0x282, CSR Addr 0x54141, Direction=N/A */ + uint8_t reserved283; /* Byte offset 0x283, CSR Addr 0x54141, Direction=N/A */ + uint8_t reserved284; /* Byte offset 0x284, CSR Addr 0x54142, Direction=N/A */ + uint8_t reserved285; /* Byte offset 0x285, CSR Addr 0x54142, Direction=N/A */ + uint8_t reserved286; /* Byte offset 0x286, CSR Addr 0x54143, Direction=N/A */ + uint8_t reserved287; /* Byte offset 0x287, CSR Addr 0x54143, Direction=N/A */ + uint8_t reserved288; /* Byte offset 0x288, CSR Addr 0x54144, Direction=N/A */ + uint8_t reserved289; /* Byte offset 0x289, CSR Addr 0x54144, Direction=N/A */ + uint8_t reserved28a; /* Byte offset 0x28a, CSR Addr 0x54145, Direction=N/A */ + uint8_t reserved28b; /* Byte offset 0x28b, CSR Addr 0x54145, Direction=N/A */ + uint8_t reserved28c; /* Byte offset 0x28c, CSR Addr 0x54146, Direction=N/A */ + uint8_t reserved28d; /* Byte offset 0x28d, CSR Addr 0x54146, Direction=N/A */ + uint8_t reserved28e; /* Byte offset 0x28e, CSR Addr 0x54147, Direction=N/A */ + uint8_t reserved28f; /* Byte offset 0x28f, CSR Addr 0x54147, Direction=N/A */ + uint8_t reserved290; /* Byte offset 0x290, CSR Addr 0x54148, Direction=N/A */ + uint8_t reserved291; /* Byte offset 0x291, CSR Addr 0x54148, Direction=N/A */ + uint8_t reserved292; /* Byte offset 0x292, CSR Addr 0x54149, Direction=N/A */ + uint8_t reserved293; /* Byte offset 0x293, CSR Addr 0x54149, Direction=N/A */ + uint8_t reserved294; /* Byte offset 0x294, CSR Addr 0x5414a, Direction=N/A */ + uint8_t reserved295; /* Byte offset 0x295, CSR Addr 0x5414a, Direction=N/A */ + uint8_t reserved296; /* Byte offset 0x296, CSR Addr 0x5414b, Direction=N/A */ + uint8_t reserved297; /* Byte offset 0x297, CSR Addr 0x5414b, Direction=N/A */ + uint8_t reserved298; /* Byte offset 0x298, CSR Addr 0x5414c, Direction=N/A */ + uint8_t reserved299; /* Byte offset 0x299, CSR Addr 0x5414c, Direction=N/A */ + uint8_t reserved29a; /* Byte offset 0x29a, CSR Addr 0x5414d, Direction=N/A */ + uint8_t reserved29b; /* Byte offset 0x29b, CSR Addr 0x5414d, Direction=N/A */ + uint8_t reserved29c; /* Byte offset 0x29c, CSR Addr 0x5414e, Direction=N/A */ + uint8_t reserved29d; /* Byte offset 0x29d, CSR Addr 0x5414e, Direction=N/A */ + uint8_t reserved29e; /* Byte offset 0x29e, CSR Addr 0x5414f, Direction=N/A */ + uint8_t reserved29f; /* Byte offset 0x29f, CSR Addr 0x5414f, Direction=N/A */ + uint8_t reserved2a0; /* Byte offset 0x2a0, CSR Addr 0x54150, Direction=N/A */ + uint8_t reserved2a1; /* Byte offset 0x2a1, CSR Addr 0x54150, Direction=N/A */ + uint8_t reserved2a2; /* Byte offset 0x2a2, CSR Addr 0x54151, Direction=N/A */ + uint8_t reserved2a3; /* Byte offset 0x2a3, CSR Addr 0x54151, Direction=N/A */ + uint8_t reserved2a4; /* Byte offset 0x2a4, CSR Addr 0x54152, Direction=N/A */ + uint8_t reserved2a5; /* Byte offset 0x2a5, CSR Addr 0x54152, Direction=N/A */ + uint8_t reserved2a6; /* Byte offset 0x2a6, CSR Addr 0x54153, Direction=N/A */ + uint8_t reserved2a7; /* Byte offset 0x2a7, CSR Addr 0x54153, Direction=N/A */ + uint8_t reserved2a8; /* Byte offset 0x2a8, CSR Addr 0x54154, Direction=N/A */ + uint8_t reserved2a9; /* Byte offset 0x2a9, CSR Addr 0x54154, Direction=N/A */ + uint8_t reserved2aa; /* Byte offset 0x2aa, CSR Addr 0x54155, Direction=N/A */ + uint8_t reserved2ab; /* Byte offset 0x2ab, CSR Addr 0x54155, Direction=N/A */ + uint8_t reserved2ac; /* Byte offset 0x2ac, CSR Addr 0x54156, Direction=N/A */ + uint8_t reserved2ad; /* Byte offset 0x2ad, CSR Addr 0x54156, Direction=N/A */ + uint8_t reserved2ae; /* Byte offset 0x2ae, CSR Addr 0x54157, Direction=N/A */ + uint8_t reserved2af; /* Byte offset 0x2af, CSR Addr 0x54157, Direction=N/A */ + uint8_t reserved2b0; /* Byte offset 0x2b0, CSR Addr 0x54158, Direction=N/A */ + uint8_t reserved2b1; /* Byte offset 0x2b1, CSR Addr 0x54158, Direction=N/A */ + uint8_t reserved2b2; /* Byte offset 0x2b2, CSR Addr 0x54159, Direction=N/A */ + uint8_t reserved2b3; /* Byte offset 0x2b3, CSR Addr 0x54159, Direction=N/A */ + uint8_t reserved2b4; /* Byte offset 0x2b4, CSR Addr 0x5415a, Direction=N/A */ + uint8_t reserved2b5; /* Byte offset 0x2b5, CSR Addr 0x5415a, Direction=N/A */ + uint8_t reserved2b6; /* Byte offset 0x2b6, CSR Addr 0x5415b, Direction=N/A */ + uint8_t reserved2b7; /* Byte offset 0x2b7, CSR Addr 0x5415b, Direction=N/A */ + uint8_t reserved2b8; /* Byte offset 0x2b8, CSR Addr 0x5415c, Direction=N/A */ + uint8_t reserved2b9; /* Byte offset 0x2b9, CSR Addr 0x5415c, Direction=N/A */ + uint8_t reserved2ba; /* Byte offset 0x2ba, CSR Addr 0x5415d, Direction=N/A */ + uint8_t reserved2bb; /* Byte offset 0x2bb, CSR Addr 0x5415d, Direction=N/A */ + uint8_t reserved2bc; /* Byte offset 0x2bc, CSR Addr 0x5415e, Direction=N/A */ + uint8_t reserved2bd; /* Byte offset 0x2bd, CSR Addr 0x5415e, Direction=N/A */ + uint8_t reserved2be; /* Byte offset 0x2be, CSR Addr 0x5415f, Direction=N/A */ + uint8_t reserved2bf; /* Byte offset 0x2bf, CSR Addr 0x5415f, Direction=N/A */ + uint8_t reserved2c0; /* Byte offset 0x2c0, CSR Addr 0x54160, Direction=N/A */ + uint8_t reserved2c1; /* Byte offset 0x2c1, CSR Addr 0x54160, Direction=N/A */ + uint8_t reserved2c2; /* Byte offset 0x2c2, CSR Addr 0x54161, Direction=N/A */ + uint8_t reserved2c3; /* Byte offset 0x2c3, CSR Addr 0x54161, Direction=N/A */ + uint8_t reserved2c4; /* Byte offset 0x2c4, CSR Addr 0x54162, Direction=N/A */ + uint8_t reserved2c5; /* Byte offset 0x2c5, CSR Addr 0x54162, Direction=N/A */ + uint8_t reserved2c6; /* Byte offset 0x2c6, CSR Addr 0x54163, Direction=N/A */ + uint8_t reserved2c7; /* Byte offset 0x2c7, CSR Addr 0x54163, Direction=N/A */ + uint8_t reserved2c8; /* Byte offset 0x2c8, CSR Addr 0x54164, Direction=N/A */ + uint8_t reserved2c9; /* Byte offset 0x2c9, CSR Addr 0x54164, Direction=N/A */ + uint8_t reserved2ca; /* Byte offset 0x2ca, CSR Addr 0x54165, Direction=N/A */ + uint8_t reserved2cb; /* Byte offset 0x2cb, CSR Addr 0x54165, Direction=N/A */ + uint8_t reserved2cc; /* Byte offset 0x2cc, CSR Addr 0x54166, Direction=N/A */ + uint8_t reserved2cd; /* Byte offset 0x2cd, CSR Addr 0x54166, Direction=N/A */ + uint8_t reserved2ce; /* Byte offset 0x2ce, CSR Addr 0x54167, Direction=N/A */ + uint8_t reserved2cf; /* Byte offset 0x2cf, CSR Addr 0x54167, Direction=N/A */ + uint8_t reserved2d0; /* Byte offset 0x2d0, CSR Addr 0x54168, Direction=N/A */ + uint8_t reserved2d1; /* Byte offset 0x2d1, CSR Addr 0x54168, Direction=N/A */ + uint8_t reserved2d2; /* Byte offset 0x2d2, CSR Addr 0x54169, Direction=N/A */ + uint8_t reserved2d3; /* Byte offset 0x2d3, CSR Addr 0x54169, Direction=N/A */ + uint8_t reserved2d4; /* Byte offset 0x2d4, CSR Addr 0x5416a, Direction=N/A */ + uint8_t reserved2d5; /* Byte offset 0x2d5, CSR Addr 0x5416a, Direction=N/A */ + uint8_t reserved2d6; /* Byte offset 0x2d6, CSR Addr 0x5416b, Direction=N/A */ + uint8_t reserved2d7; /* Byte offset 0x2d7, CSR Addr 0x5416b, Direction=N/A */ + uint8_t reserved2d8; /* Byte offset 0x2d8, CSR Addr 0x5416c, Direction=N/A */ + uint8_t reserved2d9; /* Byte offset 0x2d9, CSR Addr 0x5416c, Direction=N/A */ + uint8_t reserved2da; /* Byte offset 0x2da, CSR Addr 0x5416d, Direction=N/A */ + uint8_t reserved2db; /* Byte offset 0x2db, CSR Addr 0x5416d, Direction=N/A */ + uint8_t reserved2dc; /* Byte offset 0x2dc, CSR Addr 0x5416e, Direction=N/A */ + uint8_t reserved2dd; /* Byte offset 0x2dd, CSR Addr 0x5416e, Direction=N/A */ + uint8_t reserved2de; /* Byte offset 0x2de, CSR Addr 0x5416f, Direction=N/A */ + uint8_t reserved2df; /* Byte offset 0x2df, CSR Addr 0x5416f, Direction=N/A */ + uint8_t reserved2e0; /* Byte offset 0x2e0, CSR Addr 0x54170, Direction=N/A */ + uint8_t reserved2e1; /* Byte offset 0x2e1, CSR Addr 0x54170, Direction=N/A */ + uint8_t reserved2e2; /* Byte offset 0x2e2, CSR Addr 0x54171, Direction=N/A */ + uint8_t reserved2e3; /* Byte offset 0x2e3, CSR Addr 0x54171, Direction=N/A */ + uint8_t reserved2e4; /* Byte offset 0x2e4, CSR Addr 0x54172, Direction=N/A */ + uint8_t reserved2e5; /* Byte offset 0x2e5, CSR Addr 0x54172, Direction=N/A */ + uint8_t reserved2e6; /* Byte offset 0x2e6, CSR Addr 0x54173, Direction=N/A */ + uint8_t reserved2e7; /* Byte offset 0x2e7, CSR Addr 0x54173, Direction=N/A */ + uint8_t reserved2e8; /* Byte offset 0x2e8, CSR Addr 0x54174, Direction=N/A */ + uint8_t reserved2e9; /* Byte offset 0x2e9, CSR Addr 0x54174, Direction=N/A */ + uint8_t reserved2ea; /* Byte offset 0x2ea, CSR Addr 0x54175, Direction=N/A */ + uint8_t reserved2eb; /* Byte offset 0x2eb, CSR Addr 0x54175, Direction=N/A */ + uint8_t reserved2ec; /* Byte offset 0x2ec, CSR Addr 0x54176, Direction=N/A */ + uint8_t reserved2ed; /* Byte offset 0x2ed, CSR Addr 0x54176, Direction=N/A */ + uint8_t reserved2ee; /* Byte offset 0x2ee, CSR Addr 0x54177, Direction=N/A */ + uint8_t reserved2ef; /* Byte offset 0x2ef, CSR Addr 0x54177, Direction=N/A */ + uint8_t reserved2f0; /* Byte offset 0x2f0, CSR Addr 0x54178, Direction=N/A */ + uint8_t reserved2f1; /* Byte offset 0x2f1, CSR Addr 0x54178, Direction=N/A */ + uint8_t reserved2f2; /* Byte offset 0x2f2, CSR Addr 0x54179, Direction=N/A */ + uint8_t reserved2f3; /* Byte offset 0x2f3, CSR Addr 0x54179, Direction=N/A */ + uint8_t reserved2f4; /* Byte offset 0x2f4, CSR Addr 0x5417a, Direction=N/A */ + uint8_t reserved2f5; /* Byte offset 0x2f5, CSR Addr 0x5417a, Direction=N/A */ + uint8_t reserved2f6; /* Byte offset 0x2f6, CSR Addr 0x5417b, Direction=N/A */ + uint8_t reserved2f7; /* Byte offset 0x2f7, CSR Addr 0x5417b, Direction=N/A */ + uint8_t reserved2f8; /* Byte offset 0x2f8, CSR Addr 0x5417c, Direction=N/A */ + uint8_t reserved2f9; /* Byte offset 0x2f9, CSR Addr 0x5417c, Direction=N/A */ + uint8_t reserved2fa; /* Byte offset 0x2fa, CSR Addr 0x5417d, Direction=N/A */ + uint8_t reserved2fb; /* Byte offset 0x2fb, CSR Addr 0x5417d, Direction=N/A */ + uint8_t reserved2fc; /* Byte offset 0x2fc, CSR Addr 0x5417e, Direction=N/A */ + uint8_t reserved2fd; /* Byte offset 0x2fd, CSR Addr 0x5417e, Direction=N/A */ + uint8_t reserved2fe; /* Byte offset 0x2fe, CSR Addr 0x5417f, Direction=N/A */ + uint8_t reserved2ff; /* Byte offset 0x2ff, CSR Addr 0x5417f, Direction=N/A */ + uint8_t reserved300; /* Byte offset 0x300, CSR Addr 0x54180, Direction=N/A */ + uint8_t reserved301; /* Byte offset 0x301, CSR Addr 0x54180, Direction=N/A */ + uint8_t reserved302; /* Byte offset 0x302, CSR Addr 0x54181, Direction=N/A */ + uint8_t reserved303; /* Byte offset 0x303, CSR Addr 0x54181, Direction=N/A */ + uint8_t reserved304; /* Byte offset 0x304, CSR Addr 0x54182, Direction=N/A */ + uint8_t reserved305; /* Byte offset 0x305, CSR Addr 0x54182, Direction=N/A */ + uint8_t reserved306; /* Byte offset 0x306, CSR Addr 0x54183, Direction=N/A */ + uint8_t reserved307; /* Byte offset 0x307, CSR Addr 0x54183, Direction=N/A */ + uint8_t reserved308; /* Byte offset 0x308, CSR Addr 0x54184, Direction=N/A */ + uint8_t reserved309; /* Byte offset 0x309, CSR Addr 0x54184, Direction=N/A */ + uint8_t reserved30a; /* Byte offset 0x30a, CSR Addr 0x54185, Direction=N/A */ + uint8_t reserved30b; /* Byte offset 0x30b, CSR Addr 0x54185, Direction=N/A */ + uint8_t reserved30c; /* Byte offset 0x30c, CSR Addr 0x54186, Direction=N/A */ + uint8_t reserved30d; /* Byte offset 0x30d, CSR Addr 0x54186, Direction=N/A */ + uint8_t reserved30e; /* Byte offset 0x30e, CSR Addr 0x54187, Direction=N/A */ + uint8_t reserved30f; /* Byte offset 0x30f, CSR Addr 0x54187, Direction=N/A */ + uint8_t reserved310; /* Byte offset 0x310, CSR Addr 0x54188, Direction=N/A */ + uint8_t reserved311; /* Byte offset 0x311, CSR Addr 0x54188, Direction=N/A */ + uint8_t reserved312; /* Byte offset 0x312, CSR Addr 0x54189, Direction=N/A */ + uint8_t reserved313; /* Byte offset 0x313, CSR Addr 0x54189, Direction=N/A */ + uint8_t reserved314; /* Byte offset 0x314, CSR Addr 0x5418a, Direction=N/A */ + uint8_t reserved315; /* Byte offset 0x315, CSR Addr 0x5418a, Direction=N/A */ + uint8_t reserved316; /* Byte offset 0x316, CSR Addr 0x5418b, Direction=N/A */ + uint8_t reserved317; /* Byte offset 0x317, CSR Addr 0x5418b, Direction=N/A */ + uint8_t reserved318; /* Byte offset 0x318, CSR Addr 0x5418c, Direction=N/A */ + uint8_t reserved319; /* Byte offset 0x319, CSR Addr 0x5418c, Direction=N/A */ + uint8_t reserved31a; /* Byte offset 0x31a, CSR Addr 0x5418d, Direction=N/A */ + uint8_t reserved31b; /* Byte offset 0x31b, CSR Addr 0x5418d, Direction=N/A */ + uint8_t reserved31c; /* Byte offset 0x31c, CSR Addr 0x5418e, Direction=N/A */ + uint8_t reserved31d; /* Byte offset 0x31d, CSR Addr 0x5418e, Direction=N/A */ + uint8_t reserved31e; /* Byte offset 0x31e, CSR Addr 0x5418f, Direction=N/A */ + uint8_t reserved31f; /* Byte offset 0x31f, CSR Addr 0x5418f, Direction=N/A */ + uint8_t reserved320; /* Byte offset 0x320, CSR Addr 0x54190, Direction=N/A */ + uint8_t reserved321; /* Byte offset 0x321, CSR Addr 0x54190, Direction=N/A */ + uint8_t reserved322; /* Byte offset 0x322, CSR Addr 0x54191, Direction=N/A */ + uint8_t reserved323; /* Byte offset 0x323, CSR Addr 0x54191, Direction=N/A */ + uint8_t reserved324; /* Byte offset 0x324, CSR Addr 0x54192, Direction=N/A */ + uint8_t reserved325; /* Byte offset 0x325, CSR Addr 0x54192, Direction=N/A */ + uint8_t reserved326; /* Byte offset 0x326, CSR Addr 0x54193, Direction=N/A */ + uint8_t reserved327; /* Byte offset 0x327, CSR Addr 0x54193, Direction=N/A */ + uint8_t reserved328; /* Byte offset 0x328, CSR Addr 0x54194, Direction=N/A */ + uint8_t reserved329; /* Byte offset 0x329, CSR Addr 0x54194, Direction=N/A */ + uint8_t reserved32a; /* Byte offset 0x32a, CSR Addr 0x54195, Direction=N/A */ + uint8_t reserved32b; /* Byte offset 0x32b, CSR Addr 0x54195, Direction=N/A */ + uint8_t reserved32c; /* Byte offset 0x32c, CSR Addr 0x54196, Direction=N/A */ + uint8_t reserved32d; /* Byte offset 0x32d, CSR Addr 0x54196, Direction=N/A */ + uint8_t reserved32e; /* Byte offset 0x32e, CSR Addr 0x54197, Direction=N/A */ + uint8_t reserved32f; /* Byte offset 0x32f, CSR Addr 0x54197, Direction=N/A */ + uint8_t reserved330; /* Byte offset 0x330, CSR Addr 0x54198, Direction=N/A */ + uint8_t reserved331; /* Byte offset 0x331, CSR Addr 0x54198, Direction=N/A */ + uint8_t reserved332; /* Byte offset 0x332, CSR Addr 0x54199, Direction=N/A */ + uint8_t reserved333; /* Byte offset 0x333, CSR Addr 0x54199, Direction=N/A */ + uint8_t reserved334; /* Byte offset 0x334, CSR Addr 0x5419a, Direction=N/A */ + uint8_t reserved335; /* Byte offset 0x335, CSR Addr 0x5419a, Direction=N/A */ + uint8_t reserved336; /* Byte offset 0x336, CSR Addr 0x5419b, Direction=N/A */ + uint8_t reserved337; /* Byte offset 0x337, CSR Addr 0x5419b, Direction=N/A */ + uint8_t reserved338; /* Byte offset 0x338, CSR Addr 0x5419c, Direction=N/A */ + uint8_t reserved339; /* Byte offset 0x339, CSR Addr 0x5419c, Direction=N/A */ + uint8_t reserved33a; /* Byte offset 0x33a, CSR Addr 0x5419d, Direction=N/A */ + uint8_t reserved33b; /* Byte offset 0x33b, CSR Addr 0x5419d, Direction=N/A */ + uint8_t reserved33c; /* Byte offset 0x33c, CSR Addr 0x5419e, Direction=N/A */ + uint8_t reserved33d; /* Byte offset 0x33d, CSR Addr 0x5419e, Direction=N/A */ + uint8_t reserved33e; /* Byte offset 0x33e, CSR Addr 0x5419f, Direction=N/A */ + uint8_t reserved33f; /* Byte offset 0x33f, CSR Addr 0x5419f, Direction=N/A */ + uint8_t reserved340; /* Byte offset 0x340, CSR Addr 0x541a0, Direction=N/A */ + uint8_t reserved341; /* Byte offset 0x341, CSR Addr 0x541a0, Direction=N/A */ + uint8_t reserved342; /* Byte offset 0x342, CSR Addr 0x541a1, Direction=N/A */ + uint8_t reserved343; /* Byte offset 0x343, CSR Addr 0x541a1, Direction=N/A */ + uint8_t reserved344; /* Byte offset 0x344, CSR Addr 0x541a2, Direction=N/A */ + uint8_t reserved345; /* Byte offset 0x345, CSR Addr 0x541a2, Direction=N/A */ + uint8_t reserved346; /* Byte offset 0x346, CSR Addr 0x541a3, Direction=N/A */ + uint8_t reserved347; /* Byte offset 0x347, CSR Addr 0x541a3, Direction=N/A */ + uint8_t reserved348; /* Byte offset 0x348, CSR Addr 0x541a4, Direction=N/A */ + uint8_t reserved349; /* Byte offset 0x349, CSR Addr 0x541a4, Direction=N/A */ + uint8_t reserved34a; /* Byte offset 0x34a, CSR Addr 0x541a5, Direction=N/A */ + uint8_t reserved34b; /* Byte offset 0x34b, CSR Addr 0x541a5, Direction=N/A */ + uint8_t reserved34c; /* Byte offset 0x34c, CSR Addr 0x541a6, Direction=N/A */ + uint8_t reserved34d; /* Byte offset 0x34d, CSR Addr 0x541a6, Direction=N/A */ + uint8_t reserved34e; /* Byte offset 0x34e, CSR Addr 0x541a7, Direction=N/A */ + uint8_t reserved34f; /* Byte offset 0x34f, CSR Addr 0x541a7, Direction=N/A */ + uint8_t reserved350; /* Byte offset 0x350, CSR Addr 0x541a8, Direction=N/A */ + uint8_t reserved351; /* Byte offset 0x351, CSR Addr 0x541a8, Direction=N/A */ + uint8_t reserved352; /* Byte offset 0x352, CSR Addr 0x541a9, Direction=N/A */ + uint8_t reserved353; /* Byte offset 0x353, CSR Addr 0x541a9, Direction=N/A */ + uint8_t reserved354; /* Byte offset 0x354, CSR Addr 0x541aa, Direction=N/A */ + uint8_t reserved355; /* Byte offset 0x355, CSR Addr 0x541aa, Direction=N/A */ + uint8_t reserved356; /* Byte offset 0x356, CSR Addr 0x541ab, Direction=N/A */ + uint8_t reserved357; /* Byte offset 0x357, CSR Addr 0x541ab, Direction=N/A */ + uint8_t reserved358; /* Byte offset 0x358, CSR Addr 0x541ac, Direction=N/A */ + uint8_t reserved359; /* Byte offset 0x359, CSR Addr 0x541ac, Direction=N/A */ + uint8_t reserved35a; /* Byte offset 0x35a, CSR Addr 0x541ad, Direction=N/A */ + uint8_t reserved35b; /* Byte offset 0x35b, CSR Addr 0x541ad, Direction=N/A */ + uint8_t reserved35c; /* Byte offset 0x35c, CSR Addr 0x541ae, Direction=N/A */ + uint8_t reserved35d; /* Byte offset 0x35d, CSR Addr 0x541ae, Direction=N/A */ + uint8_t reserved35e; /* Byte offset 0x35e, CSR Addr 0x541af, Direction=N/A */ + uint8_t reserved35f; /* Byte offset 0x35f, CSR Addr 0x541af, Direction=N/A */ + uint8_t reserved360; /* Byte offset 0x360, CSR Addr 0x541b0, Direction=N/A */ + uint8_t reserved361; /* Byte offset 0x361, CSR Addr 0x541b0, Direction=N/A */ + uint8_t reserved362; /* Byte offset 0x362, CSR Addr 0x541b1, Direction=N/A */ + uint8_t reserved363; /* Byte offset 0x363, CSR Addr 0x541b1, Direction=N/A */ + uint8_t reserved364; /* Byte offset 0x364, CSR Addr 0x541b2, Direction=N/A */ + uint8_t reserved365; /* Byte offset 0x365, CSR Addr 0x541b2, Direction=N/A */ + uint8_t reserved366; /* Byte offset 0x366, CSR Addr 0x541b3, Direction=N/A */ + uint8_t reserved367; /* Byte offset 0x367, CSR Addr 0x541b3, Direction=N/A */ + uint8_t reserved368; /* Byte offset 0x368, CSR Addr 0x541b4, Direction=N/A */ + uint8_t reserved369; /* Byte offset 0x369, CSR Addr 0x541b4, Direction=N/A */ + uint8_t reserved36a; /* Byte offset 0x36a, CSR Addr 0x541b5, Direction=N/A */ + uint8_t reserved36b; /* Byte offset 0x36b, CSR Addr 0x541b5, Direction=N/A */ + uint8_t reserved36c; /* Byte offset 0x36c, CSR Addr 0x541b6, Direction=N/A */ + uint8_t reserved36d; /* Byte offset 0x36d, CSR Addr 0x541b6, Direction=N/A */ + uint8_t reserved36e; /* Byte offset 0x36e, CSR Addr 0x541b7, Direction=N/A */ + uint8_t reserved36f; /* Byte offset 0x36f, CSR Addr 0x541b7, Direction=N/A */ + uint8_t reserved370; /* Byte offset 0x370, CSR Addr 0x541b8, Direction=N/A */ + uint8_t reserved371; /* Byte offset 0x371, CSR Addr 0x541b8, Direction=N/A */ + uint8_t reserved372; /* Byte offset 0x372, CSR Addr 0x541b9, Direction=N/A */ + uint8_t reserved373; /* Byte offset 0x373, CSR Addr 0x541b9, Direction=N/A */ + uint8_t reserved374; /* Byte offset 0x374, CSR Addr 0x541ba, Direction=N/A */ + uint8_t reserved375; /* Byte offset 0x375, CSR Addr 0x541ba, Direction=N/A */ + uint8_t reserved376; /* Byte offset 0x376, CSR Addr 0x541bb, Direction=N/A */ + uint8_t reserved377; /* Byte offset 0x377, CSR Addr 0x541bb, Direction=N/A */ + uint8_t reserved378; /* Byte offset 0x378, CSR Addr 0x541bc, Direction=N/A */ + uint8_t reserved379; /* Byte offset 0x379, CSR Addr 0x541bc, Direction=N/A */ + uint8_t reserved37a; /* Byte offset 0x37a, CSR Addr 0x541bd, Direction=N/A */ + uint8_t reserved37b; /* Byte offset 0x37b, CSR Addr 0x541bd, Direction=N/A */ + uint8_t reserved37c; /* Byte offset 0x37c, CSR Addr 0x541be, Direction=N/A */ + uint8_t reserved37d; /* Byte offset 0x37d, CSR Addr 0x541be, Direction=N/A */ + uint8_t reserved37e; /* Byte offset 0x37e, CSR Addr 0x541bf, Direction=N/A */ + uint8_t reserved37f; /* Byte offset 0x37f, CSR Addr 0x541bf, Direction=N/A */ + uint8_t reserved380; /* Byte offset 0x380, CSR Addr 0x541c0, Direction=N/A */ + uint8_t reserved381; /* Byte offset 0x381, CSR Addr 0x541c0, Direction=N/A */ + uint8_t reserved382; /* Byte offset 0x382, CSR Addr 0x541c1, Direction=N/A */ + uint8_t reserved383; /* Byte offset 0x383, CSR Addr 0x541c1, Direction=N/A */ + uint8_t reserved384; /* Byte offset 0x384, CSR Addr 0x541c2, Direction=N/A */ + uint8_t reserved385; /* Byte offset 0x385, CSR Addr 0x541c2, Direction=N/A */ + uint8_t reserved386; /* Byte offset 0x386, CSR Addr 0x541c3, Direction=N/A */ + uint8_t reserved387; /* Byte offset 0x387, CSR Addr 0x541c3, Direction=N/A */ + uint8_t reserved388; /* Byte offset 0x388, CSR Addr 0x541c4, Direction=N/A */ + uint8_t reserved389; /* Byte offset 0x389, CSR Addr 0x541c4, Direction=N/A */ + uint8_t reserved38a; /* Byte offset 0x38a, CSR Addr 0x541c5, Direction=N/A */ + uint8_t reserved38b; /* Byte offset 0x38b, CSR Addr 0x541c5, Direction=N/A */ + uint8_t reserved38c; /* Byte offset 0x38c, CSR Addr 0x541c6, Direction=N/A */ + uint8_t reserved38d; /* Byte offset 0x38d, CSR Addr 0x541c6, Direction=N/A */ + uint8_t reserved38e; /* Byte offset 0x38e, CSR Addr 0x541c7, Direction=N/A */ + uint8_t reserved38f; /* Byte offset 0x38f, CSR Addr 0x541c7, Direction=N/A */ + uint8_t reserved390; /* Byte offset 0x390, CSR Addr 0x541c8, Direction=N/A */ + uint8_t reserved391; /* Byte offset 0x391, CSR Addr 0x541c8, Direction=N/A */ + uint8_t reserved392; /* Byte offset 0x392, CSR Addr 0x541c9, Direction=N/A */ + uint8_t reserved393; /* Byte offset 0x393, CSR Addr 0x541c9, Direction=N/A */ + uint8_t reserved394; /* Byte offset 0x394, CSR Addr 0x541ca, Direction=N/A */ + uint8_t reserved395; /* Byte offset 0x395, CSR Addr 0x541ca, Direction=N/A */ + uint8_t reserved396; /* Byte offset 0x396, CSR Addr 0x541cb, Direction=N/A */ + uint8_t reserved397; /* Byte offset 0x397, CSR Addr 0x541cb, Direction=N/A */ + uint8_t reserved398; /* Byte offset 0x398, CSR Addr 0x541cc, Direction=N/A */ + uint8_t reserved399; /* Byte offset 0x399, CSR Addr 0x541cc, Direction=N/A */ + uint8_t reserved39a; /* Byte offset 0x39a, CSR Addr 0x541cd, Direction=N/A */ + uint8_t reserved39b; /* Byte offset 0x39b, CSR Addr 0x541cd, Direction=N/A */ + uint8_t reserved39c; /* Byte offset 0x39c, CSR Addr 0x541ce, Direction=N/A */ + uint8_t reserved39d; /* Byte offset 0x39d, CSR Addr 0x541ce, Direction=N/A */ + uint8_t reserved39e; /* Byte offset 0x39e, CSR Addr 0x541cf, Direction=N/A */ + uint8_t reserved39f; /* Byte offset 0x39f, CSR Addr 0x541cf, Direction=N/A */ + uint8_t reserved3a0; /* Byte offset 0x3a0, CSR Addr 0x541d0, Direction=N/A */ + uint8_t reserved3a1; /* Byte offset 0x3a1, CSR Addr 0x541d0, Direction=N/A */ + uint8_t reserved3a2; /* Byte offset 0x3a2, CSR Addr 0x541d1, Direction=N/A */ + uint8_t reserved3a3; /* Byte offset 0x3a3, CSR Addr 0x541d1, Direction=N/A */ + uint8_t reserved3a4; /* Byte offset 0x3a4, CSR Addr 0x541d2, Direction=N/A */ + uint8_t reserved3a5; /* Byte offset 0x3a5, CSR Addr 0x541d2, Direction=N/A */ + uint8_t reserved3a6; /* Byte offset 0x3a6, CSR Addr 0x541d3, Direction=N/A */ + uint8_t reserved3a7; /* Byte offset 0x3a7, CSR Addr 0x541d3, Direction=N/A */ + uint8_t reserved3a8; /* Byte offset 0x3a8, CSR Addr 0x541d4, Direction=N/A */ + uint8_t reserved3a9; /* Byte offset 0x3a9, CSR Addr 0x541d4, Direction=N/A */ + uint8_t reserved3aa; /* Byte offset 0x3aa, CSR Addr 0x541d5, Direction=N/A */ + uint8_t reserved3ab; /* Byte offset 0x3ab, CSR Addr 0x541d5, Direction=N/A */ + uint8_t reserved3ac; /* Byte offset 0x3ac, CSR Addr 0x541d6, Direction=N/A */ + uint8_t reserved3ad; /* Byte offset 0x3ad, CSR Addr 0x541d6, Direction=N/A */ + uint8_t reserved3ae; /* Byte offset 0x3ae, CSR Addr 0x541d7, Direction=N/A */ + uint8_t reserved3af; /* Byte offset 0x3af, CSR Addr 0x541d7, Direction=N/A */ + uint8_t reserved3b0; /* Byte offset 0x3b0, CSR Addr 0x541d8, Direction=N/A */ + uint8_t reserved3b1; /* Byte offset 0x3b1, CSR Addr 0x541d8, Direction=N/A */ + uint8_t reserved3b2; /* Byte offset 0x3b2, CSR Addr 0x541d9, Direction=N/A */ + uint8_t reserved3b3; /* Byte offset 0x3b3, CSR Addr 0x541d9, Direction=N/A */ + uint8_t reserved3b4; /* Byte offset 0x3b4, CSR Addr 0x541da, Direction=N/A */ + uint8_t reserved3b5; /* Byte offset 0x3b5, CSR Addr 0x541da, Direction=N/A */ + uint8_t reserved3b6; /* Byte offset 0x3b6, CSR Addr 0x541db, Direction=N/A */ + uint8_t reserved3b7; /* Byte offset 0x3b7, CSR Addr 0x541db, Direction=N/A */ + uint8_t reserved3b8; /* Byte offset 0x3b8, CSR Addr 0x541dc, Direction=N/A */ + uint8_t reserved3b9; /* Byte offset 0x3b9, CSR Addr 0x541dc, Direction=N/A */ + uint8_t reserved3ba; /* Byte offset 0x3ba, CSR Addr 0x541dd, Direction=N/A */ + uint8_t reserved3bb; /* Byte offset 0x3bb, CSR Addr 0x541dd, Direction=N/A */ + uint8_t reserved3bc; /* Byte offset 0x3bc, CSR Addr 0x541de, Direction=N/A */ + uint8_t reserved3bd; /* Byte offset 0x3bd, CSR Addr 0x541de, Direction=N/A */ + uint8_t reserved3be; /* Byte offset 0x3be, CSR Addr 0x541df, Direction=N/A */ + uint8_t reserved3bf; /* Byte offset 0x3bf, CSR Addr 0x541df, Direction=N/A */ + uint8_t reserved3c0; /* Byte offset 0x3c0, CSR Addr 0x541e0, Direction=N/A */ + uint8_t reserved3c1; /* Byte offset 0x3c1, CSR Addr 0x541e0, Direction=N/A */ + uint8_t reserved3c2; /* Byte offset 0x3c2, CSR Addr 0x541e1, Direction=N/A */ + uint8_t reserved3c3; /* Byte offset 0x3c3, CSR Addr 0x541e1, Direction=N/A */ + uint8_t reserved3c4; /* Byte offset 0x3c4, CSR Addr 0x541e2, Direction=N/A */ + uint8_t reserved3c5; /* Byte offset 0x3c5, CSR Addr 0x541e2, Direction=N/A */ + uint8_t reserved3c6; /* Byte offset 0x3c6, CSR Addr 0x541e3, Direction=N/A */ + uint8_t reserved3c7; /* Byte offset 0x3c7, CSR Addr 0x541e3, Direction=N/A */ + uint8_t reserved3c8; /* Byte offset 0x3c8, CSR Addr 0x541e4, Direction=N/A */ + uint8_t reserved3c9; /* Byte offset 0x3c9, CSR Addr 0x541e4, Direction=N/A */ + uint8_t reserved3ca; /* Byte offset 0x3ca, CSR Addr 0x541e5, Direction=N/A */ + uint8_t reserved3cb; /* Byte offset 0x3cb, CSR Addr 0x541e5, Direction=N/A */ + uint8_t reserved3cc; /* Byte offset 0x3cc, CSR Addr 0x541e6, Direction=N/A */ + uint8_t reserved3cd; /* Byte offset 0x3cd, CSR Addr 0x541e6, Direction=N/A */ + uint8_t reserved3ce; /* Byte offset 0x3ce, CSR Addr 0x541e7, Direction=N/A */ + uint8_t reserved3cf; /* Byte offset 0x3cf, CSR Addr 0x541e7, Direction=N/A */ + uint8_t reserved3d0; /* Byte offset 0x3d0, CSR Addr 0x541e8, Direction=N/A */ + uint8_t reserved3d1; /* Byte offset 0x3d1, CSR Addr 0x541e8, Direction=N/A */ + uint8_t reserved3d2; /* Byte offset 0x3d2, CSR Addr 0x541e9, Direction=N/A */ + uint8_t reserved3d3; /* Byte offset 0x3d3, CSR Addr 0x541e9, Direction=N/A */ + uint8_t reserved3d4; /* Byte offset 0x3d4, CSR Addr 0x541ea, Direction=N/A */ + uint8_t reserved3d5; /* Byte offset 0x3d5, CSR Addr 0x541ea, Direction=N/A */ + uint8_t reserved3d6; /* Byte offset 0x3d6, CSR Addr 0x541eb, Direction=N/A */ + uint8_t reserved3d7; /* Byte offset 0x3d7, CSR Addr 0x541eb, Direction=N/A */ + uint8_t reserved3d8; /* Byte offset 0x3d8, CSR Addr 0x541ec, Direction=N/A */ + uint8_t reserved3d9; /* Byte offset 0x3d9, CSR Addr 0x541ec, Direction=N/A */ + uint8_t reserved3da; /* Byte offset 0x3da, CSR Addr 0x541ed, Direction=N/A */ + uint8_t reserved3db; /* Byte offset 0x3db, CSR Addr 0x541ed, Direction=N/A */ + uint8_t reserved3dc; /* Byte offset 0x3dc, CSR Addr 0x541ee, Direction=N/A */ + uint8_t reserved3dd; /* Byte offset 0x3dd, CSR Addr 0x541ee, Direction=N/A */ + uint8_t reserved3de; /* Byte offset 0x3de, CSR Addr 0x541ef, Direction=N/A */ + uint8_t reserved3df; /* Byte offset 0x3df, CSR Addr 0x541ef, Direction=N/A */ + uint8_t reserved3e0; /* Byte offset 0x3e0, CSR Addr 0x541f0, Direction=N/A */ + uint8_t reserved3e1; /* Byte offset 0x3e1, CSR Addr 0x541f0, Direction=N/A */ + uint8_t reserved3e2; /* Byte offset 0x3e2, CSR Addr 0x541f1, Direction=N/A */ + uint8_t reserved3e3; /* Byte offset 0x3e3, CSR Addr 0x541f1, Direction=N/A */ + uint8_t reserved3e4; /* Byte offset 0x3e4, CSR Addr 0x541f2, Direction=N/A */ + uint8_t reserved3e5; /* Byte offset 0x3e5, CSR Addr 0x541f2, Direction=N/A */ + uint8_t reserved3e6; /* Byte offset 0x3e6, CSR Addr 0x541f3, Direction=N/A */ + uint8_t reserved3e7; /* Byte offset 0x3e7, CSR Addr 0x541f3, Direction=N/A */ + uint8_t reserved3e8; /* Byte offset 0x3e8, CSR Addr 0x541f4, Direction=N/A */ + uint8_t reserved3e9; /* Byte offset 0x3e9, CSR Addr 0x541f4, Direction=N/A */ + uint8_t reserved3ea; /* Byte offset 0x3ea, CSR Addr 0x541f5, Direction=N/A */ + uint8_t reserved3eb; /* Byte offset 0x3eb, CSR Addr 0x541f5, Direction=N/A */ + uint8_t reserved3ec; /* Byte offset 0x3ec, CSR Addr 0x541f6, Direction=N/A */ + uint8_t reserved3ed; /* Byte offset 0x3ed, CSR Addr 0x541f6, Direction=N/A */ + uint8_t reserved3ee; /* Byte offset 0x3ee, CSR Addr 0x541f7, Direction=N/A */ + uint8_t reserved3ef; /* Byte offset 0x3ef, CSR Addr 0x541f7, Direction=N/A */ + uint8_t reserved3f0; /* Byte offset 0x3f0, CSR Addr 0x541f8, Direction=N/A */ + uint8_t reserved3f1; /* Byte offset 0x3f1, CSR Addr 0x541f8, Direction=N/A */ + uint8_t reserved3f2; /* Byte offset 0x3f2, CSR Addr 0x541f9, Direction=N/A */ + uint8_t reserved3f3; /* Byte offset 0x3f3, CSR Addr 0x541f9, Direction=N/A */ + uint8_t reserved3f4; /* Byte offset 0x3f4, CSR Addr 0x541fa, Direction=N/A */ + uint8_t reserved3f5; /* Byte offset 0x3f5, CSR Addr 0x541fa, Direction=N/A */ + uint16_t alt_cas_l; /* + * Byte offset 0x3f6, CSR Addr 0x541fb, Direction=in + * This field must be populated if RdDBI is enabled + * (applicable when mr5[A12] == 1). + * RdDBI is dynamically disabled in certain training steps, + * and so the [RdDBI disabled] CAS Latency must be provided + * in this field. + * The required encoding is as follows: + * alt_cas_l[0] == 0: use value in mr0 + * alt_cas_l[0] == 1: use value in alt_cas_l, i.e., + * mr0{A[12],A[6],A[5],A[4],A[2]} = alt_cas_l[12,6,5,4,2] + * Other bits are ignored + */ + uint8_t alt_wcas_l; /* + * Byte offset 0x3f8, CSR Addr 0x541fc, Direction=In + * This field must be populated if 2tCK write preambles are + * enabled (applicable when mr4[A12] == 1). + * 2tCK write prambles are dynamically disabled in certain + * training steps, and so the [1tCK write preamble] WCAS + * Latency must be provided in this field. + * The required encoding is as follows: + * alt_wcas_l[0] == 0: use value in mr2 + * alt_wcas_l[0] == 1: use value in alt_wcas_l, i.e., + * mr2{A[5],A[4],A[3]} = alt_wcas_l[5,4,3] + * Other bits are ignored + */ + uint8_t d4misc; /* + * Byte offset 0x3f9, CSR Addr 0x541fc, Direction=In + * Contains various options for training DDR4 Devices. + * + * Bit fields: + * + * d4misc[7:5,2,1] RFU, must be zero + * + * d4misc[0] = protect memory reset + * 0x1 = dfi_reset_n cannot control BP_MEMRESERT_L to + * devices after training. + * 0x0 = dfi_resert_n can control BP_MEMRESERT_L to + * devices after training + * + * d4misc[3]: reserved + * + * d4misc[4]: DRAM reset mode + * 0x1 = Do not reset DRAM during devinit + * 0x0 = Reset DRAM during devinit + */ +} __packed __aligned(2); + +#endif /* MNPMUSRAMMSGBLOCK_DDR4_H */ diff --git a/drivers/st/ddr/phy/firmware/include/mnpmusrammsgblock_lpddr4.h b/drivers/st/ddr/phy/firmware/include/mnpmusrammsgblock_lpddr4.h new file mode 100644 index 000000000..fb1cd58be --- /dev/null +++ b/drivers/st/ddr/phy/firmware/include/mnpmusrammsgblock_lpddr4.h @@ -0,0 +1,925 @@ +/* + * Copyright (C) 2021-2024, STMicroelectronics - All Rights Reserved + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef MNPMUSRAMMSGBLOCK_LPDDR4_H +#define MNPMUSRAMMSGBLOCK_LPDDR4_H + +/* LPDDR4_1D training firmware message block structure + * + * Please refer to the Training Firmware App Note for futher information about + * the usage for Message Block. + */ +struct pmu_smb_ddr_1d { + uint8_t reserved00; /* + * Byte offset 0x00, CSR Addr 0x54000, Direction=In + * reserved00[0:4] RFU, must be zero + * + * reserved00[5] = Quick Rd2D during 1D Training + * 0x1 = Read Deskew will begin by enabling and quickly + * training the phy's per-lane reference voltages. + * Training the vrefDACs CSRs will increase the maximum 1D + * training time by around half a millisecond, but will + * improve 1D training accuracy on systems with + * significant voltage-offsets between lane read eyes. + * 0x0 = Read Deskew will assume the messageblock's + * phyVref setting is optimal for all lanes. + * + * reserved00[6] = Enable High Effort WrDQ1D + * 0x1 = WrDQ1D will conditionally retry training at + * several extra RxClkDly Timings. This will increase the + * maximum 1D training time by up to 4 extra iterations of + * WrDQ1D. This is only required in systems that suffer + * from very large, asymmetric eye-collapse when receiving + * PRBS patterns. + * 0x0 = WrDQ1D assume rxClkDly values found by SI + * Friendly RdDqs1D will work for receiving PRBS patterns + * + * reserved00[7] = Optimize for the special hard macros in + * TSMC28. + * 0x1 = set if the phy being trained was manufactured in + * any TSMC28 process node. + * 0x0 = otherwise, when not training a TSMC28 phy, leave + * this field as 0. + */ + uint8_t msgmisc; /* + * Byte offset 0x01, CSR Addr 0x54000, Direction=In + * Contains various global options for training. + * + * Bit fields: + * + * msgmisc[0] MTESTEnable + * 0x1 = Pulse primary digital test output bump at the end + * of each major training stage. This enables observation + * of training stage completion by observing the digital + * test output. + * 0x0 = Do not pulse primary digital test output bump + * + * msgmisc[1] SimulationOnlyReset + * 0x1 = Verilog only simulation option to shorten + * duration of DRAM reset pulse length to 1ns. + * Must never be set to 1 in silicon. + * 0x0 = Use reset pulse length specified by JEDEC + * standard. + * + * msgmisc[2] SimulationOnlyTraining + * 0x1 = Verilog only simulation option to shorten the + * duration of the training steps by performing fewer + * iterations. + * Must never be set to 1 in silicon. + * 0x0 = Use standard training duration. + * + * msgmisc[3] Disable Boot Clock + * 0x1 = Disable boot frequency clock when initializing + * DRAM. (not recommended) + * 0x0 = Use Boot Frequency Clock + * + * msgmisc[4] Suppress streaming messages, including + * assertions, regardless of hdtctrl setting. + * Stage Completion messages, as well as training completion + * and error messages are still sent depending on hdtctrl + * setting. + * + * msgmisc[5] PerByteMaxRdLat + * 0x1 = Each DBYTE will return dfi_rddata_valid at the + * lowest possible latency. This may result in unaligned + * data between bytes to be returned to the DFI. + * 0x0 = Every DBYTE will return dfi_rddata_valid + * simultaneously. This will ensure that data bytes will + * return aligned accesses to the DFI. + * + * msgmisc[7-6] RFU, must be zero + * + * Notes: + * + * - SimulationOnlyReset and SimulationOnlyTraining can be + * used to speed up simulation run times, and must never + * be used in real silicon. Some VIPs may have checks on + * DRAM reset parameters that may need to be disabled when + * using SimulationOnlyReset. + */ + uint16_t pmurevision; /* + * Byte offset 0x02, CSR Addr 0x54001, Direction=Out + * PMU firmware revision ID + * After training is run, this address will contain the + * revision ID of the firmware + */ + uint8_t pstate; /* + * Byte offset 0x04, CSR Addr 0x54002, Direction=In + * Must be set to the target pstate to be trained + * 0x0 = pstate 0 + * 0x1 = pstate 1 + * 0x2 = pstate 2 + * 0x3 = pstate 3 + * All other encodings are reserved + */ + uint8_t pllbypassen; /* + * Byte offset 0x05, CSR Addr 0x54002, Direction=In + * Set according to whether target pstate uses PHY PLL + * bypass + * 0x0 = PHY PLL is enabled for target pstate + * 0x1 = PHY PLL is bypassed for target pstate + */ + uint16_t dramfreq; /* + * Byte offset 0x06, CSR Addr 0x54003, Direction=In + * DDR data rate for the target pstate in units of MT/s. + * For example enter 0x0640 for DDR1600. + */ + uint8_t dfifreqratio; /* + * Byte offset 0x08, CSR Addr 0x54004, Direction=In + * Frequency ratio betwen DfiCtlClk and SDRAM memclk. + * 0x1 = 1:1 + * 0x2 = 1:2 + * 0x4 = 1:4 + */ + uint8_t bpznresval; /* + * Byte offset 0x09, CSR Addr 0x54004, Direction=In + * Overwrite the value of precision resistor connected to + * Phy BP_ZN + * 0x00 = Do not program. Use current CSR value. + * 0xf0 = 240 Ohm + * 0x78 = 120 Ohm + * 0x28 = 40 Ohm + * All other values are reserved. + * It is recommended to set this to 0x00. + */ + uint8_t phyodtimpedance; /* + * Byte offset 0x0a, CSR Addr 0x54005, Direction=In + * Must be programmed to the termination impedance in ohms + * used by PHY during reads. + * + * 0x0 = Firmware skips programming (must be manually + * programmed by user prior to training start) + * + * See PHY databook for legal termination impedance values. + * + * For digital simulation, any legal value can be used. For + * silicon, the users must determine the correct value + * through SI simulation or other methods. + */ + uint8_t phydrvimpedance; /* + * Byte offset 0x0b, CSR Addr 0x54005, Direction=In + * Must be programmed to the driver impedance in ohms used + * by PHY during writes for all DBYTE drivers + * (DQ/DM/DBI/DQS). + * + * 0x0 = Firmware skips programming (must be manually + * programmed by user prior to training start) + * + * See PHY databook for legal R_on driver impedance values. + * + * For digital simulation, any value can be used that is not + * Hi-Z. For silicon, the users must determine the correct + * value through SI simulation or other methods. + */ + uint8_t phyvref; /* + * Byte offset 0x0c, CSR Addr 0x54006, Direction=In + * Must be programmed with the Vref level to be used by the + * PHY during reads + * + * The units of this field are a percentage of VDDQ + * according to the following equation: + * + * Receiver Vref = VDDQ*phyvref[6:0]/128 + * + * For example to set Vref at 0.25*VDDQ, set this field to + * 0x20. + * + * For digital simulation, any legal value can be used. For + * silicon, the users must calculate the analytical Vref by + * using the impedances, terminations, and series resistance + * present in the system. + */ + uint8_t lp4misc; /* + * Byte offset 0x0d, CSR Addr 0x54006, Direction=In + * Lp4 specific options for training. + * + * Bit fields: + * + * lp4misc[0] Enable dfi_reset_n + * + * 0x0 = (Recommended) PHY internal registers control + * memreset during training, and also after training. + * dfi_reset_n cannot control the PHY BP_MEMRESET_L pin. + * + * 0x1 = Enables dfi_reset_n to control memreset after + * training. PHY Internal registers control memreset + * during training only. To ensure that no glitches occur + * on BP_MEMRESET at the end of training, The MC must + * drive dfi_reset_n=1'b1 _prior to starting training_ + * + * lp4misc[7-1] RFU, must be zero + */ + uint8_t reserved0e; /* + * Byte offset 0x0e, CSR Addr 0x54007, Direction=In + * Bit Field for enabling optional 2D training features + * that impact both Rx2D and Tx2D. + * + * reserved0E[0:3]: bitTimeControl + * input for the amount of data bits 2D writes/reads per DQ + * before deciding if any specific voltage and delay setting + * passes or fails. Every time this input increases by 1, + * the number of 2D data comparisons is doubled. The 2D run + * time will increase proportionally to the number of bit + * times requested per point. + * 0 = 288 bits per point (legacy behavior) + * 1 = 576 bits per point + * 2 = 1.125 kilobits per point + * . . . + * 15 = 9 megabits per point + * + * reserved0E[4]: Exhaustive2D + * 0 = 2D optimization assumes the optimal trained point + * is near the 1D trained point (legacy behavior) + * 1 = 2D optimization searches the entire passing region + * at the cost of run time. Recommended for optimal + * results any time the optimal trained point is expected + * to be near the edges of the eyes instead of near the 1D + * trained point. + * + * reserved0E[5]: Detect Vref Eye Truncation, ignored if + * eyeWeight2DControl == 0. + * 0 = 2D optimizes for the passing region it can measure. + * 1 = For every eye, 2D checks If the legal voltage range + * truncated the eye. If the true voltage margin cannot be + * measured, 2D will optimize heavily for delay margin + * instead of using incomplete voltage margin data. Eyes + * that are not truncated will still be optimized using + * user programmed weights. + * + * reserved0E[6]: eyeWeight2DControl + * 0 = Use 8 bit weights for Delay_Weight2D and + * Voltage_Weight2D and disable TrunkV behavior. + * 1 = Use 4 bit weights for Delay_weight2D and + * Voltage_Weight2D and enable TrunkV behavior. + * + * reserved0E[7]: RFU, must be 0 + */ + uint8_t cstestfail; /* + * Byte offset 0x0f, CSR Addr 0x54007, Direction=Out + * This field will be set if training fails on any rank. + * 0x0 = No failures + * non-zero = one or more ranks failed training + */ + uint16_t sequencectrl; /* + * Byte offset 0x10, CSR Addr 0x54008, Direction=In + * Controls the training steps to be run. Each bit + * corresponds to a training step. + * + * If the bit is set to 1, the training step will run. + * If the bit is set to 0, the training step will be + * skipped. + * + * Training step to bit mapping: + * sequencectrl[0] = Run DevInit - Device/phy + * initialization. Should always be set. + * sequencectrl[1] = Run WrLvl - Write leveling + * sequencectrl[2] = Run RxEn - Read gate training + * sequencectrl[3] = Run RdDQS1D - 1d read dqs training + * sequencectrl[4] = Run WrDQ1D - 1d write dq training + * sequencectrl[5] = RFU, must be zero + * sequencectrl[6] = RFU, must be zero + * sequencectrl[7] = RFU, must be zero + * sequencectrl[8] = Run RdDeskew - Per lane read dq deskew + * training + * sequencectrl[9] = Run MxRdLat - Max read latency training + * sequencectrl[11-10] = RFU, must be zero + * sequencectrl[12] = Run LPCA - CA Training + * sequencectrl[15-13] = RFU, must be zero + */ + uint8_t hdtctrl; /* + * Byte offset 0x12, CSR Addr 0x54009, Direction=In + * To control the total number of debug messages, a + * verbosity subfield (hdtctrl, Hardware Debug Trace + * Control) exists in the message block. Every message has a + * verbosity level associated with it, and as the hdtctrl + * value is increased, less important s messages stop being + * sent through the mailboxes. The meanings of several major + * hdtctrl thresholds are explained below: + * + * 0x04 = Maximal debug messages (e.g., Eye contours) + * 0x05 = Detailed debug messages (e.g. Eye delays) + * 0x0A = Coarse debug messages (e.g. rank information) + * 0xC8 = Stage completion + * 0xC9 = Assertion messages + * 0xFF = Firmware completion messages only + */ + uint8_t reserved13; /* + * Byte offset 0x13, CSR Addr 0x54009, Direction=In + * + * 0 = Default operation, unchanged. + * Others = RD DQ calibration Training steps are completed + * with user specified pattern. + */ + uint8_t reserved14; /* + * Byte offset 0x14, CSR Addr 0x5400a, Direction=In + * Configure rd2D search iteration from a starting seed + * point: + * + * reserved14[5:0]: If reserved14[6] is 0, Number of search + * iterations (if 0, then default is 20); otherwise if this + * value non zero, this value is used as a delta to filter + * out points during the averaging: when averaging over a + * dimension (delay or voltage), the points having a margin + * smaller than the max of the eye in this dimension by at + * least this delta value are filtered out. + * + * reserved14[6]: If set, instead of search, extract center + * using an averaging function over the eye surface area, + * where some points can be filtered out using + * reserved14[5:0] + * + * reserved14[7]: if set, start search with large step size, + * decreasing at each 4 iterations, down to 1 (do not care + * if reserved14[6] is set) + */ + uint8_t reserved15; /* + * Byte offset 0x15, CSR Addr 0x5400a, Direction=In + * Configure wr2D search iteration from a starting seed + * point: + * + * reserved15[5:0]: If reserved15[6] is 0, Number of search + * iterations (if 0, then default is 20); otherwise if this + * value non zero, this value is used as a delta to filter + * out points during the averaging: when averaging over a + * dimension (delay or voltage), the points having a margin + * smaller than the max of the eye in this dimension by at + * least this delta value are filtered out. + * + * reserved15[6]: If set, instead of search, extract center + * using an averaging function over the eye surface area, + * where some points can be filtered out using + * reserved15[5:0] + * + * reserved15[7]: if set, start search with large step size, + * decreasing at each 4 iterations, down to 1 (do not care + * if reserved15[6] is set) + */ + uint8_t dfimrlmargin; /* + * Byte offset 0x16, CSR Addr 0x5400b, Direction=In + * Margin added to smallest passing trained DFI Max Read + * Latency value, in units of DFI clocks. Recommended to be + * >= 1. + * + * This margin must include the maximum positive drift + * expected in tDQSCK over the target temperature and + * voltage range of the users system. + */ + uint8_t reserved17; /* + * Byte offset 0x17, CSR Addr 0x5400b, Direction=In + * Configure DB from which extra info is dump during 2D + * training when maximal debug is set: + * + * reserved17[3:0]: first DB + * + * reserved17[7:4]: number of DB, including first DB (if 0, + * no extra debug per DB is dump) + */ + uint8_t usebroadcastmr; /* + * Byte offset 0x18, CSR Addr 0x5400c, Direction=In + * Training firmware can optionally set per rank mode + * register values for DRAM partial array self-refresh + * features if desired. + * + * 0x0 = Use mr<1:4, 11:14, 16:17, 22, 24>_a0 for rank 0 + * channel A + * Use mr<1:4, 11:14, 16:17, 22, 24>_b0 for rank 0 + * channel B + * Use mr<1:4, 11:14, 16:17, 22, 24>_a1 for rank 1 + * channel A + * Use mr<1:4, 11:14, 16:17, 22, 24>_b1 for rank 1 + * channel B + * + * 0x1 = Use mr<1:4, 11:14, 16:17, 22, 24>_a0 setting for + * all channels/ranks + * + * It is recommended in most LPDDR4 system configurations + * to set this to 1. + * It is recommended in LPDDR4x system configurations to + * set this to 0. + */ + uint8_t lp4quickboot; /* + * Byte offset 0x19, CSR Addr 0x5400c, Direction=In + * Enable Quickboot. It must be set to 0x0 since Quickboot + * is only supported in dedicated Quickboot firmware. + */ + uint8_t reserved1a; /* + * Byte offset 0x1a, CSR Addr 0x5400d, Direction=In + * Input for constraining the range of vref(DQ) values + * training will collect data for, usually reducing training + * time. However, too large of a voltage range may cause + * longer 2D training times while too small of a voltage + * range may truncate passing regions. When in doubt, leave + * this field set to 0. + * Used by 2D stages: Rd2D, Wr2D + * + * reserved1A[0-3]: Rd2D Voltage Range + * 0 = Training will search all phy vref(DQ) settings + * 1 = limit to +/-2 %VDDQ from phyVref + * 2 = limit to +/-4 %VDDQ from phyVref + * . . . + * 15 = limit to +/-30% VDDQ from phyVref + * + * reserved1A[4-7]: Wr2D Voltage Range + * 0 = Training will search all dram vref(DQ) settings + * 1 = limit to +/-2 %VDDQ from mr14 + * 2 = limit to +/-4 %VDDQ from mr14 + * . . . + * 15 = limit to +/-30% VDDQ from mr14 + */ + uint8_t catrainopt; /* + * Byte offset 0x1b, CSR Addr 0x5400d, Direction=In + * CA training option bit field + * [0] CA VREF Training + * 1 = Enable CA VREF Training + * 0 = Disable CA VREF Training + * WARNING: catrainopt[0] must be set to the same value in + * 1D and 2D training. + * + * [1] Train terminated Rank only + * 1 = Only train terminated rank in CA training + * 0 = Train all ranks in CA training + * + * [2-7] RFU must be zero + */ + uint8_t x8mode; /* + * Byte offset 0x1c, CSR Addr 0x5400e, Direction=In + * X8 mode configuration: + * 0x0 = x16 configuration for all devices + * 0xF = x8 configuration for all devices + * All other values are RFU + */ + uint8_t reserved1d; /* Byte offset 0x1d, CSR Addr 0x5400e, Direction=N/A */ + uint8_t reserved1e; /* Byte offset 0x1e, CSR Addr 0x5400f, Direction=N/A */ + uint8_t share2dvrefresult; /* + * Byte offset 0x1f, CSR Addr 0x5400f, Direction=In + * Bitmap that designates the phy's vref source for every + * pstate + * If share2dvrefresult[x] = 0, then after 2D training, + * pstate x will continue using the phyVref provided in + * pstate x's 1D messageblock. + * If share2dvrefresult[x] = 1, then after 2D training, + * pstate x will use the per-lane VrefDAC0/1 CSRs trained by + * 2d training. + */ + uint8_t reserved20; /* Byte offset 0x20, CSR Addr 0x54010, Direction=N/A */ + uint8_t reserved21; /* Byte offset 0x21, CSR Addr 0x54010, Direction=N/A */ + uint16_t phyconfigoverride; /* + * Byte offset 0x22, CSR Addr 0x54011, Direction=In + * Override PhyConfig csr. + * 0x0: Use hardware csr value for PhyConfing + * (recommended) + * Other values: Use value for PhyConfig instead of + * Hardware value. + * + */ + uint8_t enableddqscha; /* + * Byte offset 0x24, CSR Addr 0x54012, Direction=In + * Total number of DQ bits enabled in PHY Channel A + */ + uint8_t cspresentcha; /* + * Byte offset 0x25, CSR Addr 0x54012, Direction=In + * Indicates presence of DRAM at each chip select for PHY + * channel A. + * 0x1 = CS0 is populated with DRAM + * 0x3 = CS0 and CS1 are populated with DRAM + * + * All other encodings are illegal + */ + int8_t cdd_cha_rr_1_0; /* + * Byte offset 0x26, CSR Addr 0x54013, Direction=Out + * This is a signed integer value. + * Read to read critical delay difference from cs 1 to cs 0 + * on Channel A. + */ + int8_t cdd_cha_rr_0_1; /* + * Byte offset 0x27, CSR Addr 0x54013, Direction=Out + * This is a signed integer value. + * Read to read critical delay difference from cs 0 to cs 1 + * on Channel A. + */ + int8_t cdd_cha_rw_1_1; /* + * Byte offset 0x28, CSR Addr 0x54014, Direction=Out + * This is a signed integer value. + * Read to write critical delay difference from cs 1 to cs 1 + * on Channel A. + */ + int8_t cdd_cha_rw_1_0; /* + * Byte offset 0x29, CSR Addr 0x54014, Direction=Out + * This is a signed integer value. + * Read to write critical delay difference from cs 1 to cs 0 + * on Channel A. + */ + int8_t cdd_cha_rw_0_1; /* + * Byte offset 0x2a, CSR Addr 0x54015, Direction=Out + * This is a signed integer value. + * Read to write critical delay difference from cs 0 to cs 1 + * on Channel A. + */ + int8_t cdd_cha_rw_0_0; /* + * Byte offset 0x2b, CSR Addr 0x54015, Direction=Out + * This is a signed integer value. + * Read to write critical delay difference from cs0 to cs 0 + * on Channel A. + */ + int8_t cdd_cha_wr_1_1; /* + * Byte offset 0x2c, CSR Addr 0x54016, Direction=Out + * This is a signed integer value. + * Write to read critical delay difference from cs 1 to cs 1 + * on Channel A. + */ + int8_t cdd_cha_wr_1_0; /* + * Byte offset 0x2d, CSR Addr 0x54016, Direction=Out + * This is a signed integer value. + * Write to read critical delay difference from cs 1 to cs 0 + * on Channel A. + */ + int8_t cdd_cha_wr_0_1; /* + * Byte offset 0x2e, CSR Addr 0x54017, Direction=Out + * This is a signed integer value. + * Write to read critical delay difference from cs 0 to cs 1 + * on Channel A. + */ + int8_t cdd_cha_wr_0_0; /* + * Byte offset 0x2f, CSR Addr 0x54017, Direction=Out + * This is a signed integer value. + * Write to read critical delay difference from cs 0 to cs 0 + * on Channel A. + */ + int8_t cdd_cha_ww_1_0; /* + * Byte offset 0x30, CSR Addr 0x54018, Direction=Out + * This is a signed integer value. + * Write to write critical delay difference from cs 1 to cs + * 0 on Channel A. + */ + int8_t cdd_cha_ww_0_1; /* + * Byte offset 0x31, CSR Addr 0x54018, Direction=Out + * This is a signed integer value. + * Write to write critical delay difference from cs 0 to cs + * 1 on Channel A. + */ + uint8_t mr1_a0; /* + * Byte offset 0x32, CSR Addr 0x54019, Direction=In + * Value to be programmed in DRAM Mode Register 1 + * {Channel A, Rank 0} + */ + uint8_t mr2_a0; /* + * Byte offset 0x33, CSR Addr 0x54019, Direction=In + * Value to be programmed in DRAM Mode Register 2 + * {Channel A, Rank 0} + */ + uint8_t mr3_a0; /* + * Byte offset 0x34, CSR Addr 0x5401a, Direction=In + * Value to be programmed in DRAM Mode Register 3 + * {Channel A, Rank 0} + */ + uint8_t mr4_a0; /* + * Byte offset 0x35, CSR Addr 0x5401a, Direction=In + * Value to be programmed in DRAM Mode Register 4 + * {Channel A, Rank 0} + */ + uint8_t mr11_a0; /* + * Byte offset 0x36, CSR Addr 0x5401b, Direction=In + * Value to be programmed in DRAM Mode Register 11 + * {Channel A, Rank 0} + */ + uint8_t mr12_a0; /* + * Byte offset 0x37, CSR Addr 0x5401b, Direction=In + * Value to be programmed in DRAM Mode Register 12 + * {Channel A, Rank 0} + */ + uint8_t mr13_a0; /* + * Byte offset 0x38, CSR Addr 0x5401c, Direction=In + * Value to be programmed in DRAM Mode Register 13 + * {Channel A, Rank 0} + */ + uint8_t mr14_a0; /* + * Byte offset 0x39, CSR Addr 0x5401c, Direction=In + * Value to be programmed in DRAM Mode Register 14 + * {Channel A, Rank 0} + */ + uint8_t mr16_a0; /* + * Byte offset 0x3a, CSR Addr 0x5401d, Direction=In + * Value to be programmed in DRAM Mode Register 16 + * {Channel A, Rank 0} + */ + uint8_t mr17_a0; /* + * Byte offset 0x3b, CSR Addr 0x5401d, Direction=In + * Value to be programmed in DRAM Mode Register 17 + * {Channel A, Rank 0} + */ + uint8_t mr22_a0; /* + * Byte offset 0x3c, CSR Addr 0x5401e, Direction=In + * Value to be programmed in DRAM Mode Register 22 + * {Channel A, Rank 0} + */ + uint8_t mr24_a0; /* + * Byte offset 0x3d, CSR Addr 0x5401e, Direction=In + * Value to be programmed in DRAM Mode Register 24 + * {Channel A, Rank 0} + */ + uint8_t mr1_a1; /* + * Byte offset 0x3e, CSR Addr 0x5401f, Direction=In + * Value to be programmed in DRAM Mode Register 1 + * {Channel A, Rank 1} + */ + uint8_t mr2_a1; /* + * Byte offset 0x3f, CSR Addr 0x5401f, Direction=In + * Value to be programmed in DRAM Mode Register 2 + * {Channel A, Rank 1} + */ + uint8_t mr3_a1; /* + * Byte offset 0x40, CSR Addr 0x54020, Direction=In + * Value to be programmed in DRAM Mode Register 3 + * {Channel A, Rank 1} + */ + uint8_t mr4_a1; /* + * Byte offset 0x41, CSR Addr 0x54020, Direction=In + * Value to be programmed in DRAM Mode Register 4 + * {Channel A, Rank 1} + */ + uint8_t mr11_a1; /* + * Byte offset 0x42, CSR Addr 0x54021, Direction=In + * Value to be programmed in DRAM Mode Register 11 + * {Channel A, Rank 1} + */ + uint8_t mr12_a1; /* + * Byte offset 0x43, CSR Addr 0x54021, Direction=In + * Value to be programmed in DRAM Mode Register 12 + * {Channel A, Rank 1} + */ + uint8_t mr13_a1; /* + * Byte offset 0x44, CSR Addr 0x54022, Direction=In + * Value to be programmed in DRAM Mode Register 13 + * {Channel A, Rank 1} + */ + uint8_t mr14_a1; /* + * Byte offset 0x45, CSR Addr 0x54022, Direction=In + * Value to be programmed in DRAM Mode Register 14 + * {Channel A, Rank 1} + */ + uint8_t mr16_a1; /* + * Byte offset 0x46, CSR Addr 0x54023, Direction=In + * Value to be programmed in DRAM Mode Register 16 + * {Channel A, Rank 1} + */ + uint8_t mr17_a1; /* + * Byte offset 0x47, CSR Addr 0x54023, Direction=In + * Value to be programmed in DRAM Mode Register 17 + * {Channel A, Rank 1} + */ + uint8_t mr22_a1; /* + * Byte offset 0x48, CSR Addr 0x54024, Direction=In + * Value to be programmed in DRAM Mode Register 22 + * {Channel A, Rank 1} + */ + uint8_t mr24_a1; /* + * Byte offset 0x49, CSR Addr 0x54024, Direction=In + * Value to be programmed in DRAM Mode Register 24 + * {Channel A, Rank 1} + */ + uint8_t caterminatingrankcha; /* Byte offset 0x4a, CSR Addr 0x54025, Direction=In + * Terminating Rank for CA bus on Channel A + * 0x0 = Rank 0 is terminating rank + * 0x1 = Rank 1 is terminating rank + */ + uint8_t reserved4b; /* Byte offset 0x4b, CSR Addr 0x54025, Direction=N/A */ + uint8_t reserved4c; /* Byte offset 0x4c, CSR Addr 0x54026, Direction=N/A */ + uint8_t reserved4d; /* Byte offset 0x4d, CSR Addr 0x54026, Direction=N/A */ + uint8_t reserved4e; /* Byte offset 0x4e, CSR Addr 0x54027, Direction=N/A */ + uint8_t reserved4f; /* Byte offset 0x4f, CSR Addr 0x54027, Direction=N/A */ + uint8_t reserved50; /* Byte offset 0x50, CSR Addr 0x54028, Direction=N/A */ + uint8_t reserved51; /* Byte offset 0x51, CSR Addr 0x54028, Direction=N/A */ + uint8_t reserved52; /* Byte offset 0x52, CSR Addr 0x54029, Direction=N/A */ + uint8_t reserved53; /* Byte offset 0x53, CSR Addr 0x54029, Direction=N/A */ + uint8_t reserved54; /* Byte offset 0x54, CSR Addr 0x5402a, Direction=N/A */ + uint8_t reserved55; /* Byte offset 0x55, CSR Addr 0x5402a, Direction=N/A */ + uint8_t reserved56; /* Byte offset 0x56, CSR Addr 0x5402b, Direction=N/A */ + uint8_t enableddqschb; /* + * Byte offset 0x57, CSR Addr 0x5402b, Direction=In + * Total number of DQ bits enabled in PHY Channel B + */ + uint8_t cspresentchb; /* + * Byte offset 0x58, CSR Addr 0x5402c, Direction=In + * Indicates presence of DRAM at each chip select for PHY + * channel B. + * 0x0 = No chip selects are populated with DRAM + * 0x1 = CS0 is populated with DRAM + * 0x3 = CS0 and CS1 are populated with DRAM + * + * All other encodings are illegal + */ + int8_t cdd_chb_rr_1_0; /* + * Byte offset 0x59, CSR Addr 0x5402c, Direction=Out + * This is a signed integer value. + * Read to read critical delay difference from cs 1 to cs 0 + * on Channel B. + */ + int8_t cdd_chb_rr_0_1; /* + * Byte offset 0x5a, CSR Addr 0x5402d, Direction=Out + * This is a signed integer value. + * Read to read critical delay difference from cs 0 to cs 1 + * on Channel B. + */ + int8_t cdd_chb_rw_1_1; /* + * Byte offset 0x5b, CSR Addr 0x5402d, Direction=Out + * This is a signed integer value. + * Read to write critical delay difference from cs 1 to cs 1 + * on Channel B. + */ + int8_t cdd_chb_rw_1_0; /* + * Byte offset 0x5c, CSR Addr 0x5402e, Direction=Out + * This is a signed integer value. + * Read to write critical delay difference from cs 1 to cs 0 + * on Channel B. + */ + int8_t cdd_chb_rw_0_1; /* + * Byte offset 0x5d, CSR Addr 0x5402e, Direction=Out + * This is a signed integer value. + * Read to write critical delay difference from cs 0 to cs 1 + * on Channel B. + */ + int8_t cdd_chb_rw_0_0; /* + * Byte offset 0x5e, CSR Addr 0x5402f, Direction=Out + * This is a signed integer value. + * Read to write critical delay difference from cs01 to cs 0 + * on Channel B. + */ + int8_t cdd_chb_wr_1_1; /* + * Byte offset 0x5f, CSR Addr 0x5402f, Direction=Out + * This is a signed integer value. + * Write to read critical delay difference from cs 1 to cs 1 + * on Channel B. + */ + int8_t cdd_chb_wr_1_0; /* + * Byte offset 0x60, CSR Addr 0x54030, Direction=Out + * This is a signed integer value. + * Write to read critical delay difference from cs 1 to cs 0 + * on Channel B. + */ + int8_t cdd_chb_wr_0_1; /* + * Byte offset 0x61, CSR Addr 0x54030, Direction=Out + * This is a signed integer value. + * Write to read critical delay difference from cs 0 to cs 1 + * on Channel B. + */ + int8_t cdd_chb_wr_0_0; /* + * Byte offset 0x62, CSR Addr 0x54031, Direction=Out + * This is a signed integer value. + * Write to read critical delay difference from cs 0 to cs 0 + * on Channel B. + */ + int8_t cdd_chb_ww_1_0; /* + * Byte offset 0x63, CSR Addr 0x54031, Direction=Out + * This is a signed integer value. + * Write to write critical delay difference from cs 1 to cs + * 0 on Channel B. + */ + int8_t cdd_chb_ww_0_1; /* + * Byte offset 0x64, CSR Addr 0x54032, Direction=Out + * This is a signed integer value. + * Write to write critical delay difference from cs 0 to cs + * 1 on Channel B. + */ + uint8_t mr1_b0; /* + * Byte offset 0x65, CSR Addr 0x54032, Direction=In + * Value to be programmed in DRAM Mode Register 1 + * {Channel B, Rank 0} + */ + uint8_t mr2_b0; /* + * Byte offset 0x66, CSR Addr 0x54033, Direction=In + * Value to be programmed in DRAM Mode Register 2 + * {Channel B, Rank 0} + */ + uint8_t mr3_b0; /* + * Byte offset 0x67, CSR Addr 0x54033, Direction=In + * Value to be programmed in DRAM Mode Register 3 + * {Channel B, Rank 0} + */ + uint8_t mr4_b0; /* + * Byte offset 0x68, CSR Addr 0x54034, Direction=In + * Value to be programmed in DRAM Mode Register 4 + * {Channel B, Rank 0} + */ + uint8_t mr11_b0; /* + * Byte offset 0x69, CSR Addr 0x54034, Direction=In + * Value to be programmed in DRAM Mode Register 11 + * {Channel B, Rank 0} + */ + uint8_t mr12_b0; /* + * Byte offset 0x6a, CSR Addr 0x54035, Direction=In + * Value to be programmed in DRAM Mode Register 12 + * {Channel B, Rank 0} + */ + uint8_t mr13_b0; /* + * Byte offset 0x6b, CSR Addr 0x54035, Direction=In + * Value to be programmed in DRAM Mode Register 13 + * {Channel B, Rank 0} + */ + uint8_t mr14_b0; /* + * Byte offset 0x6c, CSR Addr 0x54036, Direction=In + * Value to be programmed in DRAM Mode Register 14 + * {Channel B, Rank 0} + */ + uint8_t mr16_b0; /* + * Byte offset 0x6d, CSR Addr 0x54036, Direction=In + * Value to be programmed in DRAM Mode Register 16 + * {Channel B, Rank 0} + */ + uint8_t mr17_b0; /* + * Byte offset 0x6e, CSR Addr 0x54037, Direction=In + * Value to be programmed in DRAM Mode Register 17 + * {Channel B, Rank 0} + */ + uint8_t mr22_b0; /* + * Byte offset 0x6f, CSR Addr 0x54037, Direction=In + * Value to be programmed in DRAM Mode Register 22 + * {Channel B, Rank 0} + */ + uint8_t mr24_b0; /* + * Byte offset 0x70, CSR Addr 0x54038, Direction=In + * Value to be programmed in DRAM Mode Register 24 + * {Channel B, Rank 0} + */ + uint8_t mr1_b1; /* + * Byte offset 0x71, CSR Addr 0x54038, Direction=In + * Value to be programmed in DRAM Mode Register 1 + * {Channel B, Rank 1} + */ + uint8_t mr2_b1; /* + * Byte offset 0x72, CSR Addr 0x54039, Direction=In + * Value to be programmed in DRAM Mode Register 2 + * {Channel B, Rank 1} + */ + uint8_t mr3_b1; /* + * Byte offset 0x73, CSR Addr 0x54039, Direction=In + * Value to be programmed in DRAM Mode Register 3 + * {Channel B, Rank 1} + */ + uint8_t mr4_b1; /* + * Byte offset 0x74, CSR Addr 0x5403a, Direction=In + * Value to be programmed in DRAM Mode Register 4 + * {Channel B, Rank 1} + */ + uint8_t mr11_b1; /* + * Byte offset 0x75, CSR Addr 0x5403a, Direction=In + * Value to be programmed in DRAM Mode Register 11 + * {Channel B, Rank 1} + */ + uint8_t mr12_b1; /* + * Byte offset 0x76, CSR Addr 0x5403b, Direction=In + * Value to be programmed in DRAM Mode Register 12 + * {Channel B, Rank 1} + */ + uint8_t mr13_b1; /* + * Byte offset 0x77, CSR Addr 0x5403b, Direction=In + * Value to be programmed in DRAM Mode Register 13 + * {Channel B, Rank 1} + */ + uint8_t mr14_b1; /* + * Byte offset 0x78, CSR Addr 0x5403c, Direction=In + * Value to be programmed in DRAM Mode Register 14 + * {Channel B, Rank 1} + */ + uint8_t mr16_b1; /* + * Byte offset 0x79, CSR Addr 0x5403c, Direction=In + * Value to be programmed in DRAM Mode Register 16 + * {Channel B, Rank 1} + */ + uint8_t mr17_b1; /* + * Byte offset 0x7a, CSR Addr 0x5403d, Direction=In + * Value to be programmed in DRAM Mode Register 17 + * {Channel B, Rank 1} + */ + uint8_t mr22_b1; /* + * Byte offset 0x7b, CSR Addr 0x5403d, Direction=In + * Value to be programmed in DRAM Mode Register 22 + * {Channel B, Rank 1} + */ + uint8_t mr24_b1; /* + * Byte offset 0x7c, CSR Addr 0x5403e, Direction=In + * Value to be programmed in DRAM Mode Register 24 + * {Channel B, Rank 1} + */ + uint8_t caterminatingrankchb; /* Byte offset 0x7d, CSR Addr 0x5403e, Direction=In + * Terminating Rank for CA bus on Channel B + * 0x0 = Rank 0 is terminating rank + * 0x1 = Rank 1 is terminating rank + */ + uint8_t reserved7e; /* Byte offset 0x7e, CSR Addr 0x5403f, Direction=N/A */ + uint8_t reserved7f; /* Byte offset 0x7f, CSR Addr 0x5403f, Direction=N/A */ + uint8_t reserved80; /* Byte offset 0x80, CSR Addr 0x54040, Direction=N/A */ + uint8_t reserved81; /* Byte offset 0x81, CSR Addr 0x54040, Direction=N/A */ + uint8_t reserved82; /* Byte offset 0x82, CSR Addr 0x54041, Direction=N/A */ + uint8_t reserved83; /* Byte offset 0x83, CSR Addr 0x54041, Direction=N/A */ + uint8_t reserved84; /* Byte offset 0x84, CSR Addr 0x54042, Direction=N/A */ + uint8_t reserved85; /* Byte offset 0x85, CSR Addr 0x54042, Direction=N/A */ + uint8_t reserved86; /* Byte offset 0x86, CSR Addr 0x54043, Direction=N/A */ + uint8_t reserved87; /* Byte offset 0x87, CSR Addr 0x54043, Direction=N/A */ + uint8_t reserved88; /* Byte offset 0x88, CSR Addr 0x54044, Direction=N/A */ + uint8_t reserved89; /* Byte offset 0x89, CSR Addr 0x54044, Direction=N/A */ +} __packed __aligned(2); + +#endif /* MNPMUSRAMMSGBLOCK_LPDDR4_H */ diff --git a/drivers/st/ddr/phy/phyinit/include/ddrphy_csr_all_cdefines.h b/drivers/st/ddr/phy/phyinit/include/ddrphy_csr_all_cdefines.h new file mode 100644 index 000000000..99a8c4cc7 --- /dev/null +++ b/drivers/st/ddr/phy/phyinit/include/ddrphy_csr_all_cdefines.h @@ -0,0 +1,6944 @@ +/* + * Copyright (C) 2021-2024, STMicroelectronics - All Rights Reserved + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef DDRPHY_PHYINIT_CSR_ALL_DEFINES_H +#define DDRPHY_PHYINIT_CSR_ALL_DEFINES_H + +/* ANIBx register offsets */ +#define CSR_MTESTMUXSEL_ADDR 0x1AU +#define CSR_AFORCEDRVCONT_ADDR 0x27U +#define CSR_AFORCETRICONT_ADDR 0x28U +#define CSR_ATXIMPEDANCE_ADDR 0x43U +#define CSR_ATESTPRBSERR_ADDR 0x53U +#define CSR_ATXSLEWRATE_ADDR 0x55U +#define CSR_ATESTPRBSERRCNT_ADDR 0x56U +#define CSR_ATXDLY_ADDR 0x80U + +/* DBYTEx register offsets */ +#define CSR_DBYTEMISCMODE_ADDR 0x0U +#define CSR_TSMBYTE0_ADDR 0x1U +#define CSR_TRAININGPARAM_ADDR 0x2U +#define CSR_USEDQSENREPLICA_ADDR 0x3U +#define CSR_RXTRAINPATTERNENABLE_ADDR 0x10U +#define CSR_TSMBYTE1_ADDR 0x11U +#define CSR_TSMBYTE2_ADDR 0x12U +#define CSR_TSMBYTE3_ADDR 0x13U +#define CSR_TSMBYTE4_ADDR 0x14U +#define CSR_TESTMODECONFIG_ADDR 0x17U +#define CSR_TSMBYTE5_ADDR 0x18U +/* MTESTMUXSEL already defined in ANIBx section */ +#define CSR_DTSMTRAINMODECTRL_ADDR 0x1FU +#define CSR_DFIMRL_ADDR 0x20U +#define CSR_ASYNCDBYTEMODE_ADDR 0x24U +#define CSR_ASYNCDBYTETXEN_ADDR 0x26U +#define CSR_ASYNCDBYTETXDATA_ADDR 0x28U +#define CSR_ASYNCDBYTERXDATA_ADDR 0x2AU +#define CSR_VREFDAC1_ADDR 0x30U +#define CSR_TRAININGCNTR_ADDR 0x32U +#define CSR_VREFDAC0_ADDR 0x40U +#define CSR_TXIMPEDANCECTRL0_ADDR 0x41U +#define CSR_DQDQSRCVCNTRL_ADDR 0x43U +#define CSR_TXEQUALIZATIONMODE_ADDR 0x48U +#define CSR_TXIMPEDANCECTRL1_ADDR 0x49U +#define CSR_DQDQSRCVCNTRL1_ADDR 0x4AU +#define CSR_TXIMPEDANCECTRL2_ADDR 0x4BU +#define CSR_DQDQSRCVCNTRL2_ADDR 0x4CU +#define CSR_TXODTDRVSTREN_ADDR 0x4DU +#define CSR_RXFIFOCHECKSTATUS_ADDR 0x56U +#define CSR_RXFIFOCHECKERRVALUES_ADDR 0x57U +#define CSR_RXFIFOINFO_ADDR 0x58U +#define CSR_RXFIFOVISIBILITY_ADDR 0x59U +#define CSR_RXFIFOCONTENTSDQ3210_ADDR 0x5AU +#define CSR_RXFIFOCONTENTSDQ7654_ADDR 0x5BU +#define CSR_RXFIFOCONTENTSDBI_ADDR 0x5CU +#define CSR_TXSLEWRATE_ADDR 0x5FU +#define CSR_TRAININGINCDECDTSMEN_ADDR 0x62U +#define CSR_RXPBDLYTG0_ADDR 0x68U +#define CSR_RXPBDLYTG1_ADDR 0x69U +#define CSR_RXPBDLYTG2_ADDR 0x6AU +#define CSR_RXPBDLYTG3_ADDR 0x6BU +#define CSR_RXENDLYTG0_ADDR 0x80U +#define CSR_RXENDLYTG1_ADDR 0x81U +#define CSR_RXENDLYTG2_ADDR 0x82U +#define CSR_RXENDLYTG3_ADDR 0x83U +#define CSR_RXCLKDLYTG0_ADDR 0x8CU +#define CSR_RXCLKDLYTG1_ADDR 0x8DU +#define CSR_RXCLKDLYTG2_ADDR 0x8EU +#define CSR_RXCLKDLYTG3_ADDR 0x8FU +#define CSR_RXCLKCDLYTG0_ADDR 0x90U +#define CSR_RXCLKCDLYTG1_ADDR 0x91U +#define CSR_RXCLKCDLYTG2_ADDR 0x92U +#define CSR_RXCLKCDLYTG3_ADDR 0x93U +#define CSR_DQ0LNSEL_ADDR 0xA0U +#define CSR_DQ1LNSEL_ADDR 0xA1U +#define CSR_DQ2LNSEL_ADDR 0xA2U +#define CSR_DQ3LNSEL_ADDR 0xA3U +#define CSR_DQ4LNSEL_ADDR 0xA4U +#define CSR_DQ5LNSEL_ADDR 0xA5U +#define CSR_DQ6LNSEL_ADDR 0xA6U +#define CSR_DQ7LNSEL_ADDR 0xA7U +#define CSR_PPTCTLSTATIC_ADDR 0xAAU +#define CSR_PPTCTLDYN_ADDR 0xABU +#define CSR_PPTINFO_ADDR 0xACU +#define CSR_PPTRXENEVNT_ADDR 0xADU +#define CSR_PPTDQSCNTINVTRNTG0_ADDR 0xAEU +#define CSR_PPTDQSCNTINVTRNTG1_ADDR 0xAFU +#define CSR_DTSMBLANKINGCTRL_ADDR 0xB1U +#define CSR_TSM0_ADDR 0xB2U +#define CSR_TSM1_ADDR 0xB3U +#define CSR_TSM2_ADDR 0xB4U +#define CSR_TSM3_ADDR 0xB5U +#define CSR_TXCHKDATASELECTS_ADDR 0xB6U +#define CSR_DTSMUPTHLDXINGIND_ADDR 0xB7U +#define CSR_DTSMLOTHLDXINGIND_ADDR 0xB8U +#define CSR_DBYTEALLDTSMCTRL0_ADDR 0xB9U +#define CSR_DBYTEALLDTSMCTRL1_ADDR 0xBAU +#define CSR_DBYTEALLDTSMCTRL2_ADDR 0xBBU +#define CSR_TXDQDLYTG0_ADDR 0xC0U +#define CSR_TXDQDLYTG1_ADDR 0xC1U +#define CSR_TXDQDLYTG2_ADDR 0xC2U +#define CSR_TXDQDLYTG3_ADDR 0xC3U +#define CSR_TXDQSDLYTG0_ADDR 0xD0U +#define CSR_TXDQSDLYTG1_ADDR 0xD1U +#define CSR_TXDQSDLYTG2_ADDR 0xD2U +#define CSR_TXDQSDLYTG3_ADDR 0xD3U +#define CSR_DXLCDLSTATUS_ADDR 0xE4U + +/* MASTER0 register offsets */ +#define CSR_RXFIFOINIT_ADDR 0x0U +#define CSR_FORCECLKDISABLE_ADDR 0x1U +#define CSR_CLOCKINGCTRL_ADDR 0x2U +#define CSR_FORCEINTERNALUPDATE_ADDR 0x3U +#define CSR_PHYCONFIG_ADDR 0x4U +#define CSR_PGCR_ADDR 0x5U +#define CSR_TESTBUMPCNTRL1_ADDR 0x7U +#define CSR_CALUCLKINFO_ADDR 0x8U +#define CSR_TESTBUMPCNTRL_ADDR 0xAU +#define CSR_SEQ0BDLY0_ADDR 0xBU +#define CSR_SEQ0BDLY1_ADDR 0xCU +#define CSR_SEQ0BDLY2_ADDR 0xDU +#define CSR_SEQ0BDLY3_ADDR 0xEU +#define CSR_PHYALERTSTATUS_ADDR 0xFU +#define CSR_PPTTRAINSETUP_ADDR 0x10U +#define CSR_PPTTRAINSETUP2_ADDR 0x11U +#define CSR_ATESTMODE_ADDR 0x12U +#define CSR_TXCALBINP_ADDR 0x14U +#define CSR_TXCALBINN_ADDR 0x15U +#define CSR_TXCALPOVR_ADDR 0x16U +#define CSR_TXCALNOVR_ADDR 0x17U +#define CSR_DFIMODE_ADDR 0x18U +#define CSR_TRISTATEMODECA_ADDR 0x19U +/* MTESTMUXSEL already defined in ANIBx section */ +#define CSR_MTESTPGMINFO_ADDR 0x1BU +#define CSR_DYNPWRDNUP_ADDR 0x1CU +#define CSR_PMIENABLE_ADDR 0x1DU +#define CSR_PHYTID_ADDR 0x1EU +#define CSR_HWTMRL_ADDR 0x20U +#define CSR_DFIPHYUPD_ADDR 0x21U +#define CSR_PDAMRSWRITEMODE_ADDR 0x22U +#define CSR_DFIGEARDOWNCTL_ADDR 0x23U +#define CSR_DQSPREAMBLECONTROL_ADDR 0x24U +#define CSR_MASTERX4CONFIG_ADDR 0x25U +#define CSR_WRLEVBITS_ADDR 0x26U +#define CSR_ENABLECSMULTICAST_ADDR 0x27U +#define CSR_HWTLPCSMULTICAST_ADDR 0x28U +#define CSR_ACX4ANIBDIS_ADDR 0x2CU +#define CSR_DMIPINPRESENT_ADDR 0x2DU +#define CSR_ARDPTRINITVAL_ADDR 0x2EU +#define CSR_DB0LCDLCALPHDETOUT_ADDR 0x30U +#define CSR_DB1LCDLCALPHDETOUT_ADDR 0x31U +#define CSR_DB2LCDLCALPHDETOUT_ADDR 0x32U +#define CSR_DB3LCDLCALPHDETOUT_ADDR 0x33U +#define CSR_DB4LCDLCALPHDETOUT_ADDR 0x34U +#define CSR_DB5LCDLCALPHDETOUT_ADDR 0x35U +#define CSR_DB6LCDLCALPHDETOUT_ADDR 0x36U +#define CSR_DB7LCDLCALPHDETOUT_ADDR 0x37U +#define CSR_DB8LCDLCALPHDETOUT_ADDR 0x38U +#define CSR_DB9LCDLCALPHDETOUT_ADDR 0x39U +#define CSR_DBYTEDLLMODECNTRL_ADDR 0x3AU +#define CSR_DBYTERXENTRAIN_ADDR 0x3BU +#define CSR_ANLCDLCALPHDETOUT_ADDR 0x3FU +#define CSR_CALOFFSETS_ADDR 0x45U +#define CSR_SARINITVALS_ADDR 0x47U +#define CSR_CALPEXTOVR_ADDR 0x49U +#define CSR_CALCMPR5OVR_ADDR 0x4AU +#define CSR_CALNINTOVR_ADDR 0x4BU +#define CSR_CALDRVSTR0_ADDR 0x50U +#define CSR_PROCODTCTL_ADDR 0x55U +#define CSR_PROCODTTIMECTL_ADDR 0x56U +#define CSR_MEMALERTCONTROL_ADDR 0x5BU +#define CSR_MEMALERTCONTROL2_ADDR 0x5CU +#define CSR_MEMRESETL_ADDR 0x60U +#define CSR_PUBMODE_ADDR 0x6EU +#define CSR_MISCPHYSTATUS_ADDR 0x6FU +#define CSR_CORELOOPBACKSEL_ADDR 0x70U +#define CSR_DLLTRAINPARAM_ADDR 0x71U +#define CSR_HWTLPCSENA_ADDR 0x72U +#define CSR_HWTLPCSENB_ADDR 0x73U +#define CSR_HWTLPCSENBYPASS_ADDR 0x74U +#define CSR_DFICAMODE_ADDR 0x75U +#define CSR_HWTCACTL_ADDR 0x76U +#define CSR_HWTCAMODE_ADDR 0x77U +#define CSR_DLLCONTROL_ADDR 0x78U +#define CSR_PULSEDLLUPDATEPHASE_ADDR 0x79U +#define CSR_HWTCONTROLOVR0_ADDR 0x7AU +#define CSR_HWTCONTROLOVR1_ADDR 0x7BU +#define CSR_DLLGAINCTL_ADDR 0x7CU +#define CSR_DLLLOCKPARAM_ADDR 0x7DU +#define CSR_HWTCONTROLVAL0_ADDR 0x7EU +#define CSR_HWTCONTROLVAL1_ADDR 0x7FU +#define CSR_ACSMGLBLSTART_ADDR 0x81U +#define CSR_ACSMGLBLSGLSTPCTRL_ADDR 0x82U +#define CSR_LCDLCALPHASE_ADDR 0x84U +#define CSR_LCDLCALCTRL_ADDR 0x85U +#define CSR_CALRATE_ADDR 0x88U +#define CSR_CALZAP_ADDR 0x89U +#define CSR_PSTATE_ADDR 0x8BU +#define CSR_CALPREDRIVEROVERRIDE_ADDR 0x8CU +#define CSR_PLLOUTGATECONTROL_ADDR 0x8DU +#define CSR_UCMEMRESETCONTROL_ADDR 0x8FU +#define CSR_PORCONTROL_ADDR 0x90U +#define CSR_CALBUSY_ADDR 0x97U +#define CSR_CALMISC2_ADDR 0x98U +#define CSR_CALMISC_ADDR 0x9AU +#define CSR_CALVREFS_ADDR 0x9BU +#define CSR_CALCMPR5_ADDR 0x9CU +#define CSR_CALNINT_ADDR 0x9DU +#define CSR_CALPEXT_ADDR 0x9EU +#define CSR_CALCMPINVERT_ADDR 0xA8U +#define CSR_CALCMPANACNTRL_ADDR 0xAEU +#define CSR_DFIRDDATACSDESTMAP_ADDR 0xB0U +#define CSR_VREFINGLOBAL_ADDR 0xB2U +#define CSR_DFIWRDATACSDESTMAP_ADDR 0xB4U +#define CSR_MASUPDGOODCTR_ADDR 0xB5U +#define CSR_PHYUPD0GOODCTR_ADDR 0xB6U +#define CSR_PHYUPD1GOODCTR_ADDR 0xB7U +#define CSR_CTLUPD0GOODCTR_ADDR 0xB8U +#define CSR_CTLUPD1GOODCTR_ADDR 0xB9U +#define CSR_MASUPDFAILCTR_ADDR 0xBAU +#define CSR_PHYUPD0FAILCTR_ADDR 0xBBU +#define CSR_PHYUPD1FAILCTR_ADDR 0xBCU +#define CSR_PHYPERFCTRENABLE_ADDR 0xBDU +#define CSR_DFIWRRDDATACSCONFIG_ADDR 0xBEU +#define CSR_PLLPWRDN_ADDR 0xC3U +#define CSR_PLLRESET_ADDR 0xC4U +#define CSR_PLLCTRL2_ADDR 0xC5U +#define CSR_PLLCTRL0_ADDR 0xC6U +#define CSR_PLLCTRL1_ADDR 0xC7U +#define CSR_PLLTST_ADDR 0xC8U +#define CSR_PLLLOCKSTATUS_ADDR 0xC9U +#define CSR_PLLTESTMODE_ADDR 0xCAU +#define CSR_PLLCTRL3_ADDR 0xCBU +#define CSR_PLLCTRL4_ADDR 0xCCU +#define CSR_PLLENDOFCAL_ADDR 0xCDU +#define CSR_PLLSTANDBYEFF_ADDR 0xCEU +#define CSR_PLLDACVALOUT_ADDR 0xCFU +#define CSR_DLYTESTSEQ_ADDR 0xD0U +#define CSR_DLYTESTRINGSELDB_ADDR 0xD1U +#define CSR_DLYTESTRINGSELAC_ADDR 0xD2U +#define CSR_DLYTESTCNTDFICLKIV_ADDR 0xD3U +#define CSR_DLYTESTCNTDFICLK_ADDR 0xD4U +#define CSR_DLYTESTCNTRINGOSCDB0_ADDR 0xD5U +#define CSR_DLYTESTCNTRINGOSCDB1_ADDR 0xD6U +#define CSR_DLYTESTCNTRINGOSCDB2_ADDR 0xD7U +#define CSR_DLYTESTCNTRINGOSCDB3_ADDR 0xD8U +#define CSR_DLYTESTCNTRINGOSCDB4_ADDR 0xD9U +#define CSR_DLYTESTCNTRINGOSCDB5_ADDR 0xDAU +#define CSR_DLYTESTCNTRINGOSCDB6_ADDR 0xDBU +#define CSR_DLYTESTCNTRINGOSCDB7_ADDR 0xDCU +#define CSR_DLYTESTCNTRINGOSCDB8_ADDR 0xDDU +#define CSR_DLYTESTCNTRINGOSCDB9_ADDR 0xDEU +#define CSR_DLYTESTCNTRINGOSCAC_ADDR 0xDFU +#define CSR_MSTLCDLDBGCNTL_ADDR 0xE0U +#define CSR_MSTLCDL0DBGRES_ADDR 0xE1U +#define CSR_MSTLCDL1DBGRES_ADDR 0xE2U +#define CSR_LCDLDBGCNTL_ADDR 0xE3U +#define CSR_ACLCDLSTATUS_ADDR 0xE4U +#define CSR_CUSTPHYREV_ADDR 0xEDU +#define CSR_PHYREV_ADDR 0xEEU +#define CSR_LP3EXITSEQ0BSTARTVECTOR_ADDR 0xEFU +#define CSR_DFIFREQXLAT0_ADDR 0xF0U +#define CSR_DFIFREQXLAT1_ADDR 0xF1U +#define CSR_DFIFREQXLAT2_ADDR 0xF2U +#define CSR_DFIFREQXLAT3_ADDR 0xF3U +#define CSR_DFIFREQXLAT4_ADDR 0xF4U +#define CSR_DFIFREQXLAT5_ADDR 0xF5U +#define CSR_DFIFREQXLAT6_ADDR 0xF6U +#define CSR_DFIFREQXLAT7_ADDR 0xF7U +#define CSR_TXRDPTRINIT_ADDR 0xF8U +#define CSR_DFIINITCOMPLETE_ADDR 0xF9U +#define CSR_DFIFREQRATIO_ADDR 0xFAU +#define CSR_RXFIFOCHECKS_ADDR 0xFBU +#define CSR_MTESTDTOCTRL_ADDR 0xFFU +#define CSR_MAPCAA0TODFI_ADDR 0x100U +#define CSR_MAPCAA1TODFI_ADDR 0x101U +#define CSR_MAPCAA2TODFI_ADDR 0x102U +#define CSR_MAPCAA3TODFI_ADDR 0x103U +#define CSR_MAPCAA4TODFI_ADDR 0x104U +#define CSR_MAPCAA5TODFI_ADDR 0x105U +#define CSR_MAPCAA6TODFI_ADDR 0x106U +#define CSR_MAPCAA7TODFI_ADDR 0x107U +#define CSR_MAPCAA8TODFI_ADDR 0x108U +#define CSR_MAPCAA9TODFI_ADDR 0x109U +#define CSR_MAPCAB0TODFI_ADDR 0x110U +#define CSR_MAPCAB1TODFI_ADDR 0x111U +#define CSR_MAPCAB2TODFI_ADDR 0x112U +#define CSR_MAPCAB3TODFI_ADDR 0x113U +#define CSR_MAPCAB4TODFI_ADDR 0x114U +#define CSR_MAPCAB5TODFI_ADDR 0x115U +#define CSR_MAPCAB6TODFI_ADDR 0x116U +#define CSR_MAPCAB7TODFI_ADDR 0x117U +#define CSR_MAPCAB8TODFI_ADDR 0x118U +#define CSR_MAPCAB9TODFI_ADDR 0x119U +#define CSR_PHYINTERRUPTENABLE_ADDR 0x11BU +#define CSR_PHYINTERRUPTFWCONTROL_ADDR 0x11CU +#define CSR_PHYINTERRUPTMASK_ADDR 0x11DU +#define CSR_PHYINTERRUPTCLEAR_ADDR 0x11EU +#define CSR_PHYINTERRUPTSTATUS_ADDR 0x11FU +#define CSR_HWTSWIZZLEHWTADDRESS0_ADDR 0x120U +#define CSR_HWTSWIZZLEHWTADDRESS1_ADDR 0x121U +#define CSR_HWTSWIZZLEHWTADDRESS2_ADDR 0x122U +#define CSR_HWTSWIZZLEHWTADDRESS3_ADDR 0x123U +#define CSR_HWTSWIZZLEHWTADDRESS4_ADDR 0x124U +#define CSR_HWTSWIZZLEHWTADDRESS5_ADDR 0x125U +#define CSR_HWTSWIZZLEHWTADDRESS6_ADDR 0x126U +#define CSR_HWTSWIZZLEHWTADDRESS7_ADDR 0x127U +#define CSR_HWTSWIZZLEHWTADDRESS8_ADDR 0x128U +#define CSR_HWTSWIZZLEHWTADDRESS9_ADDR 0x129U +#define CSR_HWTSWIZZLEHWTADDRESS10_ADDR 0x12AU +#define CSR_HWTSWIZZLEHWTADDRESS11_ADDR 0x12BU +#define CSR_HWTSWIZZLEHWTADDRESS12_ADDR 0x12CU +#define CSR_HWTSWIZZLEHWTADDRESS13_ADDR 0x12DU +#define CSR_HWTSWIZZLEHWTADDRESS14_ADDR 0x12EU +#define CSR_HWTSWIZZLEHWTADDRESS15_ADDR 0x12FU +#define CSR_HWTSWIZZLEHWTADDRESS17_ADDR 0x130U +#define CSR_HWTSWIZZLEHWTACTN_ADDR 0x131U +#define CSR_HWTSWIZZLEHWTBANK0_ADDR 0x132U +#define CSR_HWTSWIZZLEHWTBANK1_ADDR 0x133U +#define CSR_HWTSWIZZLEHWTBANK2_ADDR 0x134U +#define CSR_HWTSWIZZLEHWTBG0_ADDR 0x135U +#define CSR_HWTSWIZZLEHWTBG1_ADDR 0x136U +#define CSR_HWTSWIZZLEHWTCASN_ADDR 0x137U +#define CSR_HWTSWIZZLEHWTRASN_ADDR 0x138U +#define CSR_HWTSWIZZLEHWTWEN_ADDR 0x139U +#define CSR_HWTSWIZZLEHWTPARITYIN_ADDR 0x13AU +#define CSR_DFIHANDSHAKEDELAYS0_ADDR 0x13CU +#define CSR_DFIHANDSHAKEDELAYS1_ADDR 0x13DU +#define CSR_REMOTEIMPCAL_ADDR 0x13EU +#define CSR_ACLOOPBACKCTL_ADDR 0x13FU + +/* ACSM0 register offsets */ +#define CSR_ACSMSEQ0X0_ADDR 0x0U +#define CSR_ACSMSEQ0X1_ADDR 0x1U +#define CSR_ACSMSEQ0X2_ADDR 0x2U +#define CSR_ACSMSEQ0X3_ADDR 0x3U +#define CSR_ACSMSEQ0X4_ADDR 0x4U +#define CSR_ACSMSEQ0X5_ADDR 0x5U +#define CSR_ACSMSEQ0X6_ADDR 0x6U +#define CSR_ACSMSEQ0X7_ADDR 0x7U +#define CSR_ACSMSEQ0X8_ADDR 0x8U +#define CSR_ACSMSEQ0X9_ADDR 0x9U +#define CSR_ACSMSEQ0X10_ADDR 0xAU +#define CSR_ACSMSEQ0X11_ADDR 0xBU +#define CSR_ACSMSEQ0X12_ADDR 0xCU +#define CSR_ACSMSEQ0X13_ADDR 0xDU +#define CSR_ACSMSEQ0X14_ADDR 0xEU +#define CSR_ACSMSEQ0X15_ADDR 0xFU +#define CSR_ACSMSEQ0X16_ADDR 0x10U +#define CSR_ACSMSEQ0X17_ADDR 0x11U +#define CSR_ACSMSEQ0X18_ADDR 0x12U +#define CSR_ACSMSEQ0X19_ADDR 0x13U +#define CSR_ACSMSEQ0X20_ADDR 0x14U +#define CSR_ACSMSEQ0X21_ADDR 0x15U +#define CSR_ACSMSEQ0X22_ADDR 0x16U +#define CSR_ACSMSEQ0X23_ADDR 0x17U +#define CSR_ACSMSEQ0X24_ADDR 0x18U +#define CSR_ACSMSEQ0X25_ADDR 0x19U +#define CSR_ACSMSEQ0X26_ADDR 0x1AU +#define CSR_ACSMSEQ0X27_ADDR 0x1BU +#define CSR_ACSMSEQ0X28_ADDR 0x1CU +#define CSR_ACSMSEQ0X29_ADDR 0x1DU +#define CSR_ACSMSEQ0X30_ADDR 0x1EU +#define CSR_ACSMSEQ0X31_ADDR 0x1FU +#define CSR_ACSMSEQ1X0_ADDR 0x20U +#define CSR_ACSMSEQ1X1_ADDR 0x21U +#define CSR_ACSMSEQ1X2_ADDR 0x22U +#define CSR_ACSMSEQ1X3_ADDR 0x23U +#define CSR_ACSMSEQ1X4_ADDR 0x24U +#define CSR_ACSMSEQ1X5_ADDR 0x25U +#define CSR_ACSMSEQ1X6_ADDR 0x26U +#define CSR_ACSMSEQ1X7_ADDR 0x27U +#define CSR_ACSMSEQ1X8_ADDR 0x28U +#define CSR_ACSMSEQ1X9_ADDR 0x29U +#define CSR_ACSMSEQ1X10_ADDR 0x2AU +#define CSR_ACSMSEQ1X11_ADDR 0x2BU +#define CSR_ACSMSEQ1X12_ADDR 0x2CU +#define CSR_ACSMSEQ1X13_ADDR 0x2DU +#define CSR_ACSMSEQ1X14_ADDR 0x2EU +#define CSR_ACSMSEQ1X15_ADDR 0x2FU +#define CSR_ACSMSEQ1X16_ADDR 0x30U +#define CSR_ACSMSEQ1X17_ADDR 0x31U +#define CSR_ACSMSEQ1X18_ADDR 0x32U +#define CSR_ACSMSEQ1X19_ADDR 0x33U +#define CSR_ACSMSEQ1X20_ADDR 0x34U +#define CSR_ACSMSEQ1X21_ADDR 0x35U +#define CSR_ACSMSEQ1X22_ADDR 0x36U +#define CSR_ACSMSEQ1X23_ADDR 0x37U +#define CSR_ACSMSEQ1X24_ADDR 0x38U +#define CSR_ACSMSEQ1X25_ADDR 0x39U +#define CSR_ACSMSEQ1X26_ADDR 0x3AU +#define CSR_ACSMSEQ1X27_ADDR 0x3BU +#define CSR_ACSMSEQ1X28_ADDR 0x3CU +#define CSR_ACSMSEQ1X29_ADDR 0x3DU +#define CSR_ACSMSEQ1X30_ADDR 0x3EU +#define CSR_ACSMSEQ1X31_ADDR 0x3FU +#define CSR_ACSMSEQ2X0_ADDR 0x40U +#define CSR_ACSMSEQ2X1_ADDR 0x41U +#define CSR_ACSMSEQ2X2_ADDR 0x42U +#define CSR_ACSMSEQ2X3_ADDR 0x43U +#define CSR_ACSMSEQ2X4_ADDR 0x44U +#define CSR_ACSMSEQ2X5_ADDR 0x45U +#define CSR_ACSMSEQ2X6_ADDR 0x46U +#define CSR_ACSMSEQ2X7_ADDR 0x47U +#define CSR_ACSMSEQ2X8_ADDR 0x48U +#define CSR_ACSMSEQ2X9_ADDR 0x49U +#define CSR_ACSMSEQ2X10_ADDR 0x4AU +#define CSR_ACSMSEQ2X11_ADDR 0x4BU +#define CSR_ACSMSEQ2X12_ADDR 0x4CU +#define CSR_ACSMSEQ2X13_ADDR 0x4DU +#define CSR_ACSMSEQ2X14_ADDR 0x4EU +#define CSR_ACSMSEQ2X15_ADDR 0x4FU +#define CSR_ACSMSEQ2X16_ADDR 0x50U +#define CSR_ACSMSEQ2X17_ADDR 0x51U +#define CSR_ACSMSEQ2X18_ADDR 0x52U +#define CSR_ACSMSEQ2X19_ADDR 0x53U +#define CSR_ACSMSEQ2X20_ADDR 0x54U +#define CSR_ACSMSEQ2X21_ADDR 0x55U +#define CSR_ACSMSEQ2X22_ADDR 0x56U +#define CSR_ACSMSEQ2X23_ADDR 0x57U +#define CSR_ACSMSEQ2X24_ADDR 0x58U +#define CSR_ACSMSEQ2X25_ADDR 0x59U +#define CSR_ACSMSEQ2X26_ADDR 0x5AU +#define CSR_ACSMSEQ2X27_ADDR 0x5BU +#define CSR_ACSMSEQ2X28_ADDR 0x5CU +#define CSR_ACSMSEQ2X29_ADDR 0x5DU +#define CSR_ACSMSEQ2X30_ADDR 0x5EU +#define CSR_ACSMSEQ2X31_ADDR 0x5FU +#define CSR_ACSMSEQ3X0_ADDR 0x60U +#define CSR_ACSMSEQ3X1_ADDR 0x61U +#define CSR_ACSMSEQ3X2_ADDR 0x62U +#define CSR_ACSMSEQ3X3_ADDR 0x63U +#define CSR_ACSMSEQ3X4_ADDR 0x64U +#define CSR_ACSMSEQ3X5_ADDR 0x65U +#define CSR_ACSMSEQ3X6_ADDR 0x66U +#define CSR_ACSMSEQ3X7_ADDR 0x67U +#define CSR_ACSMSEQ3X8_ADDR 0x68U +#define CSR_ACSMSEQ3X9_ADDR 0x69U +#define CSR_ACSMSEQ3X10_ADDR 0x6AU +#define CSR_ACSMSEQ3X11_ADDR 0x6BU +#define CSR_ACSMSEQ3X12_ADDR 0x6CU +#define CSR_ACSMSEQ3X13_ADDR 0x6DU +#define CSR_ACSMSEQ3X14_ADDR 0x6EU +#define CSR_ACSMSEQ3X15_ADDR 0x6FU +#define CSR_ACSMSEQ3X16_ADDR 0x70U +#define CSR_ACSMSEQ3X17_ADDR 0x71U +#define CSR_ACSMSEQ3X18_ADDR 0x72U +#define CSR_ACSMSEQ3X19_ADDR 0x73U +#define CSR_ACSMSEQ3X20_ADDR 0x74U +#define CSR_ACSMSEQ3X21_ADDR 0x75U +#define CSR_ACSMSEQ3X22_ADDR 0x76U +#define CSR_ACSMSEQ3X23_ADDR 0x77U +#define CSR_ACSMSEQ3X24_ADDR 0x78U +#define CSR_ACSMSEQ3X25_ADDR 0x79U +#define CSR_ACSMSEQ3X26_ADDR 0x7AU +#define CSR_ACSMSEQ3X27_ADDR 0x7BU +#define CSR_ACSMSEQ3X28_ADDR 0x7CU +#define CSR_ACSMSEQ3X29_ADDR 0x7DU +#define CSR_ACSMSEQ3X30_ADDR 0x7EU +#define CSR_ACSMSEQ3X31_ADDR 0x7FU +#define CSR_ACSMPLAYBACK0X0_ADDR 0x80U +#define CSR_ACSMPLAYBACK1X0_ADDR 0x81U +#define CSR_ACSMPLAYBACK0X1_ADDR 0x82U +#define CSR_ACSMPLAYBACK1X1_ADDR 0x83U +#define CSR_ACSMPLAYBACK0X2_ADDR 0x84U +#define CSR_ACSMPLAYBACK1X2_ADDR 0x85U +#define CSR_ACSMPLAYBACK0X3_ADDR 0x86U +#define CSR_ACSMPLAYBACK1X3_ADDR 0x87U +#define CSR_ACSMPLAYBACK0X4_ADDR 0x88U +#define CSR_ACSMPLAYBACK1X4_ADDR 0x89U +#define CSR_ACSMPLAYBACK0X5_ADDR 0x8AU +#define CSR_ACSMPLAYBACK1X5_ADDR 0x8BU +#define CSR_ACSMPLAYBACK0X6_ADDR 0x8CU +#define CSR_ACSMPLAYBACK1X6_ADDR 0x8DU +#define CSR_ACSMPLAYBACK0X7_ADDR 0x8EU +#define CSR_ACSMPLAYBACK1X7_ADDR 0x8FU +#define CSR_ACSMPSTATEOVREN_ADDR 0x90U +#define CSR_ACSMPSTATEOVRVAL_ADDR 0x91U +#define CSR_ACSMCTRL23_ADDR 0xC0U +#define CSR_ACSMCKEVAL_ADDR 0xC2U +#define CSR_LOWSPEEDCLOCKDIVIDER_ADDR 0xC8U +#define CSR_ACSMCSMAPCTRL0_ADDR 0xD0U +#define CSR_ACSMCSMAPCTRL1_ADDR 0xD1U +#define CSR_ACSMCSMAPCTRL2_ADDR 0xD2U +#define CSR_ACSMCSMAPCTRL3_ADDR 0xD3U +#define CSR_ACSMCSMAPCTRL4_ADDR 0xD4U +#define CSR_ACSMCSMAPCTRL5_ADDR 0xD5U +#define CSR_ACSMCSMAPCTRL6_ADDR 0xD6U +#define CSR_ACSMCSMAPCTRL7_ADDR 0xD7U +#define CSR_ACSMCSMAPCTRL8_ADDR 0xD8U +#define CSR_ACSMCSMAPCTRL9_ADDR 0xD9U +#define CSR_ACSMCSMAPCTRL10_ADDR 0xDAU +#define CSR_ACSMCSMAPCTRL11_ADDR 0xDBU +#define CSR_ACSMCSMAPCTRL12_ADDR 0xDCU +#define CSR_ACSMCSMAPCTRL13_ADDR 0xDDU +#define CSR_ACSMCSMAPCTRL14_ADDR 0xDEU +#define CSR_ACSMCSMAPCTRL15_ADDR 0xDFU +#define CSR_ACSMODTCTRL0_ADDR 0xE0U +#define CSR_ACSMODTCTRL1_ADDR 0xE1U +#define CSR_ACSMODTCTRL2_ADDR 0xE2U +#define CSR_ACSMODTCTRL3_ADDR 0xE3U +#define CSR_ACSMODTCTRL4_ADDR 0xE4U +#define CSR_ACSMODTCTRL5_ADDR 0xE5U +#define CSR_ACSMODTCTRL6_ADDR 0xE6U +#define CSR_ACSMODTCTRL7_ADDR 0xE7U +#define CSR_ACSMODTCTRL8_ADDR 0xE8U +#define CSR_ACSMCTRL16_ADDR 0xE9U +#define CSR_LOWSPEEDCLOCKSTOPVAL_ADDR 0xEAU +#define CSR_ACSMCTRL18_ADDR 0xEBU +#define CSR_ACSMCTRL19_ADDR 0xECU +#define CSR_ACSMCTRL20_ADDR 0xEDU +#define CSR_ACSMCTRL21_ADDR 0xEEU +#define CSR_ACSMCTRL22_ADDR 0xEFU +#define CSR_ACSMCTRL0_ADDR 0xF0U +#define CSR_ACSMCTRL1_ADDR 0xF1U +#define CSR_ACSMCTRL2_ADDR 0xF2U +#define CSR_ACSMCTRL3_ADDR 0xF3U +#define CSR_ACSMCTRL4_ADDR 0xF4U +#define CSR_ACSMCTRL5_ADDR 0xF5U +#define CSR_ACSMCTRL6_ADDR 0xF6U +#define CSR_ACSMCTRL7_ADDR 0xF7U +#define CSR_ACSMCTRL8_ADDR 0xF8U +#define CSR_ACSMCTRL9_ADDR 0xF9U +#define CSR_ACSMCTRL10_ADDR 0xFAU +#define CSR_ACSMCTRL11_ADDR 0xFBU +#define CSR_ACSMCTRL12_ADDR 0xFCU +#define CSR_ACSMCTRL13_ADDR 0xFDU +#define CSR_ACSMCTRL14_ADDR 0xFEU +#define CSR_ACSMCTRL15_ADDR 0xFFU + +/* PPGC0 register offsets */ +#define CSR_PPGCCTRL1_ADDR 0x11U +#define CSR_PPGCLANE2CRCINMAP0_ADDR 0x15U +#define CSR_PPGCLANE2CRCINMAP1_ADDR 0x16U +#define CSR_PRBSTAPDLY0_ADDR 0x24U +#define CSR_PRBSTAPDLY1_ADDR 0x25U +#define CSR_PRBSTAPDLY2_ADDR 0x26U +#define CSR_PRBSTAPDLY3_ADDR 0x27U +#define CSR_GENPRBSBYTE0_ADDR 0x30U +#define CSR_GENPRBSBYTE1_ADDR 0x31U +#define CSR_GENPRBSBYTE2_ADDR 0x32U +#define CSR_GENPRBSBYTE3_ADDR 0x33U +#define CSR_GENPRBSBYTE4_ADDR 0x34U +#define CSR_GENPRBSBYTE5_ADDR 0x35U +#define CSR_GENPRBSBYTE6_ADDR 0x36U +#define CSR_GENPRBSBYTE7_ADDR 0x37U +#define CSR_GENPRBSBYTE8_ADDR 0x38U +#define CSR_GENPRBSBYTE9_ADDR 0x39U +#define CSR_GENPRBSBYTE10_ADDR 0x3AU +#define CSR_GENPRBSBYTE11_ADDR 0x3BU +#define CSR_GENPRBSBYTE12_ADDR 0x3CU +#define CSR_GENPRBSBYTE13_ADDR 0x3DU +#define CSR_GENPRBSBYTE14_ADDR 0x3EU +#define CSR_GENPRBSBYTE15_ADDR 0x3FU +#define CSR_PRBSGENCTL_ADDR 0x60U +#define CSR_PRBSGENSTATELO_ADDR 0x61U +#define CSR_PRBSGENSTATEHI_ADDR 0x62U +#define CSR_PRBSCHKSTATELO_ADDR 0x63U +#define CSR_PRBSCHKSTATEHI_ADDR 0x64U +#define CSR_PRBSGENCTL1_ADDR 0x65U +#define CSR_PRBSGENCTL2_ADDR 0x66U + +/* INITENG0 register offsets */ +#define CSR_PRESEQUENCEREG0B0S0_ADDR 0x0U +#define CSR_PRESEQUENCEREG0B0S1_ADDR 0x1U +#define CSR_PRESEQUENCEREG0B0S2_ADDR 0x2U +#define CSR_PRESEQUENCEREG0B1S0_ADDR 0x3U +#define CSR_PRESEQUENCEREG0B1S1_ADDR 0x4U +#define CSR_PRESEQUENCEREG0B1S2_ADDR 0x5U +#define CSR_POSTSEQUENCEREG0B0S0_ADDR 0x6U +#define CSR_POSTSEQUENCEREG0B0S1_ADDR 0x7U +#define CSR_POSTSEQUENCEREG0B0S2_ADDR 0x8U +#define CSR_POSTSEQUENCEREG0B1S0_ADDR 0x9U +#define CSR_POSTSEQUENCEREG0B1S1_ADDR 0xAU +#define CSR_POSTSEQUENCEREG0B1S2_ADDR 0xBU +#define CSR_SEQ0BDISABLEFLAG0_ADDR 0xCU +#define CSR_SEQ0BDISABLEFLAG1_ADDR 0xDU +#define CSR_SEQ0BDISABLEFLAG2_ADDR 0xEU +#define CSR_SEQ0BDISABLEFLAG3_ADDR 0xFU +#define CSR_SEQ0BDISABLEFLAG4_ADDR 0x10U +#define CSR_SEQ0BDISABLEFLAG5_ADDR 0x11U +#define CSR_SEQ0BDISABLEFLAG6_ADDR 0x12U +#define CSR_SEQ0BDISABLEFLAG7_ADDR 0x13U +#define CSR_STARTVECTOR0B0_ADDR 0x17U +#define CSR_STARTVECTOR0B1_ADDR 0x18U +#define CSR_STARTVECTOR0B2_ADDR 0x19U +#define CSR_STARTVECTOR0B3_ADDR 0x1AU +#define CSR_STARTVECTOR0B4_ADDR 0x1BU +#define CSR_STARTVECTOR0B5_ADDR 0x1CU +#define CSR_STARTVECTOR0B6_ADDR 0x1DU +#define CSR_STARTVECTOR0B7_ADDR 0x1EU +#define CSR_STARTVECTOR0B8_ADDR 0x1FU +#define CSR_STARTVECTOR0B9_ADDR 0x20U +#define CSR_STARTVECTOR0B10_ADDR 0x21U +#define CSR_STARTVECTOR0B11_ADDR 0x22U +#define CSR_STARTVECTOR0B12_ADDR 0x23U +#define CSR_STARTVECTOR0B13_ADDR 0x24U +#define CSR_STARTVECTOR0B14_ADDR 0x25U +#define CSR_STARTVECTOR0B15_ADDR 0x26U +#define CSR_SEQ0BWAITCONDSEL_ADDR 0x27U +#define CSR_PHYINLP3_ADDR 0x28U +#define CSR_SEQUENCEREG0B0S0_ADDR 0x29U +#define CSR_SEQUENCEREG0B0S1_ADDR 0x2AU +#define CSR_SEQUENCEREG0B0S2_ADDR 0x2BU +#define CSR_SEQUENCEREG0B1S0_ADDR 0x2CU +#define CSR_SEQUENCEREG0B1S1_ADDR 0x2DU +#define CSR_SEQUENCEREG0B1S2_ADDR 0x2EU +#define CSR_SEQUENCEREG0B2S0_ADDR 0x2FU +#define CSR_SEQUENCEREG0B2S1_ADDR 0x30U +#define CSR_SEQUENCEREG0B2S2_ADDR 0x31U +#define CSR_SEQUENCEREG0B3S0_ADDR 0x32U +#define CSR_SEQUENCEREG0B3S1_ADDR 0x33U +#define CSR_SEQUENCEREG0B3S2_ADDR 0x34U +#define CSR_SEQUENCEREG0B4S0_ADDR 0x35U +#define CSR_SEQUENCEREG0B4S1_ADDR 0x36U +#define CSR_SEQUENCEREG0B4S2_ADDR 0x37U +#define CSR_SEQUENCEREG0B5S0_ADDR 0x38U +#define CSR_SEQUENCEREG0B5S1_ADDR 0x39U +#define CSR_SEQUENCEREG0B5S2_ADDR 0x3AU +#define CSR_SEQUENCEREG0B6S0_ADDR 0x3BU +#define CSR_SEQUENCEREG0B6S1_ADDR 0x3CU +#define CSR_SEQUENCEREG0B6S2_ADDR 0x3DU +#define CSR_SEQUENCEREG0B7S0_ADDR 0x3EU +#define CSR_SEQUENCEREG0B7S1_ADDR 0x3FU +#define CSR_SEQUENCEREG0B7S2_ADDR 0x40U +#define CSR_SEQUENCEREG0B8S0_ADDR 0x41U +#define CSR_SEQUENCEREG0B8S1_ADDR 0x42U +#define CSR_SEQUENCEREG0B8S2_ADDR 0x43U +#define CSR_SEQUENCEREG0B9S0_ADDR 0x44U +#define CSR_SEQUENCEREG0B9S1_ADDR 0x45U +#define CSR_SEQUENCEREG0B9S2_ADDR 0x46U +#define CSR_SEQUENCEREG0B10S0_ADDR 0x47U +#define CSR_SEQUENCEREG0B10S1_ADDR 0x48U +#define CSR_SEQUENCEREG0B10S2_ADDR 0x49U +#define CSR_SEQUENCEREG0B11S0_ADDR 0x4AU +#define CSR_SEQUENCEREG0B11S1_ADDR 0x4BU +#define CSR_SEQUENCEREG0B11S2_ADDR 0x4CU +#define CSR_SEQUENCEREG0B12S0_ADDR 0x4DU +#define CSR_SEQUENCEREG0B12S1_ADDR 0x4EU +#define CSR_SEQUENCEREG0B12S2_ADDR 0x4FU +#define CSR_SEQUENCEREG0B13S0_ADDR 0x50U +#define CSR_SEQUENCEREG0B13S1_ADDR 0x51U +#define CSR_SEQUENCEREG0B13S2_ADDR 0x52U +#define CSR_SEQUENCEREG0B14S0_ADDR 0x53U +#define CSR_SEQUENCEREG0B14S1_ADDR 0x54U +#define CSR_SEQUENCEREG0B14S2_ADDR 0x55U +#define CSR_SEQUENCEREG0B15S0_ADDR 0x56U +#define CSR_SEQUENCEREG0B15S1_ADDR 0x57U +#define CSR_SEQUENCEREG0B15S2_ADDR 0x58U +#define CSR_SEQUENCEREG0B16S0_ADDR 0x59U +#define CSR_SEQUENCEREG0B16S1_ADDR 0x5AU +#define CSR_SEQUENCEREG0B16S2_ADDR 0x5BU +#define CSR_SEQUENCEREG0B17S0_ADDR 0x5CU +#define CSR_SEQUENCEREG0B17S1_ADDR 0x5DU +#define CSR_SEQUENCEREG0B17S2_ADDR 0x5EU +#define CSR_SEQUENCEREG0B18S0_ADDR 0x5FU +#define CSR_SEQUENCEREG0B18S1_ADDR 0x60U +#define CSR_SEQUENCEREG0B18S2_ADDR 0x61U +#define CSR_SEQUENCEREG0B19S0_ADDR 0x62U +#define CSR_SEQUENCEREG0B19S1_ADDR 0x63U +#define CSR_SEQUENCEREG0B19S2_ADDR 0x64U +#define CSR_SEQUENCEREG0B20S0_ADDR 0x65U +#define CSR_SEQUENCEREG0B20S1_ADDR 0x66U +#define CSR_SEQUENCEREG0B20S2_ADDR 0x67U +#define CSR_SEQUENCEREG0B21S0_ADDR 0x68U +#define CSR_SEQUENCEREG0B21S1_ADDR 0x69U +#define CSR_SEQUENCEREG0B21S2_ADDR 0x6AU +#define CSR_SEQUENCEREG0B22S0_ADDR 0x6BU +#define CSR_SEQUENCEREG0B22S1_ADDR 0x6CU +#define CSR_SEQUENCEREG0B22S2_ADDR 0x6DU +#define CSR_SEQUENCEREG0B23S0_ADDR 0x6EU +#define CSR_SEQUENCEREG0B23S1_ADDR 0x6FU +#define CSR_SEQUENCEREG0B23S2_ADDR 0x70U +#define CSR_SEQUENCEREG0B24S0_ADDR 0x71U +#define CSR_SEQUENCEREG0B24S1_ADDR 0x72U +#define CSR_SEQUENCEREG0B24S2_ADDR 0x73U +#define CSR_SEQUENCEREG0B25S0_ADDR 0x74U +#define CSR_SEQUENCEREG0B25S1_ADDR 0x75U +#define CSR_SEQUENCEREG0B25S2_ADDR 0x76U +#define CSR_SEQUENCEREG0B26S0_ADDR 0x77U +#define CSR_SEQUENCEREG0B26S1_ADDR 0x78U +#define CSR_SEQUENCEREG0B26S2_ADDR 0x79U +#define CSR_SEQUENCEREG0B27S0_ADDR 0x7AU +#define CSR_SEQUENCEREG0B27S1_ADDR 0x7BU +#define CSR_SEQUENCEREG0B27S2_ADDR 0x7CU +#define CSR_SEQUENCEREG0B28S0_ADDR 0x7DU +#define CSR_SEQUENCEREG0B28S1_ADDR 0x7EU +#define CSR_SEQUENCEREG0B28S2_ADDR 0x7FU +#define CSR_SEQUENCEREG0B29S0_ADDR 0x80U +#define CSR_SEQUENCEREG0B29S1_ADDR 0x81U +#define CSR_SEQUENCEREG0B29S2_ADDR 0x82U +#define CSR_SEQUENCEREG0B30S0_ADDR 0x83U +#define CSR_SEQUENCEREG0B30S1_ADDR 0x84U +#define CSR_SEQUENCEREG0B30S2_ADDR 0x85U +#define CSR_SEQUENCEREG0B31S0_ADDR 0x86U +#define CSR_SEQUENCEREG0B31S1_ADDR 0x87U +#define CSR_SEQUENCEREG0B31S2_ADDR 0x88U +#define CSR_SEQUENCEREG0B32S0_ADDR 0x89U +#define CSR_SEQUENCEREG0B32S1_ADDR 0x8AU +#define CSR_SEQUENCEREG0B32S2_ADDR 0x8BU +#define CSR_SEQUENCEREG0B33S0_ADDR 0x8CU +#define CSR_SEQUENCEREG0B33S1_ADDR 0x8DU +#define CSR_SEQUENCEREG0B33S2_ADDR 0x8EU +#define CSR_SEQUENCEREG0B34S0_ADDR 0x8FU +#define CSR_SEQUENCEREG0B34S1_ADDR 0x90U +#define CSR_SEQUENCEREG0B34S2_ADDR 0x91U +#define CSR_SEQUENCEREG0B35S0_ADDR 0x92U +#define CSR_SEQUENCEREG0B35S1_ADDR 0x93U +#define CSR_SEQUENCEREG0B35S2_ADDR 0x94U +#define CSR_SEQUENCEREG0B36S0_ADDR 0x95U +#define CSR_SEQUENCEREG0B36S1_ADDR 0x96U +#define CSR_SEQUENCEREG0B36S2_ADDR 0x97U +#define CSR_SEQUENCEREG0B37S0_ADDR 0x98U +#define CSR_SEQUENCEREG0B37S1_ADDR 0x99U +#define CSR_SEQUENCEREG0B37S2_ADDR 0x9AU +#define CSR_SEQUENCEREG0B38S0_ADDR 0x9BU +#define CSR_SEQUENCEREG0B38S1_ADDR 0x9CU +#define CSR_SEQUENCEREG0B38S2_ADDR 0x9DU +#define CSR_SEQUENCEREG0B39S0_ADDR 0x9EU +#define CSR_SEQUENCEREG0B39S1_ADDR 0x9FU +#define CSR_SEQUENCEREG0B39S2_ADDR 0xA0U +#define CSR_SEQUENCEREG0B40S0_ADDR 0xA1U +#define CSR_SEQUENCEREG0B40S1_ADDR 0xA2U +#define CSR_SEQUENCEREG0B40S2_ADDR 0xA3U +#define CSR_SEQUENCEREG0B41S0_ADDR 0xA4U +#define CSR_SEQUENCEREG0B41S1_ADDR 0xA5U +#define CSR_SEQUENCEREG0B41S2_ADDR 0xA6U +#define CSR_SEQUENCEREG0B42S0_ADDR 0xA7U +#define CSR_SEQUENCEREG0B42S1_ADDR 0xA8U +#define CSR_SEQUENCEREG0B42S2_ADDR 0xA9U +#define CSR_SEQUENCEREG0B43S0_ADDR 0xAAU +#define CSR_SEQUENCEREG0B43S1_ADDR 0xABU +#define CSR_SEQUENCEREG0B43S2_ADDR 0xACU +#define CSR_SEQUENCEREG0B44S0_ADDR 0xADU +#define CSR_SEQUENCEREG0B44S1_ADDR 0xAEU +#define CSR_SEQUENCEREG0B44S2_ADDR 0xAFU +#define CSR_SEQUENCEREG0B45S0_ADDR 0xB0U +#define CSR_SEQUENCEREG0B45S1_ADDR 0xB1U +#define CSR_SEQUENCEREG0B45S2_ADDR 0xB2U +#define CSR_SEQUENCEREG0B46S0_ADDR 0xB3U +#define CSR_SEQUENCEREG0B46S1_ADDR 0xB4U +#define CSR_SEQUENCEREG0B46S2_ADDR 0xB5U +#define CSR_SEQUENCEREG0B47S0_ADDR 0xB6U +#define CSR_SEQUENCEREG0B47S1_ADDR 0xB7U +#define CSR_SEQUENCEREG0B47S2_ADDR 0xB8U +#define CSR_SEQUENCEREG0B48S0_ADDR 0xB9U +#define CSR_SEQUENCEREG0B48S1_ADDR 0xBAU +#define CSR_SEQUENCEREG0B48S2_ADDR 0xBBU +#define CSR_SEQUENCEREG0B49S0_ADDR 0xBCU +#define CSR_SEQUENCEREG0B49S1_ADDR 0xBDU +#define CSR_SEQUENCEREG0B49S2_ADDR 0xBEU +#define CSR_SEQUENCEREG0B50S0_ADDR 0xBFU +#define CSR_SEQUENCEREG0B50S1_ADDR 0xC0U +#define CSR_SEQUENCEREG0B50S2_ADDR 0xC1U +#define CSR_SEQUENCEREG0B51S0_ADDR 0xC2U +#define CSR_SEQUENCEREG0B51S1_ADDR 0xC3U +#define CSR_SEQUENCEREG0B51S2_ADDR 0xC4U +#define CSR_SEQUENCEREG0B52S0_ADDR 0xC5U +#define CSR_SEQUENCEREG0B52S1_ADDR 0xC6U +#define CSR_SEQUENCEREG0B52S2_ADDR 0xC7U +#define CSR_SEQUENCEREG0B53S0_ADDR 0xC8U +#define CSR_SEQUENCEREG0B53S1_ADDR 0xC9U +#define CSR_SEQUENCEREG0B53S2_ADDR 0xCAU +#define CSR_SEQUENCEREG0B54S0_ADDR 0xCBU +#define CSR_SEQUENCEREG0B54S1_ADDR 0xCCU +#define CSR_SEQUENCEREG0B54S2_ADDR 0xCDU +#define CSR_SEQUENCEREG0B55S0_ADDR 0xCEU +#define CSR_SEQUENCEREG0B55S1_ADDR 0xCFU +#define CSR_SEQUENCEREG0B55S2_ADDR 0xD0U +#define CSR_SEQUENCEREG0B56S0_ADDR 0xD1U +#define CSR_SEQUENCEREG0B56S1_ADDR 0xD2U +#define CSR_SEQUENCEREG0B56S2_ADDR 0xD3U +#define CSR_SEQUENCEREG0B57S0_ADDR 0xD4U +#define CSR_SEQUENCEREG0B57S1_ADDR 0xD5U +#define CSR_SEQUENCEREG0B57S2_ADDR 0xD6U +#define CSR_SEQUENCEREG0B58S0_ADDR 0xD7U +#define CSR_SEQUENCEREG0B58S1_ADDR 0xD8U +#define CSR_SEQUENCEREG0B58S2_ADDR 0xD9U +#define CSR_SEQUENCEREG0B59S0_ADDR 0xDAU +#define CSR_SEQUENCEREG0B59S1_ADDR 0xDBU +#define CSR_SEQUENCEREG0B59S2_ADDR 0xDCU +#define CSR_SEQUENCEREG0B60S0_ADDR 0xDDU +#define CSR_SEQUENCEREG0B60S1_ADDR 0xDEU +#define CSR_SEQUENCEREG0B60S2_ADDR 0xDFU +#define CSR_SEQUENCEREG0B61S0_ADDR 0xE0U +#define CSR_SEQUENCEREG0B61S1_ADDR 0xE1U +#define CSR_SEQUENCEREG0B61S2_ADDR 0xE2U +#define CSR_SEQUENCEREG0B62S0_ADDR 0xE3U +#define CSR_SEQUENCEREG0B62S1_ADDR 0xE4U +#define CSR_SEQUENCEREG0B62S2_ADDR 0xE5U +#define CSR_SEQUENCEREG0B63S0_ADDR 0xE6U +#define CSR_SEQUENCEREG0B63S1_ADDR 0xE7U +#define CSR_SEQUENCEREG0B63S2_ADDR 0xE8U +#define CSR_SEQUENCEREG0B64S0_ADDR 0xE9U +#define CSR_SEQUENCEREG0B64S1_ADDR 0xEAU +#define CSR_SEQUENCEREG0B64S2_ADDR 0xEBU +#define CSR_SEQUENCEREG0B65S0_ADDR 0xECU +#define CSR_SEQUENCEREG0B65S1_ADDR 0xEDU +#define CSR_SEQUENCEREG0B65S2_ADDR 0xEEU +#define CSR_SEQUENCEREG0B66S0_ADDR 0xEFU +#define CSR_SEQUENCEREG0B66S1_ADDR 0xF0U +#define CSR_SEQUENCEREG0B66S2_ADDR 0xF1U +#define CSR_SEQUENCEREG0B67S0_ADDR 0xF2U +#define CSR_SEQUENCEREG0B67S1_ADDR 0xF3U +#define CSR_SEQUENCEREG0B67S2_ADDR 0xF4U +#define CSR_SEQUENCEREG0B68S0_ADDR 0xF5U +#define CSR_SEQUENCEREG0B68S1_ADDR 0xF6U +#define CSR_SEQUENCEREG0B68S2_ADDR 0xF7U +#define CSR_SEQUENCEREG0B69S0_ADDR 0xF8U +#define CSR_SEQUENCEREG0B69S1_ADDR 0xF9U +#define CSR_SEQUENCEREG0B69S2_ADDR 0xFAU +#define CSR_SEQUENCEREG0B70S0_ADDR 0xFBU +#define CSR_SEQUENCEREG0B70S1_ADDR 0xFCU +#define CSR_SEQUENCEREG0B70S2_ADDR 0xFDU +#define CSR_SEQUENCEREG0B71S0_ADDR 0xFEU +#define CSR_SEQUENCEREG0B71S1_ADDR 0xFFU +#define CSR_SEQUENCEREG0B71S2_ADDR 0x100U +#define CSR_SEQUENCEREG0B72S0_ADDR 0x101U +#define CSR_SEQUENCEREG0B72S1_ADDR 0x102U +#define CSR_SEQUENCEREG0B72S2_ADDR 0x103U +#define CSR_SEQUENCEREG0B73S0_ADDR 0x104U +#define CSR_SEQUENCEREG0B73S1_ADDR 0x105U +#define CSR_SEQUENCEREG0B73S2_ADDR 0x106U +#define CSR_SEQUENCEREG0B74S0_ADDR 0x107U +#define CSR_SEQUENCEREG0B74S1_ADDR 0x108U +#define CSR_SEQUENCEREG0B74S2_ADDR 0x109U +#define CSR_SEQUENCEREG0B75S0_ADDR 0x10AU +#define CSR_SEQUENCEREG0B75S1_ADDR 0x10BU +#define CSR_SEQUENCEREG0B75S2_ADDR 0x10CU +#define CSR_SEQUENCEREG0B76S0_ADDR 0x10DU +#define CSR_SEQUENCEREG0B76S1_ADDR 0x10EU +#define CSR_SEQUENCEREG0B76S2_ADDR 0x10FU +#define CSR_SEQUENCEREG0B77S0_ADDR 0x110U +#define CSR_SEQUENCEREG0B77S1_ADDR 0x111U +#define CSR_SEQUENCEREG0B77S2_ADDR 0x112U +#define CSR_SEQUENCEREG0B78S0_ADDR 0x113U +#define CSR_SEQUENCEREG0B78S1_ADDR 0x114U +#define CSR_SEQUENCEREG0B78S2_ADDR 0x115U +#define CSR_SEQUENCEREG0B79S0_ADDR 0x116U +#define CSR_SEQUENCEREG0B79S1_ADDR 0x117U +#define CSR_SEQUENCEREG0B79S2_ADDR 0x118U +#define CSR_SEQUENCEREG0B80S0_ADDR 0x119U +#define CSR_SEQUENCEREG0B80S1_ADDR 0x11AU +#define CSR_SEQUENCEREG0B80S2_ADDR 0x11BU +#define CSR_SEQUENCEREG0B81S0_ADDR 0x11CU +#define CSR_SEQUENCEREG0B81S1_ADDR 0x11DU +#define CSR_SEQUENCEREG0B81S2_ADDR 0x11EU +#define CSR_SEQUENCEREG0B82S0_ADDR 0x11FU +#define CSR_SEQUENCEREG0B82S1_ADDR 0x120U +#define CSR_SEQUENCEREG0B82S2_ADDR 0x121U +#define CSR_SEQUENCEREG0B83S0_ADDR 0x122U +#define CSR_SEQUENCEREG0B83S1_ADDR 0x123U +#define CSR_SEQUENCEREG0B83S2_ADDR 0x124U +#define CSR_SEQUENCEREG0B84S0_ADDR 0x125U +#define CSR_SEQUENCEREG0B84S1_ADDR 0x126U +#define CSR_SEQUENCEREG0B84S2_ADDR 0x127U +#define CSR_SEQUENCEREG0B85S0_ADDR 0x128U +#define CSR_SEQUENCEREG0B85S1_ADDR 0x129U +#define CSR_SEQUENCEREG0B85S2_ADDR 0x12AU +#define CSR_SEQUENCEREG0B86S0_ADDR 0x12BU +#define CSR_SEQUENCEREG0B86S1_ADDR 0x12CU +#define CSR_SEQUENCEREG0B86S2_ADDR 0x12DU +#define CSR_SEQUENCEREG0B87S0_ADDR 0x12EU +#define CSR_SEQUENCEREG0B87S1_ADDR 0x12FU +#define CSR_SEQUENCEREG0B87S2_ADDR 0x130U +#define CSR_SEQUENCEREG0B88S0_ADDR 0x131U +#define CSR_SEQUENCEREG0B88S1_ADDR 0x132U +#define CSR_SEQUENCEREG0B88S2_ADDR 0x133U +#define CSR_SEQUENCEREG0B89S0_ADDR 0x134U +#define CSR_SEQUENCEREG0B89S1_ADDR 0x135U +#define CSR_SEQUENCEREG0B89S2_ADDR 0x136U +#define CSR_SEQUENCEREG0B90S0_ADDR 0x137U +#define CSR_SEQUENCEREG0B90S1_ADDR 0x138U +#define CSR_SEQUENCEREG0B90S2_ADDR 0x139U +#define CSR_SEQUENCEREG0B91S0_ADDR 0x13AU +#define CSR_SEQUENCEREG0B91S1_ADDR 0x13BU +#define CSR_SEQUENCEREG0B91S2_ADDR 0x13CU +#define CSR_SEQUENCEREG0B92S0_ADDR 0x13DU +#define CSR_SEQUENCEREG0B92S1_ADDR 0x13EU +#define CSR_SEQUENCEREG0B92S2_ADDR 0x13FU +#define CSR_SEQUENCEREG0B93S0_ADDR 0x140U +#define CSR_SEQUENCEREG0B93S1_ADDR 0x141U +#define CSR_SEQUENCEREG0B93S2_ADDR 0x142U +#define CSR_SEQUENCEREG0B94S0_ADDR 0x143U +#define CSR_SEQUENCEREG0B94S1_ADDR 0x144U +#define CSR_SEQUENCEREG0B94S2_ADDR 0x145U +#define CSR_SEQUENCEREG0B95S0_ADDR 0x146U +#define CSR_SEQUENCEREG0B95S1_ADDR 0x147U +#define CSR_SEQUENCEREG0B95S2_ADDR 0x148U +#define CSR_SEQUENCEREG0B96S0_ADDR 0x149U +#define CSR_SEQUENCEREG0B96S1_ADDR 0x14AU +#define CSR_SEQUENCEREG0B96S2_ADDR 0x14BU +#define CSR_SEQUENCEREG0B97S0_ADDR 0x14CU +#define CSR_SEQUENCEREG0B97S1_ADDR 0x14DU +#define CSR_SEQUENCEREG0B97S2_ADDR 0x14EU +#define CSR_SEQUENCEREG0B98S0_ADDR 0x14FU +#define CSR_SEQUENCEREG0B98S1_ADDR 0x150U +#define CSR_SEQUENCEREG0B98S2_ADDR 0x151U +#define CSR_SEQUENCEREG0B99S0_ADDR 0x152U +#define CSR_SEQUENCEREG0B99S1_ADDR 0x153U +#define CSR_SEQUENCEREG0B99S2_ADDR 0x154U +#define CSR_SEQUENCEREG0B100S0_ADDR 0x155U +#define CSR_SEQUENCEREG0B100S1_ADDR 0x156U +#define CSR_SEQUENCEREG0B100S2_ADDR 0x157U +#define CSR_SEQUENCEREG0B101S0_ADDR 0x158U +#define CSR_SEQUENCEREG0B101S1_ADDR 0x159U +#define CSR_SEQUENCEREG0B101S2_ADDR 0x15AU +#define CSR_SEQUENCEREG0B102S0_ADDR 0x15BU +#define CSR_SEQUENCEREG0B102S1_ADDR 0x15CU +#define CSR_SEQUENCEREG0B102S2_ADDR 0x15DU +#define CSR_SEQUENCEREG0B103S0_ADDR 0x15EU +#define CSR_SEQUENCEREG0B103S1_ADDR 0x15FU +#define CSR_SEQUENCEREG0B103S2_ADDR 0x160U +#define CSR_SEQUENCEREG0B104S0_ADDR 0x161U +#define CSR_SEQUENCEREG0B104S1_ADDR 0x162U +#define CSR_SEQUENCEREG0B104S2_ADDR 0x163U +#define CSR_SEQUENCEREG0B105S0_ADDR 0x164U +#define CSR_SEQUENCEREG0B105S1_ADDR 0x165U +#define CSR_SEQUENCEREG0B105S2_ADDR 0x166U +#define CSR_SEQUENCEREG0B106S0_ADDR 0x167U +#define CSR_SEQUENCEREG0B106S1_ADDR 0x168U +#define CSR_SEQUENCEREG0B106S2_ADDR 0x169U +#define CSR_SEQUENCEREG0B107S0_ADDR 0x16AU +#define CSR_SEQUENCEREG0B107S1_ADDR 0x16BU +#define CSR_SEQUENCEREG0B107S2_ADDR 0x16CU +#define CSR_SEQUENCEREG0B108S0_ADDR 0x16DU +#define CSR_SEQUENCEREG0B108S1_ADDR 0x16EU +#define CSR_SEQUENCEREG0B108S2_ADDR 0x16FU +#define CSR_SEQUENCEREG0B109S0_ADDR 0x170U +#define CSR_SEQUENCEREG0B109S1_ADDR 0x171U +#define CSR_SEQUENCEREG0B109S2_ADDR 0x172U +#define CSR_SEQUENCEREG0B110S0_ADDR 0x173U +#define CSR_SEQUENCEREG0B110S1_ADDR 0x174U +#define CSR_SEQUENCEREG0B110S2_ADDR 0x175U +#define CSR_SEQUENCEREG0B111S0_ADDR 0x176U +#define CSR_SEQUENCEREG0B111S1_ADDR 0x177U +#define CSR_SEQUENCEREG0B111S2_ADDR 0x178U +#define CSR_SEQUENCEREG0B112S0_ADDR 0x179U +#define CSR_SEQUENCEREG0B112S1_ADDR 0x17AU +#define CSR_SEQUENCEREG0B112S2_ADDR 0x17BU +#define CSR_SEQUENCEREG0B113S0_ADDR 0x17CU +#define CSR_SEQUENCEREG0B113S1_ADDR 0x17DU +#define CSR_SEQUENCEREG0B113S2_ADDR 0x17EU +#define CSR_SEQUENCEREG0B114S0_ADDR 0x17FU +#define CSR_SEQUENCEREG0B114S1_ADDR 0x180U +#define CSR_SEQUENCEREG0B114S2_ADDR 0x181U +#define CSR_SEQUENCEREG0B115S0_ADDR 0x182U +#define CSR_SEQUENCEREG0B115S1_ADDR 0x183U +#define CSR_SEQUENCEREG0B115S2_ADDR 0x184U +#define CSR_SEQUENCEREG0B116S0_ADDR 0x185U +#define CSR_SEQUENCEREG0B116S1_ADDR 0x186U +#define CSR_SEQUENCEREG0B116S2_ADDR 0x187U +#define CSR_SEQUENCEREG0B117S0_ADDR 0x188U +#define CSR_SEQUENCEREG0B117S1_ADDR 0x189U +#define CSR_SEQUENCEREG0B117S2_ADDR 0x18AU +#define CSR_SEQUENCEREG0B118S0_ADDR 0x18BU +#define CSR_SEQUENCEREG0B118S1_ADDR 0x18CU +#define CSR_SEQUENCEREG0B118S2_ADDR 0x18DU +#define CSR_SEQUENCEREG0B119S0_ADDR 0x18EU +#define CSR_SEQUENCEREG0B119S1_ADDR 0x18FU +#define CSR_SEQUENCEREG0B119S2_ADDR 0x190U +#define CSR_SEQUENCEREG0B120S0_ADDR 0x191U +#define CSR_SEQUENCEREG0B120S1_ADDR 0x192U +#define CSR_SEQUENCEREG0B120S2_ADDR 0x193U +#define CSR_SEQUENCEREG0B121S0_ADDR 0x194U +#define CSR_SEQUENCEREG0B121S1_ADDR 0x195U +#define CSR_SEQUENCEREG0B121S2_ADDR 0x196U +#define CSR_SEQ0BGPR1_ADDR 0x201U +#define CSR_SEQ0BGPR2_ADDR 0x202U +#define CSR_SEQ0BGPR3_ADDR 0x203U +#define CSR_SEQ0BGPR4_ADDR 0x204U +#define CSR_SEQ0BGPR5_ADDR 0x205U +#define CSR_SEQ0BGPR6_ADDR 0x206U +#define CSR_SEQ0BGPR7_ADDR 0x207U +#define CSR_SEQ0BGPR8_ADDR 0x208U +#define CSR_SEQ0BFIXEDADDRBITS_ADDR 0x2FFU + +/* DRTUB0 register offsets */ +#define CSR_DCTSHADOWREGS_ADDR 0x4U +#define CSR_DCTWRITEONLYSHADOW_ADDR 0x30U +#define CSR_UCTWRITEONLY_ADDR 0x32U +#define CSR_UCTWRITEPROT_ADDR 0x33U +#define CSR_UCTDATWRITEONLY_ADDR 0x34U +#define CSR_UCTDATWRITEPROT_ADDR 0x35U +#define CSR_UCTLERR_ADDR 0x36U +#define CSR_UCCLKHCLKENABLES_ADDR 0x80U +#define CSR_CURPSTATE0B_ADDR 0x81U +#define CSR_CLRWAKEUPSTICKY_ADDR 0x95U +#define CSR_WAKEUPMASK_ADDR 0x96U +#define CSR_CUSTPUBREV_ADDR 0xEDU +#define CSR_PUBREV_ADDR 0xEEU + +/* APBONLY0 register offsets */ +#define CSR_MICROCONTMUXSEL_ADDR 0x0U +#define CSR_UCTSHADOWREGS_ADDR 0x4U +#define CSR_DCTWRITEONLY_ADDR 0x30U +#define CSR_DCTWRITEPROT_ADDR 0x31U +#define CSR_UCTWRITEONLYSHADOW_ADDR 0x32U +#define CSR_UCTDATWRITEONLYSHADOW_ADDR 0x34U +#define CSR_NEVERGATECSRCLOCK_ADDR 0x35U +#define CSR_DFICFGRDDATAVALIDTICKS_ADDR 0x37U +#define CSR_MICRORESET_ADDR 0x99U +#define CSR_SEQUENCEROVERRIDE_ADDR 0xE7U +#define CSR_DFIINITCOMPLETESHADOW_ADDR 0xFAU + +/* ANIBx register bit fields */ +/* CSR_MTESTMUXSEL */ +#define CSR_MTESTMUXSEL_LSB 0 +#define CSR_MTESTMUXSEL_MASK GENMASK_32(5, 0) +/* CSR_AFORCEDRVCONT */ +#define CSR_AFORCEDRVCONT_LSB 0 +#define CSR_AFORCEDRVCONT_MASK GENMASK_32(3, 0) +/* CSR_AFORCETRICONT */ +#define CSR_AFORCETRICONT_LSB 0 +#define CSR_AFORCETRICONT_MASK GENMASK_32(3, 0) +/* CSR_ATXIMPEDANCE */ +#define CSR_ATXIMPEDANCE_LSB 0 +#define CSR_ATXIMPEDANCE_MASK GENMASK_32(9, 0) +#define CSR_ADRVSTRENP_LSB 0 +#define CSR_ADRVSTRENP_MASK GENMASK_32(4, 0) +#define CSR_ADRVSTRENN_LSB 5 +#define CSR_ADRVSTRENN_MASK GENMASK_32(9, 5) +/* CSR_ATESTPRBSERR */ +#define CSR_ATESTPRBSERR_LSB 0 +#define CSR_ATESTPRBSERR_MASK GENMASK_32(3, 0) +/* CSR_ATXSLEWRATE */ +#define CSR_ATXSLEWRATE_LSB 0 +#define CSR_ATXSLEWRATE_MASK GENMASK_32(10, 0) +#define CSR_ATXPREP_LSB 0 +#define CSR_ATXPREP_MASK GENMASK_32(3, 0) +#define CSR_ATXPREN_LSB 4 +#define CSR_ATXPREN_MASK GENMASK_32(7, 4) +#define CSR_ATXPREDRVMODE_LSB 8 +#define CSR_ATXPREDRVMODE_MASK GENMASK_32(10, 8) +/* CSR_ATESTPRBSERRCNT */ +#define CSR_ATESTPRBSERRCNT_LSB 0 +#define CSR_ATESTPRBSERRCNT_MASK GENMASK_32(15, 0) +/* CSR_ATXDLY */ +#define CSR_ATXDLY_LSB 0 +#define CSR_ATXDLY_MASK GENMASK_32(6, 0) + +/* DBYTEx register bit fields */ +/* CSR_DBYTEMISCMODE */ +#define CSR_DBYTEMISCMODE_LSB 2 +#define CSR_DBYTEMISCMODE_MASK BIT(2) +#define CSR_DBYTEDISABLE_LSB 2 +#define CSR_DBYTEDISABLE_MASK BIT(2) +/* CSR_TSMBYTE0 */ +#define CSR_TSMBYTE0_LSB 0 +#define CSR_TSMBYTE0_MASK GENMASK_32(15, 0) +#define CSR_PERPHTRAINEN_LSB 0 +#define CSR_PERPHTRAINEN_MASK BIT(0) +#define CSR_EYEINC_LSB 1 +#define CSR_EYEINC_MASK BIT(1) +#define CSR_EDGEINC_LSB 2 +#define CSR_EDGEINC_MASK BIT(2) +#define CSR_EDGEEYEMXSEL_LSB 3 +#define CSR_EDGEEYEMXSEL_MASK BIT(3) +#define CSR_TSMBYTE0RSVD_LSB 4 +#define CSR_TSMBYTE0RSVD_MASK GENMASK_32(5, 4) +#define CSR_DIMMBROADINC_LSB 6 +#define CSR_DIMMBROADINC_MASK BIT(6) +#define CSR_DIMMINC_LSB 7 +#define CSR_DIMMINC_MASK GENMASK_32(8, 7) +#define CSR_COARSEINC_LSB 9 +#define CSR_COARSEINC_MASK BIT(9) +#define CSR_DELAYINC_LSB 10 +#define CSR_DELAYINC_MASK BIT(10) +#define CSR_RXINC_LSB 11 +#define CSR_RXINC_MASK BIT(11) +#define CSR_RXPERTRAIN_LSB 12 +#define CSR_RXPERTRAIN_MASK BIT(12) +#define CSR_TXPERTRAIN_LSB 13 +#define CSR_TXPERTRAIN_MASK BIT(13) +#define CSR_DMTRAIN_LSB 14 +#define CSR_DMTRAIN_MASK BIT(14) +#define CSR_WRLEVTRAIN_LSB 15 +#define CSR_WRLEVTRAIN_MASK BIT(15) +/* CSR_TRAININGPARAM */ +#define CSR_TRAININGPARAM_LSB 0 +#define CSR_TRAININGPARAM_MASK GENMASK_32(15, 0) +#define CSR_ENDYNRATEREDUCTION_LSB 0 +#define CSR_ENDYNRATEREDUCTION_MASK BIT(0) +#define CSR_TRAININGPARAM01RSVD_LSB 1 +#define CSR_TRAININGPARAM01RSVD_MASK BIT(1) +#define CSR_TRAINENRXCLK_LSB 2 +#define CSR_TRAINENRXCLK_MASK BIT(2) +#define CSR_TRAINENRXEN_LSB 3 +#define CSR_TRAINENRXEN_MASK BIT(3) +#define CSR_TRAINENTXDQS_LSB 4 +#define CSR_TRAINENTXDQS_MASK BIT(4) +#define CSR_TRAINENTXDQ_LSB 5 +#define CSR_TRAINENTXDQ_MASK BIT(5) +#define CSR_TRAINENVREFDAC1_LSB 6 +#define CSR_TRAINENVREFDAC1_MASK BIT(6) +#define CSR_TRAINENVREFDAC0_LSB 7 +#define CSR_TRAINENVREFDAC0_MASK BIT(7) +#define CSR_TRAINENRXPBD_LSB 8 +#define CSR_TRAINENRXPBD_MASK BIT(8) +#define CSR_ROLLINTOCOARSE_LSB 9 +#define CSR_ROLLINTOCOARSE_MASK BIT(9) +#define CSR_TRAINUSINGNATIVEDDLCNTL_LSB 10 +#define CSR_TRAINUSINGNATIVEDDLCNTL_MASK BIT(10) +#define CSR_TRAININGPARAM11RSVD_LSB 11 +#define CSR_TRAININGPARAM11RSVD_MASK BIT(11) +#define CSR_TRAININGPARAM12RSVD_LSB 12 +#define CSR_TRAININGPARAM12RSVD_MASK BIT(12) +#define CSR_INCDECRATE_LSB 13 +#define CSR_INCDECRATE_MASK GENMASK_32(15, 13) +/* CSR_USEDQSENREPLICA */ +#define CSR_USEDQSENREPLICA_LSB 0 +#define CSR_USEDQSENREPLICA_MASK BIT(0) +/* CSR_RXTRAINPATTERNENABLE */ +#define CSR_RXTRAINPATTERNENABLE_LSB 0 +#define CSR_RXTRAINPATTERNENABLE_MASK BIT(0) +/* CSR_TSMBYTE1 */ +#define CSR_TSMBYTE1_LSB 0 +#define CSR_TSMBYTE1_MASK GENMASK_32(15, 0) +#define CSR_DTSMBDSTP_LSB 0 +#define CSR_DTSMBDSTP_MASK GENMASK_32(7, 0) +#define CSR_DTSMGDSTP_LSB 8 +#define CSR_DTSMGDSTP_MASK GENMASK_32(15, 8) +/* CSR_TSMBYTE2 */ +#define CSR_TSMBYTE2_LSB 0 +#define CSR_TSMBYTE2_MASK GENMASK_32(15, 0) +#define CSR_DTSMGDBAR_LSB 0 +#define CSR_DTSMGDBAR_MASK GENMASK_32(15, 0) +/* CSR_TSMBYTE3 */ +#define CSR_TSMBYTE3_LSB 0 +#define CSR_TSMBYTE3_MASK GENMASK_32(8, 0) +#define CSR_DTSMINCDECMODE_LSB 0 +#define CSR_DTSMINCDECMODE_MASK BIT(0) +#define CSR_DTSMINCDECCTRL_LSB 1 +#define CSR_DTSMINCDECCTRL_MASK BIT(1) +#define CSR_ENBLRXSAMPFLOPS_LSB 2 +#define CSR_ENBLRXSAMPFLOPS_MASK BIT(2) +#define CSR_SELRXSAMPFLOPS_LSB 3 +#define CSR_SELRXSAMPFLOPS_MASK BIT(3) +#define CSR_SELRXBYBASS_LSB 4 +#define CSR_SELRXBYBASS_MASK BIT(4) +#define CSR_DTSMIGNUPDATEACK_LSB 5 +#define CSR_DTSMIGNUPDATEACK_MASK BIT(5) +#define CSR_ENABLERXDQASYNC_LSB 6 +#define CSR_ENABLERXDQASYNC_MASK BIT(6) +#define CSR_DTSMSTATICCMPR_LSB 7 +#define CSR_DTSMSTATICCMPR_MASK BIT(7) +#define CSR_DTSMSTATICCMPRVAL_LSB 8 +#define CSR_DTSMSTATICCMPRVAL_MASK BIT(8) +/* CSR_TSMBYTE4 */ +#define CSR_TSMBYTE4_LSB 0 +#define CSR_TSMBYTE4_MASK GENMASK_32(3, 0) +#define CSR_DTSMINCDECPW_LSB 0 +#define CSR_DTSMINCDECPW_MASK GENMASK_32(3, 0) +/* CSR_TESTMODECONFIG */ +#define CSR_TESTMODECONFIG_LSB 0 +#define CSR_TESTMODECONFIG_MASK GENMASK_32(9, 0) +#define CSR_LOOPBACKEN_LSB 0 +#define CSR_LOOPBACKEN_MASK BIT(0) +#define CSR_RSVDTESTDLLEN_LSB 1 +#define CSR_RSVDTESTDLLEN_MASK BIT(1) +#define CSR_RSVDTWOTCKTXDQSPRE_LSB 2 +#define CSR_RSVDTWOTCKTXDQSPRE_MASK BIT(2) +#define CSR_TESTMODERSVD_LSB 3 +#define CSR_TESTMODERSVD_MASK GENMASK_32(7, 3) +#define CSR_LOOPBACKDISDQSTRI_LSB 8 +#define CSR_LOOPBACKDISDQSTRI_MASK BIT(8) +#define CSR_RSVDDISTXDQEQPREAMBLE_LSB 9 +#define CSR_RSVDDISTXDQEQPREAMBLE_MASK BIT(9) +/* CSR_TSMBYTE5 */ +#define CSR_TSMBYTE5_LSB 0 +#define CSR_TSMBYTE5_MASK GENMASK_32(15, 0) +#define CSR_DTSMBDBAR_LSB 0 +#define CSR_DTSMBDBAR_MASK GENMASK_32(15, 0) +/* MTESTMUXSEL already defined in ANIBx section */ +/* CSR_DTSMTRAINMODECTRL */ +#define CSR_DTSMTRAINMODECTRL_LSB 0 +#define CSR_DTSMTRAINMODECTRL_MASK GENMASK_32(3, 0) +#define CSR_DTSMSOELANEMODE_LSB 0 +#define CSR_DTSMSOELANEMODE_MASK GENMASK_32(1, 0) +#define CSR_DTSMBYTEERRANDMODE_LSB 2 +#define CSR_DTSMBYTEERRANDMODE_MASK BIT(2) +#define CSR_DTSMNIBERRMODE_LSB 3 +#define CSR_DTSMNIBERRMODE_MASK BIT(3) +/* CSR_DFIMRL */ +#define CSR_DFIMRL_LSB 0 +#define CSR_DFIMRL_MASK GENMASK_32(4, 0) +/* CSR_ASYNCDBYTEMODE */ +#define CSR_ASYNCDBYTEMODE_LSB 0 +#define CSR_ASYNCDBYTEMODE_MASK GENMASK_32(8, 0) +/* CSR_ASYNCDBYTETXEN */ +#define CSR_ASYNCDBYTETXEN_LSB 0 +#define CSR_ASYNCDBYTETXEN_MASK GENMASK_32(11, 0) +/* CSR_ASYNCDBYTETXDATA */ +#define CSR_ASYNCDBYTETXDATA_LSB 0 +#define CSR_ASYNCDBYTETXDATA_MASK GENMASK_32(11, 0) +/* CSR_ASYNCDBYTERXDATA */ +#define CSR_ASYNCDBYTERXDATA_LSB 0 +#define CSR_ASYNCDBYTERXDATA_MASK GENMASK_32(11, 0) +/* CSR_VREFDAC1 */ +#define CSR_VREFDAC1_LSB 0 +#define CSR_VREFDAC1_MASK GENMASK_32(6, 0) +/* CSR_TRAININGCNTR */ +#define CSR_TRAININGCNTR_LSB 0 +#define CSR_TRAININGCNTR_MASK GENMASK_32(15, 0) +#define CSR_TRAININGCNTRFINE_LSB 0 +#define CSR_TRAININGCNTRFINE_MASK GENMASK_32(9, 0) +#define CSR_TRAININGCNTRCOARSE_LSB 10 +#define CSR_TRAININGCNTRCOARSE_MASK GENMASK_32(15, 10) +/* CSR_VREFDAC0 */ +#define CSR_VREFDAC0_LSB 0 +#define CSR_VREFDAC0_MASK GENMASK_32(6, 0) +/* CSR_TXIMPEDANCECTRL0 */ +#define CSR_TXIMPEDANCECTRL0_LSB 0 +#define CSR_TXIMPEDANCECTRL0_MASK GENMASK_32(11, 0) +#define CSR_DRVSTRENDQP_LSB 0 +#define CSR_DRVSTRENDQP_MASK GENMASK_32(5, 0) +#define CSR_DRVSTRENDQN_LSB 6 +#define CSR_DRVSTRENDQN_MASK GENMASK_32(11, 6) +/* CSR_DQDQSRCVCNTRL */ +#define CSR_DQDQSRCVCNTRL_LSB 0 +#define CSR_DQDQSRCVCNTRL_MASK GENMASK_32(15, 0) +#define CSR_SELANALOGVREF_LSB 0 +#define CSR_SELANALOGVREF_MASK BIT(0) +#define CSR_EXTVREFRANGE_LSB 1 +#define CSR_EXTVREFRANGE_MASK BIT(1) +#define CSR_DFECTRL_LSB 2 +#define CSR_DFECTRL_MASK GENMASK_32(3, 2) +#define CSR_MAJORMODEDBYTE_LSB 4 +#define CSR_MAJORMODEDBYTE_MASK GENMASK_32(6, 4) +#define CSR_GAINCURRADJ_LSB 7 +#define CSR_GAINCURRADJ_MASK GENMASK_32(11, 7) +#define CSR_RESERVED_LSB 12 +#define CSR_RESERVED_MASK GENMASK_32(15, 12) +/* CSR_TXEQUALIZATIONMODE */ +#define CSR_TXEQUALIZATIONMODE_LSB 0 +#define CSR_TXEQUALIZATIONMODE_MASK GENMASK_32(1, 0) +#define CSR_TXEQMODE_LSB 0 +#define CSR_TXEQMODE_MASK GENMASK_32(1, 0) +/* CSR_TXIMPEDANCECTRL1 */ +#define CSR_TXIMPEDANCECTRL1_LSB 0 +#define CSR_TXIMPEDANCECTRL1_MASK GENMASK_32(11, 0) +#define CSR_DRVSTRENFSDQP_LSB 0 +#define CSR_DRVSTRENFSDQP_MASK GENMASK_32(5, 0) +#define CSR_DRVSTRENFSDQN_LSB 6 +#define CSR_DRVSTRENFSDQN_MASK GENMASK_32(11, 6) +/* CSR_DQDQSRCVCNTRL1 */ +#define CSR_DQDQSRCVCNTRL1_LSB 0 +#define CSR_DQDQSRCVCNTRL1_MASK GENMASK_32(11, 0) +#define CSR_POWERDOWNRCVR_LSB 0 +#define CSR_POWERDOWNRCVR_MASK GENMASK_32(8, 0) +#define CSR_POWERDOWNRCVRDQS_LSB 9 +#define CSR_POWERDOWNRCVRDQS_MASK BIT(9) +#define CSR_RXPADSTANDBYEN_LSB 10 +#define CSR_RXPADSTANDBYEN_MASK BIT(10) +#define CSR_ENLPREQPDR_LSB 11 +#define CSR_ENLPREQPDR_MASK BIT(11) +/* CSR_TXIMPEDANCECTRL2 */ +#define CSR_TXIMPEDANCECTRL2_LSB 0 +#define CSR_TXIMPEDANCECTRL2_MASK GENMASK_32(11, 0) +#define CSR_DRVSTRENEQHIDQP_LSB 0 +#define CSR_DRVSTRENEQHIDQP_MASK GENMASK_32(5, 0) +#define CSR_DRVSTRENEQLODQN_LSB 6 +#define CSR_DRVSTRENEQLODQN_MASK GENMASK_32(11, 6) +/* CSR_DQDQSRCVCNTRL2 */ +#define CSR_DQDQSRCVCNTRL2_LSB 0 +#define CSR_DQDQSRCVCNTRL2_MASK BIT(0) +#define CSR_ENRXAGRESSIVEPDR_LSB 0 +#define CSR_ENRXAGRESSIVEPDR_MASK BIT(0) +/* CSR_TXODTDRVSTREN */ +#define CSR_TXODTDRVSTREN_LSB 0 +#define CSR_TXODTDRVSTREN_MASK GENMASK_32(11, 0) +#define CSR_ODTSTRENP_LSB 0 +#define CSR_ODTSTRENP_MASK GENMASK_32(5, 0) +#define CSR_ODTSTRENN_LSB 6 +#define CSR_ODTSTRENN_MASK GENMASK_32(11, 6) +/* CSR_RXFIFOCHECKSTATUS */ +#define CSR_RXFIFOCHECKSTATUS_LSB 0 +#define CSR_RXFIFOCHECKSTATUS_MASK GENMASK_32(1, 0) +#define CSR_RXFIFOLOCERR_LSB 0 +#define CSR_RXFIFOLOCERR_MASK BIT(0) +#define CSR_RXFIFOLOCUERR_LSB 1 +#define CSR_RXFIFOLOCUERR_MASK BIT(1) +/* CSR_RXFIFOCHECKERRVALUES */ +#define CSR_RXFIFOCHECKERRVALUES_LSB 0 +#define CSR_RXFIFOCHECKERRVALUES_MASK GENMASK_32(15, 0) +#define CSR_RXFIFORDLOCERRVALUE_LSB 0 +#define CSR_RXFIFORDLOCERRVALUE_MASK GENMASK_32(3, 0) +#define CSR_RXFIFOWRLOCERRVALUE_LSB 4 +#define CSR_RXFIFOWRLOCERRVALUE_MASK GENMASK_32(7, 4) +#define CSR_RXFIFORDLOCUERRVALUE_LSB 8 +#define CSR_RXFIFORDLOCUERRVALUE_MASK GENMASK_32(11, 8) +#define CSR_RXFIFOWRLOCUERRVALUE_LSB 12 +#define CSR_RXFIFOWRLOCUERRVALUE_MASK GENMASK_32(15, 12) +/* CSR_RXFIFOINFO */ +#define CSR_RXFIFOINFO_LSB 0 +#define CSR_RXFIFOINFO_MASK GENMASK_32(15, 0) +#define CSR_RXFIFORDLOC_LSB 0 +#define CSR_RXFIFORDLOC_MASK GENMASK_32(3, 0) +#define CSR_RXFIFOWRLOC_LSB 4 +#define CSR_RXFIFOWRLOC_MASK GENMASK_32(7, 4) +#define CSR_RXFIFORDLOCU_LSB 8 +#define CSR_RXFIFORDLOCU_MASK GENMASK_32(11, 8) +#define CSR_RXFIFOWRLOCU_LSB 12 +#define CSR_RXFIFOWRLOCU_MASK GENMASK_32(15, 12) +/* CSR_RXFIFOVISIBILITY */ +#define CSR_RXFIFOVISIBILITY_LSB 0 +#define CSR_RXFIFOVISIBILITY_MASK GENMASK_32(4, 0) +#define CSR_RXFIFORDPTR_LSB 0 +#define CSR_RXFIFORDPTR_MASK GENMASK_32(2, 0) +#define CSR_RXFIFORDPTROVR_LSB 3 +#define CSR_RXFIFORDPTROVR_MASK BIT(3) +#define CSR_RXFIFORDEN_LSB 4 +#define CSR_RXFIFORDEN_MASK BIT(4) +/* CSR_RXFIFOCONTENTSDQ3210 */ +#define CSR_RXFIFOCONTENTSDQ3210_LSB 0 +#define CSR_RXFIFOCONTENTSDQ3210_MASK GENMASK_32(15, 0) +/* CSR_RXFIFOCONTENTSDQ7654 */ +#define CSR_RXFIFOCONTENTSDQ7654_LSB 0 +#define CSR_RXFIFOCONTENTSDQ7654_MASK GENMASK_32(15, 0) +/* CSR_RXFIFOCONTENTSDBI */ +#define CSR_RXFIFOCONTENTSDBI_LSB 0 +#define CSR_RXFIFOCONTENTSDBI_MASK GENMASK_32(3, 0) +/* CSR_TXSLEWRATE */ +#define CSR_TXSLEWRATE_LSB 0 +#define CSR_TXSLEWRATE_MASK GENMASK_32(10, 0) +#define CSR_TXPREP_LSB 0 +#define CSR_TXPREP_MASK GENMASK_32(3, 0) +#define CSR_TXPREN_LSB 4 +#define CSR_TXPREN_MASK GENMASK_32(7, 4) +#define CSR_TXPREDRVMODE_LSB 8 +#define CSR_TXPREDRVMODE_MASK GENMASK_32(10, 8) +/* CSR_TRAININGINCDECDTSMEN */ +#define CSR_TRAININGINCDECDTSMEN_LSB 0 +#define CSR_TRAININGINCDECDTSMEN_MASK GENMASK_32(8, 0) +/* CSR_RXPBDLYTG0 */ +#define CSR_RXPBDLYTG0_LSB 0 +#define CSR_RXPBDLYTG0_MASK GENMASK_32(6, 0) +/* CSR_RXPBDLYTG1 */ +#define CSR_RXPBDLYTG1_LSB 0 +#define CSR_RXPBDLYTG1_MASK GENMASK_32(6, 0) +/* CSR_RXPBDLYTG2 */ +#define CSR_RXPBDLYTG2_LSB 0 +#define CSR_RXPBDLYTG2_MASK GENMASK_32(6, 0) +/* CSR_RXPBDLYTG3 */ +#define CSR_RXPBDLYTG3_LSB 0 +#define CSR_RXPBDLYTG3_MASK GENMASK_32(6, 0) +/* CSR_RXENDLYTG0 */ +#define CSR_RXENDLYTG0_LSB 0 +#define CSR_RXENDLYTG0_MASK GENMASK_32(10, 0) +/* CSR_RXENDLYTG1 */ +#define CSR_RXENDLYTG1_LSB 0 +#define CSR_RXENDLYTG1_MASK GENMASK_32(10, 0) +/* CSR_RXENDLYTG2 */ +#define CSR_RXENDLYTG2_LSB 0 +#define CSR_RXENDLYTG2_MASK GENMASK_32(10, 0) +/* CSR_RXENDLYTG3 */ +#define CSR_RXENDLYTG3_LSB 0 +#define CSR_RXENDLYTG3_MASK GENMASK_32(10, 0) +/* CSR_RXCLKDLYTG0 */ +#define CSR_RXCLKDLYTG0_LSB 0 +#define CSR_RXCLKDLYTG0_MASK GENMASK_32(5, 0) +/* CSR_RXCLKDLYTG1 */ +#define CSR_RXCLKDLYTG1_LSB 0 +#define CSR_RXCLKDLYTG1_MASK GENMASK_32(5, 0) +/* CSR_RXCLKDLYTG2 */ +#define CSR_RXCLKDLYTG2_LSB 0 +#define CSR_RXCLKDLYTG2_MASK GENMASK_32(5, 0) +/* CSR_RXCLKDLYTG3 */ +#define CSR_RXCLKDLYTG3_LSB 0 +#define CSR_RXCLKDLYTG3_MASK GENMASK_32(5, 0) +/* CSR_RXCLKCDLYTG0 */ +#define CSR_RXCLKCDLYTG0_LSB 0 +#define CSR_RXCLKCDLYTG0_MASK GENMASK_32(5, 0) +/* CSR_RXCLKCDLYTG1 */ +#define CSR_RXCLKCDLYTG1_LSB 0 +#define CSR_RXCLKCDLYTG1_MASK GENMASK_32(5, 0) +/* CSR_RXCLKCDLYTG2 */ +#define CSR_RXCLKCDLYTG2_LSB 0 +#define CSR_RXCLKCDLYTG2_MASK GENMASK_32(5, 0) +/* CSR_RXCLKCDLYTG3 */ +#define CSR_RXCLKCDLYTG3_LSB 0 +#define CSR_RXCLKCDLYTG3_MASK GENMASK_32(5, 0) +/* CSR_DQ0LNSEL */ +#define CSR_DQ0LNSEL_LSB 0 +#define CSR_DQ0LNSEL_MASK GENMASK_32(2, 0) +/* CSR_DQ1LNSEL */ +#define CSR_DQ1LNSEL_LSB 0 +#define CSR_DQ1LNSEL_MASK GENMASK_32(2, 0) +/* CSR_DQ2LNSEL */ +#define CSR_DQ2LNSEL_LSB 0 +#define CSR_DQ2LNSEL_MASK GENMASK_32(2, 0) +/* CSR_DQ3LNSEL */ +#define CSR_DQ3LNSEL_LSB 0 +#define CSR_DQ3LNSEL_MASK GENMASK_32(2, 0) +/* CSR_DQ4LNSEL */ +#define CSR_DQ4LNSEL_LSB 0 +#define CSR_DQ4LNSEL_MASK GENMASK_32(2, 0) +/* CSR_DQ5LNSEL */ +#define CSR_DQ5LNSEL_LSB 0 +#define CSR_DQ5LNSEL_MASK GENMASK_32(2, 0) +/* CSR_DQ6LNSEL */ +#define CSR_DQ6LNSEL_LSB 0 +#define CSR_DQ6LNSEL_MASK GENMASK_32(2, 0) +/* CSR_DQ7LNSEL */ +#define CSR_DQ7LNSEL_LSB 0 +#define CSR_DQ7LNSEL_MASK GENMASK_32(2, 0) +/* CSR_PPTCTLSTATIC */ +#define CSR_PPTCTLSTATIC_LSB 0 +#define CSR_PPTCTLSTATIC_MASK GENMASK_32(11, 0) +#define CSR_PPTENDQS2DQTG0_LSB 0 +#define CSR_PPTENDQS2DQTG0_MASK BIT(0) +#define CSR_PPTENDQS2DQTG1_LSB 1 +#define CSR_PPTENDQS2DQTG1_MASK BIT(1) +#define CSR_DOCBYTESELTG0_LSB 2 +#define CSR_DOCBYTESELTG0_MASK BIT(2) +#define CSR_DOCBYTESELTG1_LSB 3 +#define CSR_DOCBYTESELTG1_MASK BIT(3) +#define CSR_PPTINFOSEL_LSB 4 +#define CSR_PPTINFOSEL_MASK GENMASK_32(7, 4) +#define CSR_PPTENRXENDLYTG0_LSB 8 +#define CSR_PPTENRXENDLYTG0_MASK BIT(8) +#define CSR_PPTENRXENDLYTG1_LSB 9 +#define CSR_PPTENRXENDLYTG1_MASK BIT(9) +#define CSR_PPTENRXENBACKOFF_LSB 10 +#define CSR_PPTENRXENBACKOFF_MASK GENMASK_32(11, 10) +/* CSR_PPTCTLDYN */ +#define CSR_PPTCTLDYN_LSB 0 +#define CSR_PPTCTLDYN_MASK GENMASK_32(1, 0) +#define CSR_PPTDQS2DQACTIVE_LSB 0 +#define CSR_PPTDQS2DQACTIVE_MASK BIT(0) +#define CSR_PPTENRXENUSEDQSSAMPVAL_LSB 1 +#define CSR_PPTENRXENUSEDQSSAMPVAL_MASK BIT(1) +/* CSR_PPTINFO */ +#define CSR_PPTINFO_LSB 0 +#define CSR_PPTINFO_MASK GENMASK_32(15, 0) +/* CSR_PPTRXENEVNT */ +#define CSR_PPTRXENEVNT_LSB 0 +#define CSR_PPTRXENEVNT_MASK GENMASK_32(1, 0) +#define CSR_PPTRXENINIT_LSB 0 +#define CSR_PPTRXENINIT_MASK BIT(0) +#define CSR_PPTRXENMHUI_LSB 1 +#define CSR_PPTRXENMHUI_MASK BIT(1) +/* CSR_PPTDQSCNTINVTRNTG0 */ +#define CSR_PPTDQSCNTINVTRNTG0_LSB 0 +#define CSR_PPTDQSCNTINVTRNTG0_MASK GENMASK_32(15, 0) +/* CSR_PPTDQSCNTINVTRNTG1 */ +#define CSR_PPTDQSCNTINVTRNTG1_LSB 0 +#define CSR_PPTDQSCNTINVTRNTG1_MASK GENMASK_32(15, 0) +/* CSR_DTSMBLANKINGCTRL */ +#define CSR_DTSMBLANKINGCTRL_LSB 0 +#define CSR_DTSMBLANKINGCTRL_MASK GENMASK_32(9, 0) +#define CSR_DTSMBLANK_LSB 0 +#define CSR_DTSMBLANK_MASK GENMASK_32(9, 0) +/* CSR_TSM0 */ +#define CSR_TSM0_LSB 0 +#define CSR_TSM0_MASK GENMASK_32(13, 0) +#define CSR_DTSMENB_LSB 0 +#define CSR_DTSMENB_MASK BIT(0) +#define CSR_DTSMDIR_LSB 1 +#define CSR_DTSMDIR_MASK BIT(1) +#define CSR_DTSMIGNFRST_LSB 2 +#define CSR_DTSMIGNFRST_MASK BIT(2) +#define CSR_DTSMODDPHASE_LSB 3 +#define CSR_DTSMODDPHASE_MASK BIT(3) +#define CSR_DTSMFLTPRE_LSB 4 +#define CSR_DTSMFLTPRE_MASK BIT(4) +#define CSR_DTSMFLTCUR_LSB 5 +#define CSR_DTSMFLTCUR_MASK BIT(5) +#define CSR_DTSMFLTNXT_LSB 6 +#define CSR_DTSMFLTNXT_MASK BIT(6) +#define CSR_DTSMFLTVAL_LSB 7 +#define CSR_DTSMFLTVAL_MASK GENMASK_32(9, 7) +#define CSR_DTSMMSKBIT_LSB 10 +#define CSR_DTSMMSKBIT_MASK GENMASK_32(13, 10) +/* CSR_TSM1 */ +#define CSR_TSM1_LSB 0 +#define CSR_TSM1_MASK GENMASK_32(15, 0) +#define CSR_DTSMERRCNT_LSB 0 +#define CSR_DTSMERRCNT_MASK GENMASK_32(15, 0) +/* CSR_TSM2 */ +#define CSR_TSM2_LSB 0 +#define CSR_TSM2_MASK BIT(0) +#define CSR_DTSMDISERRCHK_LSB 0 +#define CSR_DTSMDISERRCHK_MASK BIT(0) +/* CSR_TSM3 */ +#define CSR_TSM3_LSB 0 +#define CSR_TSM3_MASK GENMASK_32(9, 0) +#define CSR_DTSMCLRERRCNTMSK_LSB 0 +#define CSR_DTSMCLRERRCNTMSK_MASK GENMASK_32(8, 0) +#define CSR_DTSMCLRERRCNT_LSB 9 +#define CSR_DTSMCLRERRCNT_MASK BIT(9) +/* CSR_TXCHKDATASELECTS */ +#define CSR_TXCHKDATASELECTS_LSB 0 +#define CSR_TXCHKDATASELECTS_MASK GENMASK_32(1, 0) +#define CSR_SELCHKTOTX_LSB 0 +#define CSR_SELCHKTOTX_MASK BIT(0) +#define CSR_SELTXTOCHK_LSB 1 +#define CSR_SELTXTOCHK_MASK BIT(1) +/* CSR_DTSMUPTHLDXINGIND */ +#define CSR_DTSMUPTHLDXINGIND_LSB 0 +#define CSR_DTSMUPTHLDXINGIND_MASK GENMASK_32(8, 0) +/* CSR_DTSMLOTHLDXINGIND */ +#define CSR_DTSMLOTHLDXINGIND_LSB 0 +#define CSR_DTSMLOTHLDXINGIND_MASK GENMASK_32(8, 0) +/* CSR_DBYTEALLDTSMCTRL0 */ +#define CSR_DBYTEALLDTSMCTRL0_LSB 0 +#define CSR_DBYTEALLDTSMCTRL0_MASK GENMASK_32(8, 0) +#define CSR_DTSMINHIBDTSM_LSB 0 +#define CSR_DTSMINHIBDTSM_MASK GENMASK_32(8, 0) +/* CSR_DBYTEALLDTSMCTRL1 */ +#define CSR_DBYTEALLDTSMCTRL1_LSB 0 +#define CSR_DBYTEALLDTSMCTRL1_MASK GENMASK_32(8, 0) +#define CSR_DTSMGATEINC_LSB 0 +#define CSR_DTSMGATEINC_MASK GENMASK_32(8, 0) +/* CSR_DBYTEALLDTSMCTRL2 */ +#define CSR_DBYTEALLDTSMCTRL2_LSB 0 +#define CSR_DBYTEALLDTSMCTRL2_MASK GENMASK_32(8, 0) +#define CSR_DTSMGATEDEC_LSB 0 +#define CSR_DTSMGATEDEC_MASK GENMASK_32(8, 0) +/* CSR_TXDQDLYTG0 */ +#define CSR_TXDQDLYTG0_LSB 0 +#define CSR_TXDQDLYTG0_MASK GENMASK_32(8, 0) +/* CSR_TXDQDLYTG1 */ +#define CSR_TXDQDLYTG1_LSB 0 +#define CSR_TXDQDLYTG1_MASK GENMASK_32(8, 0) +/* CSR_TXDQDLYTG2 */ +#define CSR_TXDQDLYTG2_LSB 0 +#define CSR_TXDQDLYTG2_MASK GENMASK_32(8, 0) +/* CSR_TXDQDLYTG3 */ +#define CSR_TXDQDLYTG3_LSB 0 +#define CSR_TXDQDLYTG3_MASK GENMASK_32(8, 0) +/* CSR_TXDQSDLYTG0 */ +#define CSR_TXDQSDLYTG0_LSB 0 +#define CSR_TXDQSDLYTG0_MASK GENMASK_32(9, 0) +/* CSR_TXDQSDLYTG1 */ +#define CSR_TXDQSDLYTG1_LSB 0 +#define CSR_TXDQSDLYTG1_MASK GENMASK_32(9, 0) +/* CSR_TXDQSDLYTG2 */ +#define CSR_TXDQSDLYTG2_LSB 0 +#define CSR_TXDQSDLYTG2_MASK GENMASK_32(9, 0) +/* CSR_TXDQSDLYTG3 */ +#define CSR_TXDQSDLYTG3_LSB 0 +#define CSR_TXDQSDLYTG3_MASK GENMASK_32(9, 0) +/* CSR_DXLCDLSTATUS_ADDR */ +#define CSR_DXLCDLSTATUS_LSB 0 +#define CSR_DXLCDLSTATUS_MASK GENMASK_32(13, 0) +#define CSR_DXLCDLFINESNAPVAL_LSB 0 +#define CSR_DXLCDLFINESNAPVAL_MASK GENMASK_32(9, 0) +#define CSR_DXLCDLPHDSNAPVAL_LSB 10 +#define CSR_DXLCDLPHDSNAPVAL_MASK BIT(10) +#define CSR_DXLCDLSTICKYLOCK_LSB 11 +#define CSR_DXLCDLSTICKYLOCK_MASK BIT(11) +#define CSR_DXLCDLSTICKYUNLOCK_LSB 12 +#define CSR_DXLCDLSTICKYUNLOCK_MASK BIT(12) +#define CSR_DXLCDLLIVELOCK_LSB 13 +#define CSR_DXLCDLLIVELOCK_MASK BIT(13) + +/* MASTER0 register offsets */ +/* CSR_RXFIFOINIT */ +#define CSR_RXFIFOINIT_LSB 0 +#define CSR_RXFIFOINIT_MASK GENMASK_32(1, 0) +#define CSR_RXFIFOINITPTR_LSB 0 +#define CSR_RXFIFOINITPTR_MASK BIT(0) +#define CSR_INHIBITRXFIFORD_LSB 1 +#define CSR_INHIBITRXFIFORD_MASK BIT(1) +/* CSR_FORCECLKDISABLE */ +#define CSR_FORCECLKDISABLE_LSB 0 +#define CSR_FORCECLKDISABLE_MASK GENMASK_32(3, 0) +/* CSR_CLOCKINGCTRL */ +#define CSR_CLOCKINGCTRL_LSB 0 +#define CSR_CLOCKINGCTRL_MASK GENMASK_32(1, 0) +#define CSR_PCLKENASYNCCTRL_LSB 0 +#define CSR_PCLKENASYNCCTRL_MASK BIT(0) +#define CSR_DLLTRACKENCTRL_LSB 1 +#define CSR_DLLTRACKENCTRL_MASK BIT(1) +/* CSR_FORCEINTERNALUPDATE */ +#define CSR_FORCEINTERNALUPDATE_LSB 0 +#define CSR_FORCEINTERNALUPDATE_MASK BIT(0) +/* CSR_PHYCONFIG */ +#define CSR_PHYCONFIG_LSB 0 +#define CSR_PHYCONFIG_MASK GENMASK_32(9, 0) +#define CSR_PHYCONFIGANIBS_LSB 0 +#define CSR_PHYCONFIGANIBS_MASK GENMASK_32(3, 0) +#define CSR_PHYCONFIGDBYTES_LSB 4 +#define CSR_PHYCONFIGDBYTES_MASK GENMASK_32(7, 4) +#define CSR_PHYCONFIGDFI_LSB 8 +#define CSR_PHYCONFIGDFI_MASK GENMASK_32(9, 8) +/* CSR_PGCR */ +#define CSR_PGCR_LSB 0 +#define CSR_PGCR_MASK BIT(0) +#define CSR_RXCLKRISEFALLMODE_LSB 0 +#define CSR_RXCLKRISEFALLMODE_MASK BIT(0) +/* CSR_TESTBUMPCNTRL1 */ +#define CSR_TESTBUMPCNTRL1_LSB 0 +#define CSR_TESTBUMPCNTRL1_MASK GENMASK_32(15, 0) +#define CSR_TESTMAJORMODE_LSB 0 +#define CSR_TESTMAJORMODE_MASK GENMASK_32(2, 0) +#define CSR_TESTBIASBYPASSEN_LSB 3 +#define CSR_TESTBIASBYPASSEN_MASK BIT(3) +#define CSR_TESTANALOGOUTCTRL_LSB 4 +#define CSR_TESTANALOGOUTCTRL_MASK GENMASK_32(7, 4) +#define CSR_TESTGAINCURRADJ_LSB 8 +#define CSR_TESTGAINCURRADJ_MASK GENMASK_32(12, 8) +#define CSR_TESTSELEXTERNALVREF_LSB 13 +#define CSR_TESTSELEXTERNALVREF_MASK BIT(13) +#define CSR_TESTEXTVREFRANGE_LSB 14 +#define CSR_TESTEXTVREFRANGE_MASK BIT(14) +#define CSR_TESTPOWERGATEEN_LSB 15 +#define CSR_TESTPOWERGATEEN_MASK BIT(15) +/* CSR_CALUCLKINFO */ +#define CSR_CALUCLKINFO_LSB 0 +#define CSR_CALUCLKINFO_MASK GENMASK_32(10, 0) +#define CSR_CALUCLKTICKSPER1US_LSB 0 +#define CSR_CALUCLKTICKSPER1US_MASK GENMASK_32(10, 0) +/* CSR_TESTBUMPCNTRL */ +#define CSR_TESTBUMPCNTRL_LSB 0 +#define CSR_TESTBUMPCNTRL_MASK GENMASK_32(9, 0) +#define CSR_TESTBUMPEN_LSB 0 +#define CSR_TESTBUMPEN_MASK GENMASK_32(1, 0) +#define CSR_TESTBUMPTOGGLE_LSB 2 +#define CSR_TESTBUMPTOGGLE_MASK BIT(2) +#define CSR_TESTBUMPDATASEL_LSB 3 +#define CSR_TESTBUMPDATASEL_MASK GENMASK_32(8, 3) +#define CSR_FORCEMTESTONALERT_LSB 9 +#define CSR_FORCEMTESTONALERT_MASK BIT(9) +/* CSR_SEQ0BDLY0 */ +#define CSR_SEQ0BDLY0_LSB 0 +#define CSR_SEQ0BDLY0_MASK GENMASK_32(15, 0) +/* CSR_SEQ0BDLY1 */ +#define CSR_SEQ0BDLY1_LSB 0 +#define CSR_SEQ0BDLY1_MASK GENMASK_32(15, 0) +/* CSR_SEQ0BDLY2 */ +#define CSR_SEQ0BDLY2_LSB 0 +#define CSR_SEQ0BDLY2_MASK GENMASK_32(15, 0) +/* CSR_SEQ0BDLY3 */ +#define CSR_SEQ0BDLY3_LSB 0 +#define CSR_SEQ0BDLY3_MASK GENMASK_32(15, 0) +/* CSR_PHYALERTSTATUS */ +#define CSR_PHYALERTSTATUS_LSB 0 +#define CSR_PHYALERTSTATUS_MASK BIT(0) +#define CSR_PHYALERT_LSB 0 +#define CSR_PHYALERT_MASK BIT(0) +/* CSR_PPTTRAINSETUP */ +#define CSR_PPTTRAINSETUP_LSB 0 +#define CSR_PPTTRAINSETUP_MASK GENMASK_32(6, 0) +#define CSR_PHYMSTRTRAININTERVAL_LSB 0 +#define CSR_PHYMSTRTRAININTERVAL_MASK GENMASK_32(3, 0) +#define CSR_PHYMSTRMAXREQTOACK_LSB 4 +#define CSR_PHYMSTRMAXREQTOACK_MASK GENMASK_32(6, 4) +/* CSR_PPTTRAINSETUP2 */ +#define CSR_PPTTRAINSETUP2_LSB 0 +#define CSR_PPTTRAINSETUP2_MASK GENMASK_32(2, 0) +#define CSR_PHYMSTRFREQOVERRIDE_LSB 0 +#define CSR_PHYMSTRFREQOVERRIDE_MASK GENMASK_32(2, 0) +/* CSR_ATESTMODE */ +#define CSR_ATESTMODE_LSB 0 +#define CSR_ATESTMODE_MASK GENMASK_32(4, 0) +#define CSR_ATESTPRBSEN_LSB 0 +#define CSR_ATESTPRBSEN_MASK BIT(0) +#define CSR_ATESTCLKEN_LSB 1 +#define CSR_ATESTCLKEN_MASK BIT(1) +#define CSR_ATESTMODESEL_LSB 2 +#define CSR_ATESTMODESEL_MASK GENMASK_32(4, 2) +/* CSR_TXCALBINP */ +#define CSR_TXCALBINP_LSB 0 +#define CSR_TXCALBINP_MASK GENMASK_32(4, 0) +/* CSR_TXCALBINN */ +#define CSR_TXCALBINN_LSB 0 +#define CSR_TXCALBINN_MASK GENMASK_32(4, 0) +/* CSR_TXCALPOVR */ +#define CSR_TXCALPOVR_LSB 0 +#define CSR_TXCALPOVR_MASK GENMASK_32(5, 0) +#define CSR_TXCALBINPOVRVAL_LSB 0 +#define CSR_TXCALBINPOVRVAL_MASK GENMASK_32(4, 0) +#define CSR_TXCALBINPOVREN_LSB 5 +#define CSR_TXCALBINPOVREN_MASK BIT(5) +/* CSR_TXCALNOVR */ +#define CSR_TXCALNOVR_LSB 0 +#define CSR_TXCALNOVR_MASK GENMASK_32(5, 0) +#define CSR_TXCALBINNOVRVAL_LSB 0 +#define CSR_TXCALBINNOVRVAL_MASK GENMASK_32(4, 0) +#define CSR_TXCALBINNOVREN_LSB 5 +#define CSR_TXCALBINNOVREN_MASK BIT(5) +/* CSR_DFIMODE */ +#define CSR_DFIMODE_LSB 0 +#define CSR_DFIMODE_MASK GENMASK_32(2, 0) +#define CSR_DFI0ENABLE_LSB 0 +#define CSR_DFI0ENABLE_MASK BIT(0) +#define CSR_DFI1ENABLE_LSB 1 +#define CSR_DFI1ENABLE_MASK BIT(1) +#define CSR_DFI1OVERRIDE_LSB 2 +#define CSR_DFI1OVERRIDE_MASK BIT(2) +/* CSR_TRISTATEMODECA */ +#define CSR_TRISTATEMODECA_LSB 0 +#define CSR_TRISTATEMODECA_MASK GENMASK_32(3, 0) +#define CSR_DISDYNADRTRI_LSB 0 +#define CSR_DISDYNADRTRI_MASK BIT(0) +#define CSR_DDR2TMODE_LSB 1 +#define CSR_DDR2TMODE_MASK BIT(1) +#define CSR_CKDISVAL_LSB 2 +#define CSR_CKDISVAL_MASK GENMASK_32(3, 2) +/* MTESTMUXSEL already defined in ANIBx section */ +/* CSR_MTESTPGMINFO */ +#define CSR_MTESTPGMINFO_LSB 0 +#define CSR_MTESTPGMINFO_MASK BIT(0) +/* CSR_DYNPWRDNUP */ +#define CSR_DYNPWRDNUP_LSB 0 +#define CSR_DYNPWRDNUP_MASK BIT(0) +#define CSR_DYNPOWERDOWN_LSB 0 +#define CSR_DYNPOWERDOWN_MASK BIT(0) +/* CSR_PMIENABLE */ +#define CSR_PMIENABLE_LSB 0 +#define CSR_PMIENABLE_MASK BIT(0) +/* CSR_PHYTID */ +#define CSR_PHYTID_LSB 0 +#define CSR_PHYTID_MASK GENMASK_32(15, 0) +/* CSR_HWTMRL */ +#define CSR_HWTMRL_LSB 0 +#define CSR_HWTMRL_MASK GENMASK_32(4, 0) +/* CSR_DFIPHYUPD */ +#define CSR_DFIPHYUPD_LSB 0 +#define CSR_DFIPHYUPD_MASK GENMASK_32(15, 0) +#define CSR_DFIPHYUPDCNT_LSB 0 +#define CSR_DFIPHYUPDCNT_MASK GENMASK_32(3, 0) +#define CSR_DFIPHYUPDRESP_LSB 4 +#define CSR_DFIPHYUPDRESP_MASK GENMASK_32(6, 4) +#define CSR_DFIPHYUPDMODE_LSB 7 +#define CSR_DFIPHYUPDMODE_MASK BIT(7) +#define CSR_DFIPHYUPDTHRESHOLD_LSB 8 +#define CSR_DFIPHYUPDTHRESHOLD_MASK GENMASK_32(11, 8) +#define CSR_DFIPHYUPDINTTHRESHOLD_LSB 12 +#define CSR_DFIPHYUPDINTTHRESHOLD_MASK GENMASK_32(15, 12) +/* CSR_PDAMRSWRITEMODE */ +#define CSR_PDAMRSWRITEMODE_LSB 0 +#define CSR_PDAMRSWRITEMODE_MASK BIT(0) +/* CSR_DFIGEARDOWNCTL */ +#define CSR_DFIGEARDOWNCTL_LSB 0 +#define CSR_DFIGEARDOWNCTL_MASK GENMASK_32(1, 0) +/* CSR_DQSPREAMBLECONTROL */ +#define CSR_DQSPREAMBLECONTROL_LSB 0 +#define CSR_DQSPREAMBLECONTROL_MASK GENMASK_32(8, 0) +#define CSR_TWOTCKRXDQSPRE_LSB 0 +#define CSR_TWOTCKRXDQSPRE_MASK BIT(0) +#define CSR_TWOTCKTXDQSPRE_LSB 1 +#define CSR_TWOTCKTXDQSPRE_MASK BIT(1) +#define CSR_POSITIONDFEINIT_LSB 2 +#define CSR_POSITIONDFEINIT_MASK GENMASK_32(4, 2) +#define CSR_LP4TGLTWOTCKTXDQSPRE_LSB 5 +#define CSR_LP4TGLTWOTCKTXDQSPRE_MASK BIT(5) +#define CSR_LP4POSTAMBLEEXT_LSB 6 +#define CSR_LP4POSTAMBLEEXT_MASK BIT(6) +#define CSR_LP4STTCPREBRIDGERXEN_LSB 7 +#define CSR_LP4STTCPREBRIDGERXEN_MASK BIT(7) +#define CSR_WDQSEXTENSION_LSB 8 +#define CSR_WDQSEXTENSION_MASK BIT(8) +/* CSR_MASTERX4CONFIG */ +#define CSR_MASTERX4CONFIG_LSB 0 +#define CSR_MASTERX4CONFIG_MASK GENMASK_32(3, 0) +#define CSR_X4TG_LSB 0 +#define CSR_X4TG_MASK GENMASK_32(3, 0) +/* CSR_WRLEVBITS */ +#define CSR_WRLEVBITS_LSB 0 +#define CSR_WRLEVBITS_MASK GENMASK_32(7, 0) +#define CSR_WRLEVFORDQSL_LSB 0 +#define CSR_WRLEVFORDQSL_MASK GENMASK_32(3, 0) +#define CSR_WRLEVFORDQSU_LSB 4 +#define CSR_WRLEVFORDQSU_MASK GENMASK_32(7, 4) +/* CSR_ENABLECSMULTICAST */ +#define CSR_ENABLECSMULTICAST_LSB 0 +#define CSR_ENABLECSMULTICAST_MASK BIT(0) +/* CSR_HWTLPCSMULTICAST */ +#define CSR_HWTLPCSMULTICAST_LSB 0 +#define CSR_HWTLPCSMULTICAST_MASK BIT(0) +/* CSR_ACX4ANIBDIS */ +#define CSR_ACX4ANIBDIS_LSB 0 +#define CSR_ACX4ANIBDIS_MASK GENMASK_32(11, 0) +/* CSR_DMIPINPRESENT */ +#define CSR_DMIPINPRESENT_LSB 0 +#define CSR_DMIPINPRESENT_MASK BIT(0) +#define CSR_RDDBIENABLED_LSB 0 +#define CSR_RDDBIENABLED_MASK BIT(0) +/* CSR_ARDPTRINITVAL */ +#define CSR_ARDPTRINITVAL_LSB 0 +#define CSR_ARDPTRINITVAL_MASK GENMASK_32(3, 0) +/* CSR_DB0LCDLCALPHDETOUT */ +#define CSR_DB0LCDLCALPHDETOUT_LSB 0 +#define CSR_DB0LCDLCALPHDETOUT_MASK GENMASK_32(15, 0) +/* CSR_DB1LCDLCALPHDETOUT */ +#define CSR_DB1LCDLCALPHDETOUT_LSB 0 +#define CSR_DB1LCDLCALPHDETOUT_MASK GENMASK_32(15, 0) +/* CSR_DB2LCDLCALPHDETOUT */ +#define CSR_DB2LCDLCALPHDETOUT_LSB 0 +#define CSR_DB2LCDLCALPHDETOUT_MASK GENMASK_32(15, 0) +/* CSR_DB3LCDLCALPHDETOUT */ +#define CSR_DB3LCDLCALPHDETOUT_LSB 0 +#define CSR_DB3LCDLCALPHDETOUT_MASK GENMASK_32(15, 0) +/* CSR_DB4LCDLCALPHDETOUT */ +#define CSR_DB4LCDLCALPHDETOUT_LSB 0 +#define CSR_DB4LCDLCALPHDETOUT_MASK GENMASK_32(15, 0) +/* CSR_DB5LCDLCALPHDETOUT */ +#define CSR_DB5LCDLCALPHDETOUT_LSB 0 +#define CSR_DB5LCDLCALPHDETOUT_MASK GENMASK_32(15, 0) +/* CSR_DB6LCDLCALPHDETOUT */ +#define CSR_DB6LCDLCALPHDETOUT_LSB 0 +#define CSR_DB6LCDLCALPHDETOUT_MASK GENMASK_32(15, 0) +/* CSR_DB7LCDLCALPHDETOUT */ +#define CSR_DB7LCDLCALPHDETOUT_LSB 0 +#define CSR_DB7LCDLCALPHDETOUT_MASK GENMASK_32(15, 0) +/* CSR_DB8LCDLCALPHDETOUT */ +#define CSR_DB8LCDLCALPHDETOUT_LSB 0 +#define CSR_DB8LCDLCALPHDETOUT_MASK GENMASK_32(15, 0) +/* CSR_DB9LCDLCALPHDETOUT */ +#define CSR_DB9LCDLCALPHDETOUT_LSB 0 +#define CSR_DB9LCDLCALPHDETOUT_MASK GENMASK_32(15, 0) +/* CSR_DBYTEDLLMODECNTRL */ +#define CSR_DBYTEDLLMODECNTRL_LSB 1 +#define CSR_DBYTEDLLMODECNTRL_MASK BIT(1) +#define CSR_DLLRXPREAMBLEMODE_LSB 1 +#define CSR_DLLRXPREAMBLEMODE_MASK BIT(1) +/* CSR_DBYTERXENTRAIN */ +#define CSR_DBYTERXENTRAIN_LSB 0 +#define CSR_DBYTERXENTRAIN_MASK BIT(0) +#define CSR_RXENTRAIN_LSB 0 +#define CSR_RXENTRAIN_MASK BIT(0) +/* CSR_ANLCDLCALPHDETOUT */ +#define CSR_ANLCDLCALPHDETOUT_LSB 0 +#define CSR_ANLCDLCALPHDETOUT_MASK GENMASK_32(11, 0) +/* CSR_CALOFFSETS */ +#define CSR_CALOFFSETS_LSB 0 +#define CSR_CALOFFSETS_MASK GENMASK_32(13, 0) +#define CSR_CALCMPR5OFFSET_LSB 0 +#define CSR_CALCMPR5OFFSET_MASK GENMASK_32(5, 0) +#define CSR_CALDRVPDTHOFFSET_LSB 6 +#define CSR_CALDRVPDTHOFFSET_MASK GENMASK_32(9, 6) +#define CSR_CALDRVPUTHOFFSET_LSB 10 +#define CSR_CALDRVPUTHOFFSET_MASK GENMASK_32(13, 10) +/* CSR_SARINITVALS */ +#define CSR_SARINITVALS_LSB 0 +#define CSR_SARINITVALS_MASK GENMASK_32(8, 0) +#define CSR_SARINITOFFSET05_LSB 0 +#define CSR_SARINITOFFSET05_MASK GENMASK_32(2, 0) +#define CSR_SARINITNINT_LSB 3 +#define CSR_SARINITNINT_MASK GENMASK_32(5, 3) +#define CSR_SARINITPEXT_LSB 6 +#define CSR_SARINITPEXT_MASK GENMASK_32(8, 6) +/* CSR_CALPEXTOVR */ +#define CSR_CALPEXTOVR_LSB 0 +#define CSR_CALPEXTOVR_MASK GENMASK_32(4, 0) +/* CSR_CALCMPR5OVR */ +#define CSR_CALCMPR5OVR_LSB 0 +#define CSR_CALCMPR5OVR_MASK GENMASK_32(7, 0) +/* CSR_CALNINTOVR */ +#define CSR_CALNINTOVR_LSB 0 +#define CSR_CALNINTOVR_MASK GENMASK_32(4, 0) +/* CSR_CALDRVSTR0 */ +#define CSR_CALDRVSTR0_LSB 0 +#define CSR_CALDRVSTR0_MASK GENMASK_32(7, 0) +#define CSR_CALDRVSTRPD50_LSB 0 +#define CSR_CALDRVSTRPD50_MASK GENMASK_32(3, 0) +#define CSR_CALDRVSTRPU50_LSB 4 +#define CSR_CALDRVSTRPU50_MASK GENMASK_32(7, 4) +/* CSR_PROCODTCTL */ +#define CSR_PROCODTCTL_LSB 0 +#define CSR_PROCODTCTL_MASK GENMASK_32(1, 0) +#define CSR_PROCODTALWAYSOFF_LSB 0 +#define CSR_PROCODTALWAYSOFF_MASK BIT(0) +#define CSR_PROCODTALWAYSON_LSB 1 +#define CSR_PROCODTALWAYSON_MASK BIT(1) +/* CSR_PROCODTTIMECTL */ +#define CSR_PROCODTTIMECTL_LSB 0 +#define CSR_PROCODTTIMECTL_MASK GENMASK_32(5, 0) +#define CSR_PODTTAILWIDTH_LSB 0 +#define CSR_PODTTAILWIDTH_MASK GENMASK_32(1, 0) +#define CSR_PODTSTARTDELAY_LSB 2 +#define CSR_PODTSTARTDELAY_MASK GENMASK_32(3, 2) +#define CSR_PODTTAILWIDTHEXT_LSB 4 +#define CSR_PODTTAILWIDTHEXT_MASK GENMASK_32(5, 4) +/* CSR_MEMALERTCONTROL */ +#define CSR_MEMALERTCONTROL_LSB 0 +#define CSR_MEMALERTCONTROL_MASK GENMASK_32(15, 0) +#define CSR_MALERTVREFLEVEL_LSB 0 +#define CSR_MALERTVREFLEVEL_MASK GENMASK_32(6, 0) +#define CSR_MALERTVREFEXTEN_LSB 7 +#define CSR_MALERTVREFEXTEN_MASK BIT(7) +#define CSR_MALERTPUSTREN_LSB 8 +#define CSR_MALERTPUSTREN_MASK GENMASK_32(11, 8) +#define CSR_MALERTPUEN_LSB 12 +#define CSR_MALERTPUEN_MASK BIT(12) +#define CSR_MALERTRXEN_LSB 13 +#define CSR_MALERTRXEN_MASK BIT(13) +#define CSR_MALERTDISABLEVAL_LSB 14 +#define CSR_MALERTDISABLEVAL_MASK BIT(14) +#define CSR_MALERTFORCEERROR_LSB 15 +#define CSR_MALERTFORCEERROR_MASK BIT(15) +/* CSR_MEMALERTCONTROL2 */ +#define CSR_MEMALERTCONTROL2_LSB 0 +#define CSR_MEMALERTCONTROL2_MASK BIT(0) +#define CSR_MALERTSYNCBYPASS_LSB 0 +#define CSR_MALERTSYNCBYPASS_MASK BIT(0) +/* CSR_MEMRESETL */ +#define CSR_MEMRESETL_LSB 0 +#define CSR_MEMRESETL_MASK GENMASK_32(1, 0) +#define CSR_MEMRESETLVALUE_LSB 0 +#define CSR_MEMRESETLVALUE_MASK BIT(0) +#define CSR_PROTECTMEMRESET_LSB 1 +#define CSR_PROTECTMEMRESET_MASK BIT(1) +/* CSR_PUBMODE */ +#define CSR_PUBMODE_LSB 0 +#define CSR_PUBMODE_MASK BIT(0) +#define CSR_HWTMEMSRC_LSB 0 +#define CSR_HWTMEMSRC_MASK BIT(0) +/* CSR_MISCPHYSTATUS */ +#define CSR_MISCPHYSTATUS_LSB 0 +#define CSR_MISCPHYSTATUS_MASK GENMASK_32(1, 0) +#define CSR_DCTSANE_LSB 0 +#define CSR_DCTSANE_MASK BIT(0) +#define CSR_PORMEMRESET_LSB 1 +#define CSR_PORMEMRESET_MASK BIT(1) +/* CSR_CORELOOPBACKSEL */ +#define CSR_CORELOOPBACKSEL_LSB 0 +#define CSR_CORELOOPBACKSEL_MASK BIT(0) +/* CSR_DLLTRAINPARAM */ +#define CSR_DLLTRAINPARAM_LSB 0 +#define CSR_DLLTRAINPARAM_MASK GENMASK_32(1, 0) +#define CSR_EXTENDPHDTIME_LSB 0 +#define CSR_EXTENDPHDTIME_MASK GENMASK_32(1, 0) +/* CSR_HWTLPCSENA */ +#define CSR_HWTLPCSENA_LSB 0 +#define CSR_HWTLPCSENA_MASK GENMASK_32(1, 0) +/* CSR_HWTLPCSENB */ +#define CSR_HWTLPCSENB_LSB 0 +#define CSR_HWTLPCSENB_MASK GENMASK_32(1, 0) +/* CSR_HWTLPCSENBYPASS */ +#define CSR_HWTLPCSENBYPASS_LSB 0 +#define CSR_HWTLPCSENBYPASS_MASK BIT(0) +/* CSR_DFICAMODE */ +#define CSR_DFICAMODE_LSB 0 +#define CSR_DFICAMODE_MASK GENMASK_32(3, 0) +#define CSR_DFILP3CAMODE_LSB 0 +#define CSR_DFILP3CAMODE_MASK BIT(0) +#define CSR_DFID4CAMODE_LSB 1 +#define CSR_DFID4CAMODE_MASK BIT(1) +#define CSR_DFILP4CAMODE_LSB 2 +#define CSR_DFILP4CAMODE_MASK BIT(2) +#define CSR_DFID4ALTCAMODE_LSB 3 +#define CSR_DFID4ALTCAMODE_MASK BIT(3) +/* CSR_HWTCACTL */ +#define CSR_HWTCACTL_LSB 0 +#define CSR_HWTCACTL_MASK BIT(0) +#define CSR_HWTDISDYNADRTRI_LSB 0 +#define CSR_HWTDISDYNADRTRI_MASK BIT(0) +/* CSR_HWTCAMODE */ +#define CSR_HWTCAMODE_LSB 0 +#define CSR_HWTCAMODE_MASK GENMASK_32(5, 0) +#define CSR_HWTLP3CAMODE_LSB 0 +#define CSR_HWTLP3CAMODE_MASK BIT(0) +#define CSR_HWTD4CAMODE_LSB 1 +#define CSR_HWTD4CAMODE_MASK BIT(1) +#define CSR_HWTLP4CAMODE_LSB 2 +#define CSR_HWTLP4CAMODE_MASK BIT(2) +#define CSR_HWTD4ALTCAMODE_LSB 3 +#define CSR_HWTD4ALTCAMODE_MASK BIT(3) +#define CSR_HWTCSINVERT_LSB 4 +#define CSR_HWTCSINVERT_MASK BIT(4) +#define CSR_HWTDBIINVERT_LSB 5 +#define CSR_HWTDBIINVERT_MASK BIT(5) +/* CSR_DLLCONTROL */ +#define CSR_DLLCONTROL_LSB 0 +#define CSR_DLLCONTROL_MASK GENMASK_32(2, 0) +#define CSR_DLLRESETRELOCK_LSB 0 +#define CSR_DLLRESETRELOCK_MASK BIT(0) +#define CSR_DLLRESETSLAVE_LSB 1 +#define CSR_DLLRESETSLAVE_MASK BIT(1) +#define CSR_DLLRESETRSVD_LSB 2 +#define CSR_DLLRESETRSVD_MASK BIT(2) +/* CSR_PULSEDLLUPDATEPHASE */ +#define CSR_PULSEDLLUPDATEPHASE_LSB 0 +#define CSR_PULSEDLLUPDATEPHASE_MASK GENMASK_32(7, 0) +#define CSR_PULSEDBYTEDLLUPDATEPHASE_LSB 0 +#define CSR_PULSEDBYTEDLLUPDATEPHASE_MASK BIT(0) +#define CSR_PULSEACKDLLUPDATEPHASE_LSB 1 +#define CSR_PULSEACKDLLUPDATEPHASE_MASK BIT(1) +#define CSR_PULSEACADLLUPDATEPHASE_LSB 2 +#define CSR_PULSEACADLLUPDATEPHASE_MASK BIT(2) +#define CSR_UPDATEPHASEDESTRESERVED_LSB 3 +#define CSR_UPDATEPHASEDESTRESERVED_MASK GENMASK_32(5, 3) +#define CSR_TRAINUPDATEPHASEONLONGBUBBLE_LSB 6 +#define CSR_TRAINUPDATEPHASEONLONGBUBBLE_MASK BIT(6) +#define CSR_ALWAYSUPDATELCDLPHASE_LSB 7 +#define CSR_ALWAYSUPDATELCDLPHASE_MASK BIT(7) +/* CSR_HWTCONTROLOVR0 */ +#define CSR_HWTCONTROLOVR0_LSB 0 +#define CSR_HWTCONTROLOVR0_MASK GENMASK_32(12, 0) +#define CSR_HWTCS0OVR0_LSB 0 +#define CSR_HWTCS0OVR0_MASK BIT(0) +#define CSR_HWTCS1OVR0_LSB 1 +#define CSR_HWTCS1OVR0_MASK BIT(1) +#define CSR_HWTCS2OVR0_LSB 2 +#define CSR_HWTCS2OVR0_MASK BIT(2) +#define CSR_HWTCS3OVR0_LSB 3 +#define CSR_HWTCS3OVR0_MASK BIT(3) +#define CSR_HWTCKE0OVR0_LSB 4 +#define CSR_HWTCKE0OVR0_MASK BIT(4) +#define CSR_HWTCKE1OVR0_LSB 5 +#define CSR_HWTCKE1OVR0_MASK BIT(5) +#define CSR_HWTCKE2OVR0_LSB 6 +#define CSR_HWTCKE2OVR0_MASK BIT(6) +#define CSR_HWTCKE3OVR0_LSB 7 +#define CSR_HWTCKE3OVR0_MASK BIT(7) +#define CSR_HWTODT0OVR0_LSB 8 +#define CSR_HWTODT0OVR0_MASK BIT(8) +#define CSR_HWTODT1OVR0_LSB 9 +#define CSR_HWTODT1OVR0_MASK BIT(9) +#define CSR_HWTODT2OVR0_LSB 10 +#define CSR_HWTODT2OVR0_MASK BIT(10) +#define CSR_HWTODT3OVR0_LSB 11 +#define CSR_HWTODT3OVR0_MASK BIT(11) +#define CSR_HWTPARITYOVR0_LSB 12 +#define CSR_HWTPARITYOVR0_MASK BIT(12) +/* CSR_HWTCONTROLOVR1 */ +#define CSR_HWTCONTROLOVR1_LSB 0 +#define CSR_HWTCONTROLOVR1_MASK GENMASK_32(12, 0) +#define CSR_HWTCS0OVR1_LSB 0 +#define CSR_HWTCS0OVR1_MASK BIT(0) +#define CSR_HWTCS1OVR1_LSB 1 +#define CSR_HWTCS1OVR1_MASK BIT(1) +#define CSR_HWTCS2OVR1_LSB 2 +#define CSR_HWTCS2OVR1_MASK BIT(2) +#define CSR_HWTCS3OVR1_LSB 3 +#define CSR_HWTCS3OVR1_MASK BIT(3) +#define CSR_HWTCKE0OVR1_LSB 4 +#define CSR_HWTCKE0OVR1_MASK BIT(4) +#define CSR_HWTCKE1OVR1_LSB 5 +#define CSR_HWTCKE1OVR1_MASK BIT(5) +#define CSR_HWTCKE2OVR1_LSB 6 +#define CSR_HWTCKE2OVR1_MASK BIT(6) +#define CSR_HWTCKE3OVR1_LSB 7 +#define CSR_HWTCKE3OVR1_MASK BIT(7) +#define CSR_HWTODT0OVR1_LSB 8 +#define CSR_HWTODT0OVR1_MASK BIT(8) +#define CSR_HWTODT1OVR1_LSB 9 +#define CSR_HWTODT1OVR1_MASK BIT(9) +#define CSR_HWTODT2OVR1_LSB 10 +#define CSR_HWTODT2OVR1_MASK BIT(10) +#define CSR_HWTODT3OVR1_LSB 11 +#define CSR_HWTODT3OVR1_MASK BIT(11) +#define CSR_HWTPARITYOVR1_LSB 12 +#define CSR_HWTPARITYOVR1_MASK BIT(12) +/* CSR_DLLGAINCTL */ +#define CSR_DLLGAINCTL_LSB 0 +#define CSR_DLLGAINCTL_MASK GENMASK_32(11, 0) +#define CSR_DLLGAINIV_LSB 0 +#define CSR_DLLGAINIV_MASK GENMASK_32(3, 0) +#define CSR_DLLGAINTV_LSB 4 +#define CSR_DLLGAINTV_MASK GENMASK_32(7, 4) +#define CSR_DLLSEEDSEL_LSB 8 +#define CSR_DLLSEEDSEL_MASK GENMASK_32(11, 8) +/* CSR_DLLLOCKPARAM */ +#define CSR_DLLLOCKPARAM_LSB 0 +#define CSR_DLLLOCKPARAM_MASK GENMASK_32(12, 0) +#define CSR_DISDLLSEEDSEL_LSB 0 +#define CSR_DISDLLSEEDSEL_MASK BIT(0) +#define CSR_DISDLLGAINIVSEED_LSB 1 +#define CSR_DISDLLGAINIVSEED_MASK BIT(1) +#define CSR_DLLLOCKPARAMSPARE_LSB 2 +#define CSR_DLLLOCKPARAMSPARE_MASK GENMASK_32(3, 2) +#define CSR_LCDLSEED0_LSB 4 +#define CSR_LCDLSEED0_MASK GENMASK_32(12, 4) +/* CSR_HWTCONTROLVAL0 */ +#define CSR_HWTCONTROLVAL0_LSB 0 +#define CSR_HWTCONTROLVAL0_MASK GENMASK_32(12, 0) +#define CSR_HWTCS0VAL0_LSB 0 +#define CSR_HWTCS0VAL0_MASK BIT(0) +#define CSR_HWTCS1VAL0_LSB 1 +#define CSR_HWTCS1VAL0_MASK BIT(1) +#define CSR_HWTCS2VAL0_LSB 2 +#define CSR_HWTCS2VAL0_MASK BIT(2) +#define CSR_HWTCS3VAL0_LSB 3 +#define CSR_HWTCS3VAL0_MASK BIT(3) +#define CSR_HWTCKE0VAL0_LSB 4 +#define CSR_HWTCKE0VAL0_MASK BIT(4) +#define CSR_HWTCKE1VAL0_LSB 5 +#define CSR_HWTCKE1VAL0_MASK BIT(5) +#define CSR_HWTCKE2VAL0_LSB 6 +#define CSR_HWTCKE2VAL0_MASK BIT(6) +#define CSR_HWTCKE3VAL0_LSB 7 +#define CSR_HWTCKE3VAL0_MASK BIT(7) +#define CSR_HWTODT0VAL0_LSB 8 +#define CSR_HWTODT0VAL0_MASK BIT(8) +#define CSR_HWTODT1VAL0_LSB 9 +#define CSR_HWTODT1VAL0_MASK BIT(9) +#define CSR_HWTODT2VAL0_LSB 10 +#define CSR_HWTODT2VAL0_MASK BIT(10) +#define CSR_HWTODT3VAL0_LSB 11 +#define CSR_HWTODT3VAL0_MASK BIT(11) +#define CSR_HWTPARITYVAL0_LSB 12 +#define CSR_HWTPARITYVAL0_MASK BIT(12) +/* CSR_HWTCONTROLVAL1 */ +#define CSR_HWTCONTROLVAL1_LSB 0 +#define CSR_HWTCONTROLVAL1_MASK GENMASK_32(12, 0) +#define CSR_HWTCS0VAL1_LSB 0 +#define CSR_HWTCS0VAL1_MASK BIT(0) +#define CSR_HWTCS1VAL1_LSB 1 +#define CSR_HWTCS1VAL1_MASK BIT(1) +#define CSR_HWTCS2VAL1_LSB 2 +#define CSR_HWTCS2VAL1_MASK BIT(2) +#define CSR_HWTCS3VAL1_LSB 3 +#define CSR_HWTCS3VAL1_MASK BIT(3) +#define CSR_HWTCKE0VAL1_LSB 4 +#define CSR_HWTCKE0VAL1_MASK BIT(4) +#define CSR_HWTCKE1VAL1_LSB 5 +#define CSR_HWTCKE1VAL1_MASK BIT(5) +#define CSR_HWTCKE2VAL1_LSB 6 +#define CSR_HWTCKE2VAL1_MASK BIT(6) +#define CSR_HWTCKE3VAL1_LSB 7 +#define CSR_HWTCKE3VAL1_MASK BIT(7) +#define CSR_HWTODT0VAL1_LSB 8 +#define CSR_HWTODT0VAL1_MASK BIT(8) +#define CSR_HWTODT1VAL1_LSB 9 +#define CSR_HWTODT1VAL1_MASK BIT(9) +#define CSR_HWTODT2VAL1_LSB 10 +#define CSR_HWTODT2VAL1_MASK BIT(10) +#define CSR_HWTODT3VAL1_LSB 11 +#define CSR_HWTODT3VAL1_MASK BIT(11) +#define CSR_HWTPARITYVAL1_LSB 12 +#define CSR_HWTPARITYVAL1_MASK BIT(12) +/* CSR_ACSMGLBLSTART */ +#define CSR_ACSMGLBLSTART_LSB 0 +#define CSR_ACSMGLBLSTART_MASK BIT(0) +/* CSR_ACSMGLBLSGLSTPCTRL */ +#define CSR_ACSMGLBLSGLSTPCTRL_LSB 0 +#define CSR_ACSMGLBLSGLSTPCTRL_MASK GENMASK_32(1, 0) +#define CSR_ACSMSGLSTPMODE_LSB 0 +#define CSR_ACSMSGLSTPMODE_MASK BIT(0) +#define CSR_ACSMSGLSTP_LSB 1 +#define CSR_ACSMSGLSTP_MASK BIT(1) +/* CSR_LCDLCALPHASE */ +#define CSR_LCDLCALPHASE_LSB 0 +#define CSR_LCDLCALPHASE_MASK GENMASK_32(8, 0) +/* CSR_LCDLCALCTRL */ +#define CSR_LCDLCALCTRL_LSB 0 +#define CSR_LCDLCALCTRL_MASK GENMASK_32(6, 0) +#define CSR_LCDLCALMODE_LSB 0 +#define CSR_LCDLCALMODE_MASK BIT(0) +#define CSR_LCDLCALSLOWCLKSEL_LSB 1 +#define CSR_LCDLCALSLOWCLKSEL_MASK BIT(1) +#define CSR_LCDLCALEN_LSB 2 +#define CSR_LCDLCALEN_MASK BIT(2) +#define CSR_LCDLCALPHASEUPDATE_LSB 3 +#define CSR_LCDLCALPHASEUPDATE_MASK BIT(3) +#define CSR_LCDLCALCLKEN_LSB 4 +#define CSR_LCDLCALCLKEN_MASK BIT(4) +#define CSR_LCDLCALSAMPEN_LSB 5 +#define CSR_LCDLCALSAMPEN_MASK BIT(5) +#define CSR_LCDLCALSLOWCLKEN_LSB 6 +#define CSR_LCDLCALSLOWCLKEN_MASK BIT(6) +/* CSR_CALRATE */ +#define CSR_CALRATE_LSB 0 +#define CSR_CALRATE_MASK GENMASK_32(6, 0) +#define CSR_CALINTERVAL_LSB 0 +#define CSR_CALINTERVAL_MASK GENMASK_32(3, 0) +#define CSR_CALRUN_LSB 4 +#define CSR_CALRUN_MASK BIT(4) +#define CSR_CALONCE_LSB 5 +#define CSR_CALONCE_MASK BIT(5) +#define CSR_DISABLEBACKGROUNDZQUPDATES_LSB 6 +#define CSR_DISABLEBACKGROUNDZQUPDATES_MASK BIT(6) +/* CSR_CALZAP */ +#define CSR_CALZAP_LSB 0 +#define CSR_CALZAP_MASK BIT(0) +/* CSR_PSTATE */ +#define CSR_PSTATE_LSB 0 +#define CSR_PSTATE_MASK GENMASK_32(3, 0) +/* CSR_CALPREDRIVEROVERRIDE */ +#define CSR_CALPREDRIVEROVERRIDE_LSB 0 +#define CSR_CALPREDRIVEROVERRIDE_MASK GENMASK_32(7, 0) +#define CSR_TXPREOVN_LSB 0 +#define CSR_TXPREOVN_MASK GENMASK_32(3, 0) +#define CSR_TXPREOVP_LSB 4 +#define CSR_TXPREOVP_MASK GENMASK_32(7, 4) +/* CSR_PLLOUTGATECONTROL */ +#define CSR_PLLOUTGATECONTROL_LSB 0 +#define CSR_PLLOUTGATECONTROL_MASK GENMASK_32(1, 0) +#define CSR_PCLKGATEEN_LSB 0 +#define CSR_PCLKGATEEN_MASK BIT(0) +#define CSR_RESERVED2X1_LSB 1 +#define CSR_RESERVED2X1_MASK BIT(1) +/* CSR_UCMEMRESETCONTROL */ +#define CSR_UCMEMRESETCONTROL_LSB 0 +#define CSR_UCMEMRESETCONTROL_MASK BIT(0) +#define CSR_UCDCTSANE_LSB 0 +#define CSR_UCDCTSANE_MASK BIT(0) +/* CSR_PORCONTROL */ +#define CSR_PORCONTROL_LSB 0 +#define CSR_PORCONTROL_MASK BIT(0) +#define CSR_PLLDLLLOCKDONE_LSB 0 +#define CSR_PLLDLLLOCKDONE_MASK BIT(0) +/* CSR_CALBUSY */ +#define CSR_CALBUSY_LSB 0 +#define CSR_CALBUSY_MASK BIT(0) +/* CSR_CALMISC2 */ +#define CSR_CALMISC2_LSB 0 +#define CSR_CALMISC2_MASK GENMASK_32(15, 0) +#define CSR_CALNUMVOTES_LSB 0 +#define CSR_CALNUMVOTES_MASK GENMASK_32(2, 0) +#define CSR_RESERVED10X3_LSB 3 +#define CSR_RESERVED10X3_MASK GENMASK_32(10, 3) +#define CSR_RESERVED11_LSB 11 +#define CSR_RESERVED11_MASK BIT(11) +#define CSR_CALCMPTRRESTRIM_LSB 12 +#define CSR_CALCMPTRRESTRIM_MASK BIT(12) +#define CSR_CALCANCELROUNDERRDIS_LSB 13 +#define CSR_CALCANCELROUNDERRDIS_MASK BIT(13) +#define CSR_CALSLOWCMPANA_LSB 14 +#define CSR_CALSLOWCMPANA_MASK BIT(14) +#define CSR_RESERVED15_LSB 15 +#define CSR_RESERVED15_MASK BIT(15) +/* CSR_CALMISC */ +#define CSR_CALMISC_LSB 0 +#define CSR_CALMISC_MASK GENMASK_32(2, 0) +#define CSR_CALCMPR5DIS_LSB 0 +#define CSR_CALCMPR5DIS_MASK BIT(0) +#define CSR_CALNINTDIS_LSB 1 +#define CSR_CALNINTDIS_MASK BIT(1) +#define CSR_CALPEXTDIS_LSB 2 +#define CSR_CALPEXTDIS_MASK BIT(2) +/* CSR_CALVREFS */ +#define CSR_CALVREFS_LSB 0 +#define CSR_CALVREFS_MASK GENMASK_32(1, 0) +/* CSR_CALCMPR5 */ +#define CSR_CALCMPR5_LSB 0 +#define CSR_CALCMPR5_MASK GENMASK_32(7, 0) +/* CSR_CALNINT */ +#define CSR_CALNINT_LSB 0 +#define CSR_CALNINT_MASK GENMASK_32(4, 0) +#define CSR_CALNINTTHB_LSB 0 +#define CSR_CALNINTTHB_MASK GENMASK_32(4, 0) +/* CSR_CALPEXT */ +#define CSR_CALPEXT_LSB 0 +#define CSR_CALPEXT_MASK GENMASK_32(4, 0) +#define CSR_CALPEXTTHB_LSB 0 +#define CSR_CALPEXTTHB_MASK GENMASK_32(4, 0) +/* CSR_CALCMPINVERT */ +#define CSR_CALCMPINVERT_LSB 0 +#define CSR_CALCMPINVERT_MASK GENMASK_32(4, 0) +#define CSR_CMPINVERTCALDAC50_LSB 0 +#define CSR_CMPINVERTCALDAC50_MASK BIT(0) +#define CSR_CMPINVERTCALDRVPD50_LSB 1 +#define CSR_CMPINVERTCALDRVPD50_MASK BIT(1) +#define CSR_CMPINVERTCALDRVPU50_LSB 2 +#define CSR_CMPINVERTCALDRVPU50_MASK BIT(2) +#define CSR_CMPINVERTCALODTPD_LSB 3 +#define CSR_CMPINVERTCALODTPD_MASK BIT(3) +#define CSR_CMPINVERTCALODTPU_LSB 4 +#define CSR_CMPINVERTCALODTPU_MASK BIT(4) +/* CSR_CALCMPANACNTRL */ +#define CSR_CALCMPANACNTRL_LSB 0 +#define CSR_CALCMPANACNTRL_MASK GENMASK_32(9, 0) +#define CSR_CMPRGAINCURRADJ_LSB 0 +#define CSR_CMPRGAINCURRADJ_MASK GENMASK_32(7, 0) +#define CSR_CMPRGAINRESADJ_LSB 8 +#define CSR_CMPRGAINRESADJ_MASK BIT(8) +#define CSR_CMPRBIASBYPASSEN_LSB 9 +#define CSR_CMPRBIASBYPASSEN_MASK BIT(9) +/* CSR_DFIRDDATACSDESTMAP */ +#define CSR_DFIRDDATACSDESTMAP_LSB 0 +#define CSR_DFIRDDATACSDESTMAP_MASK GENMASK_32(7, 0) +#define CSR_DFIRDDESTM0_LSB 0 +#define CSR_DFIRDDESTM0_MASK GENMASK_32(1, 0) +#define CSR_DFIRDDESTM1_LSB 2 +#define CSR_DFIRDDESTM1_MASK GENMASK_32(3, 2) +#define CSR_DFIRDDESTM2_LSB 4 +#define CSR_DFIRDDESTM2_MASK GENMASK_32(5, 4) +#define CSR_DFIRDDESTM3_LSB 6 +#define CSR_DFIRDDESTM3_MASK GENMASK_32(7, 6) +/* CSR_VREFINGLOBAL */ +#define CSR_VREFINGLOBAL_LSB 0 +#define CSR_VREFINGLOBAL_MASK GENMASK_32(14, 0) +#define CSR_GLOBALVREFINSEL_LSB 0 +#define CSR_GLOBALVREFINSEL_MASK GENMASK_32(2, 0) +#define CSR_GLOBALVREFINDAC_LSB 3 +#define CSR_GLOBALVREFINDAC_MASK GENMASK_32(9, 3) +#define CSR_GLOBALVREFINTRIM_LSB 10 +#define CSR_GLOBALVREFINTRIM_MASK GENMASK_32(13, 10) +#define CSR_GLOBALVREFINMODE_LSB 14 +#define CSR_GLOBALVREFINMODE_MASK BIT(14) +/* CSR_DFIWRDATACSDESTMAP */ +#define CSR_DFIWRDATACSDESTMAP_LSB 0 +#define CSR_DFIWRDATACSDESTMAP_MASK GENMASK_32(7, 0) +#define CSR_DFIWRDESTM0_LSB 0 +#define CSR_DFIWRDESTM0_MASK GENMASK_32(1, 0) +#define CSR_DFIWRDESTM1_LSB 2 +#define CSR_DFIWRDESTM1_MASK GENMASK_32(3, 2) +#define CSR_DFIWRDESTM2_LSB 4 +#define CSR_DFIWRDESTM2_MASK GENMASK_32(5, 4) +#define CSR_DFIWRDESTM3_LSB 6 +#define CSR_DFIWRDESTM3_MASK GENMASK_32(7, 6) +/* CSR_MASUPDGOODCTR */ +#define CSR_MASUPDGOODCTR_LSB 0 +#define CSR_MASUPDGOODCTR_MASK GENMASK_32(15, 0) +/* CSR_PHYUPD0GOODCTR */ +#define CSR_PHYUPD0GOODCTR_LSB 0 +#define CSR_PHYUPD0GOODCTR_MASK GENMASK_32(15, 0) +/* CSR_PHYUPD1GOODCTR */ +#define CSR_PHYUPD1GOODCTR_LSB 0 +#define CSR_PHYUPD1GOODCTR_MASK GENMASK_32(15, 0) +/* CSR_CTLUPD0GOODCTR */ +#define CSR_CTLUPD0GOODCTR_LSB 0 +#define CSR_CTLUPD0GOODCTR_MASK GENMASK_32(15, 0) +/* CSR_CTLUPD1GOODCTR */ +#define CSR_CTLUPD1GOODCTR_LSB 0 +#define CSR_CTLUPD1GOODCTR_MASK GENMASK_32(15, 0) +/* CSR_MASUPDFAILCTR */ +#define CSR_MASUPDFAILCTR_LSB 0 +#define CSR_MASUPDFAILCTR_MASK GENMASK_32(15, 0) +/* CSR_PHYUPD0FAILCTR */ +#define CSR_PHYUPD0FAILCTR_LSB 0 +#define CSR_PHYUPD0FAILCTR_MASK GENMASK_32(15, 0) +/* CSR_PHYUPD1FAILCTR */ +#define CSR_PHYUPD1FAILCTR_LSB 0 +#define CSR_PHYUPD1FAILCTR_MASK GENMASK_32(15, 0) +/* CSR_PHYPERFCTRENABLE */ +#define CSR_PHYPERFCTRENABLE_LSB 0 +#define CSR_PHYPERFCTRENABLE_MASK GENMASK_32(7, 0) +#define CSR_MASUPDGOODCTL_LSB 0 +#define CSR_MASUPDGOODCTL_MASK BIT(0) +#define CSR_PHYUPD0GOODCTL_LSB 1 +#define CSR_PHYUPD0GOODCTL_MASK BIT(1) +#define CSR_PHYUPD1GOODCTL_LSB 2 +#define CSR_PHYUPD1GOODCTL_MASK BIT(2) +#define CSR_CTLUPD0GOODCTL_LSB 3 +#define CSR_CTLUPD0GOODCTL_MASK BIT(3) +#define CSR_CTLUPD1GOODCTL_LSB 4 +#define CSR_CTLUPD1GOODCTL_MASK BIT(4) +#define CSR_MASUPDFAILCTL_LSB 5 +#define CSR_MASUPDFAILCTL_MASK BIT(5) +#define CSR_PHYUPD0FAILCTL_LSB 6 +#define CSR_PHYUPD0FAILCTL_MASK BIT(6) +#define CSR_PHYUPD1FAILCTL_LSB 7 +#define CSR_PHYUPD1FAILCTL_MASK BIT(7) +/* CSR_DFIWRRDDATACSCONFIG */ +#define CSR_DFIWRRDDATACSCONFIG_LSB 0 +#define CSR_DFIWRRDDATACSCONFIG_MASK GENMASK_32(1, 0) +#define CSR_DFIWRDATACSPOLARITY_LSB 0 +#define CSR_DFIWRDATACSPOLARITY_MASK BIT(0) +#define CSR_DFIRDDATACSPOLARITY_LSB 1 +#define CSR_DFIRDDATACSPOLARITY_MASK BIT(1) +/* CSR_PLLPWRDN */ +#define CSR_PLLPWRDN_LSB 0 +#define CSR_PLLPWRDN_MASK BIT(0) +/* CSR_PLLRESET */ +#define CSR_PLLRESET_LSB 0 +#define CSR_PLLRESET_MASK BIT(0) +/* CSR_PLLCTRL2 */ +#define CSR_PLLCTRL2_LSB 0 +#define CSR_PLLCTRL2_MASK GENMASK_32(4, 0) +#define CSR_PLLFREQSEL_LSB 0 +#define CSR_PLLFREQSEL_MASK GENMASK_32(4, 0) +/* CSR_PLLCTRL0 */ +#define CSR_PLLCTRL0_LSB 0 +#define CSR_PLLCTRL0_MASK GENMASK_32(15, 0) +#define CSR_PLLSTANDBY_LSB 0 +#define CSR_PLLSTANDBY_MASK BIT(0) +#define CSR_PLLBYPSEL_LSB 1 +#define CSR_PLLBYPSEL_MASK BIT(1) +#define CSR_PLLX2MODE_LSB 2 +#define CSR_PLLX2MODE_MASK BIT(2) +#define CSR_PLLOUTBYPEN_LSB 3 +#define CSR_PLLOUTBYPEN_MASK BIT(3) +#define CSR_PLLPRESET_LSB 4 +#define CSR_PLLPRESET_MASK BIT(4) +#define CSR_PLLBYPASSMODE_LSB 5 +#define CSR_PLLBYPASSMODE_MASK BIT(5) +#define CSR_PLLSELDFIFREQRATIO_LSB 6 +#define CSR_PLLSELDFIFREQRATIO_MASK BIT(6) +#define CSR_PLLSYNCBUSFLUSH_LSB 7 +#define CSR_PLLSYNCBUSFLUSH_MASK BIT(7) +#define CSR_PLLSYNCBUSBYP_LSB 8 +#define CSR_PLLSYNCBUSBYP_MASK BIT(8) +#define CSR_PLLRESERVED10X9_LSB 9 +#define CSR_PLLRESERVED10X9_MASK GENMASK_32(10, 9) +#define CSR_PLLGEARSHIFT_LSB 11 +#define CSR_PLLGEARSHIFT_MASK BIT(11) +#define CSR_PLLLOCKCNTSEL_LSB 12 +#define CSR_PLLLOCKCNTSEL_MASK BIT(12) +#define CSR_PLLLOCKPHSEL_LSB 13 +#define CSR_PLLLOCKPHSEL_MASK GENMASK_32(14, 13) +#define CSR_PLLSPARECTRL0_LSB 15 +#define CSR_PLLSPARECTRL0_MASK BIT(15) +/* CSR_PLLCTRL1 */ +#define CSR_PLLCTRL1_LSB 0 +#define CSR_PLLCTRL1_MASK GENMASK_32(8, 0) +#define CSR_PLLCPINTCTRL_LSB 0 +#define CSR_PLLCPINTCTRL_MASK GENMASK_32(4, 0) +#define CSR_PLLCPPROPCTRL_LSB 5 +#define CSR_PLLCPPROPCTRL_MASK GENMASK_32(8, 5) +/* CSR_PLLTST */ +#define CSR_PLLTST_LSB 0 +#define CSR_PLLTST_MASK GENMASK_32(8, 0) +#define CSR_PLLANATSTEN_LSB 0 +#define CSR_PLLANATSTEN_MASK BIT(0) +#define CSR_PLLANATSTSEL_LSB 1 +#define CSR_PLLANATSTSEL_MASK GENMASK_32(4, 1) +#define CSR_PLLDIGTSTSEL_LSB 5 +#define CSR_PLLDIGTSTSEL_MASK GENMASK_32(8, 5) +/* CSR_PLLLOCKSTATUS */ +#define CSR_PLLLOCKSTATUS_LSB 0 +#define CSR_PLLLOCKSTATUS_MASK BIT(0) +/* CSR_PLLTESTMODE */ +#define CSR_PLLTESTMODE_LSB 0 +#define CSR_PLLTESTMODE_MASK GENMASK_32(15, 0) +/* CSR_PLLCTRL3 */ +#define CSR_PLLCTRL3_LSB 0 +#define CSR_PLLCTRL3_MASK GENMASK_32(15, 0) +#define CSR_PLLSPARE_LSB 0 +#define CSR_PLLSPARE_MASK GENMASK_32(3, 0) +#define CSR_PLLMAXRANGE_LSB 4 +#define CSR_PLLMAXRANGE_MASK GENMASK_32(8, 4) +#define CSR_PLLDACVALIN_LSB 9 +#define CSR_PLLDACVALIN_MASK GENMASK_32(13, 9) +#define CSR_PLLFORCECAL_LSB 14 +#define CSR_PLLFORCECAL_MASK BIT(14) +#define CSR_PLLENCAL_LSB 15 +#define CSR_PLLENCAL_MASK BIT(15) +/* CSR_PLLCTRL4 */ +#define CSR_PLLCTRL4_LSB 0 +#define CSR_PLLCTRL4_MASK GENMASK_32(8, 0) +#define CSR_PLLCPINTGSCTRL_LSB 0 +#define CSR_PLLCPINTGSCTRL_MASK GENMASK_32(4, 0) +#define CSR_PLLCPPROPGSCTRL_LSB 5 +#define CSR_PLLCPPROPGSCTRL_MASK GENMASK_32(8, 5) +/* CSR_PLLENDOFCAL */ +#define CSR_PLLENDOFCAL_LSB 0 +#define CSR_PLLENDOFCAL_MASK BIT(0) +/* CSR_PLLSTANDBYEFF */ +#define CSR_PLLSTANDBYEFF_LSB 0 +#define CSR_PLLSTANDBYEFF_MASK BIT(0) +/* CSR_PLLDACVALOUT */ +#define CSR_PLLDACVALOUT_LSB 0 +#define CSR_PLLDACVALOUT_MASK GENMASK_32(4, 0) +/* CSR_DLYTESTSEQ */ +#define CSR_DLYTESTSEQ_LSB 0 +#define CSR_DLYTESTSEQ_MASK GENMASK_32(5, 0) +#define CSR_DLYTESTEN_LSB 0 +#define CSR_DLYTESTEN_MASK BIT(0) +#define CSR_DLYTESTCNTINIT_LSB 1 +#define CSR_DLYTESTCNTINIT_MASK BIT(1) +#define CSR_DLYTESTENOVERRIDE1_LSB 2 +#define CSR_DLYTESTENOVERRIDE1_MASK BIT(2) +#define CSR_DLYTESTENOVERRIDE2_LSB 3 +#define CSR_DLYTESTENOVERRIDE2_MASK BIT(3) +#define CSR_SYNCDLYMULTIPLIER_LSB 4 +#define CSR_SYNCDLYMULTIPLIER_MASK GENMASK_32(5, 4) +/* CSR_DLYTESTRINGSELDB */ +#define CSR_DLYTESTRINGSELDB_LSB 0 +#define CSR_DLYTESTRINGSELDB_MASK GENMASK_32(4, 0) +#define CSR_DLYTESTCUTDB_LSB 0 +#define CSR_DLYTESTCUTDB_MASK GENMASK_32(4, 0) +/* CSR_DLYTESTRINGSELAC */ +#define CSR_DLYTESTRINGSELAC_LSB 0 +#define CSR_DLYTESTRINGSELAC_MASK GENMASK_32(4, 0) +#define CSR_DLYTESTCUTAC_LSB 0 +#define CSR_DLYTESTCUTAC_MASK GENMASK_32(4, 0) +/* CSR_DLYTESTCNTDFICLKIV */ +#define CSR_DLYTESTCNTDFICLKIV_LSB 0 +#define CSR_DLYTESTCNTDFICLKIV_MASK GENMASK_32(15, 0) +/* CSR_DLYTESTCNTDFICLK */ +#define CSR_DLYTESTCNTDFICLK_LSB 0 +#define CSR_DLYTESTCNTDFICLK_MASK GENMASK_32(15, 0) +/* CSR_DLYTESTCNTRINGOSCDB0 */ +#define CSR_DLYTESTCNTRINGOSCDB0_LSB 0 +#define CSR_DLYTESTCNTRINGOSCDB0_MASK GENMASK_32(15, 0) +/* CSR_DLYTESTCNTRINGOSCDB1 */ +#define CSR_DLYTESTCNTRINGOSCDB1_LSB 0 +#define CSR_DLYTESTCNTRINGOSCDB1_MASK GENMASK_32(15, 0) +/* CSR_DLYTESTCNTRINGOSCDB2 */ +#define CSR_DLYTESTCNTRINGOSCDB2_LSB 0 +#define CSR_DLYTESTCNTRINGOSCDB2_MASK GENMASK_32(15, 0) +/* CSR_DLYTESTCNTRINGOSCDB3 */ +#define CSR_DLYTESTCNTRINGOSCDB3_LSB 0 +#define CSR_DLYTESTCNTRINGOSCDB3_MASK GENMASK_32(15, 0) +/* CSR_DLYTESTCNTRINGOSCDB4 */ +#define CSR_DLYTESTCNTRINGOSCDB4_LSB 0 +#define CSR_DLYTESTCNTRINGOSCDB4_MASK GENMASK_32(15, 0) +/* CSR_DLYTESTCNTRINGOSCDB5 */ +#define CSR_DLYTESTCNTRINGOSCDB5_LSB 0 +#define CSR_DLYTESTCNTRINGOSCDB5_MASK GENMASK_32(15, 0) +/* CSR_DLYTESTCNTRINGOSCDB6 */ +#define CSR_DLYTESTCNTRINGOSCDB6_LSB 0 +#define CSR_DLYTESTCNTRINGOSCDB6_MASK GENMASK_32(15, 0) +/* CSR_DLYTESTCNTRINGOSCDB7 */ +#define CSR_DLYTESTCNTRINGOSCDB7_LSB 0 +#define CSR_DLYTESTCNTRINGOSCDB7_MASK GENMASK_32(15, 0) +/* CSR_DLYTESTCNTRINGOSCDB8 */ +#define CSR_DLYTESTCNTRINGOSCDB8_LSB 0 +#define CSR_DLYTESTCNTRINGOSCDB8_MASK GENMASK_32(15, 0) +/* CSR_DLYTESTCNTRINGOSCDB9 */ +#define CSR_DLYTESTCNTRINGOSCDB9_LSB 0 +#define CSR_DLYTESTCNTRINGOSCDB9_MASK GENMASK_32(15, 0) +/* CSR_DLYTESTCNTRINGOSCAC */ +#define CSR_DLYTESTCNTRINGOSCAC_LSB 0 +#define CSR_DLYTESTCNTRINGOSCAC_MASK GENMASK_32(15, 0) +/* CSR_MSTLCDLDBGCNTL */ +#define CSR_MSTLCDLDBGCNTL_LSB 0 +#define CSR_MSTLCDLDBGCNTL_MASK GENMASK_32(11, 0) +#define CSR_MSTLCDLFINEOVRVAL_LSB 0 +#define CSR_MSTLCDLFINEOVRVAL_MASK GENMASK_32(8, 0) +#define CSR_MSTLCDLFINEOVR_LSB 9 +#define CSR_MSTLCDLFINEOVR_MASK BIT(9) +#define CSR_MSTLCDLFINESNAP_LSB 10 +#define CSR_MSTLCDLFINESNAP_MASK BIT(10) +#define CSR_MSTLCDLTSTENABLE_LSB 11 +#define CSR_MSTLCDLTSTENABLE_MASK BIT(11) +/* CSR_MSTLCDL0DBGRES */ +#define CSR_MSTLCDL0DBGRES_LSB 0 +#define CSR_MSTLCDL0DBGRES_MASK GENMASK_32(12, 0) +#define CSR_MSTLCDL0FINESNAPVAL_LSB 0 +#define CSR_MSTLCDL0FINESNAPVAL_MASK GENMASK_32(8, 0) +#define CSR_MSTLCDL0PHDSNAPVAL_LSB 9 +#define CSR_MSTLCDL0PHDSNAPVAL_MASK BIT(9) +#define CSR_MSTLCDL0STICKYLOCK_LSB 10 +#define CSR_MSTLCDL0STICKYLOCK_MASK BIT(10) +#define CSR_MSTLCDL0STICKYUNLOCK_LSB 11 +#define CSR_MSTLCDL0STICKYUNLOCK_MASK BIT(11) +#define CSR_MSTLCDL0LIVELOCK_LSB 12 +#define CSR_MSTLCDL0LIVELOCK_MASK BIT(12) +/* CSR_MSTLCDL1DBGRES */ +#define CSR_MSTLCDL1DBGRES_LSB 0 +#define CSR_MSTLCDL1DBGRES_MASK GENMASK_32(12, 0) +#define CSR_MSTLCDL1FINESNAPVAL_LSB 0 +#define CSR_MSTLCDL1FINESNAPVAL_MASK GENMASK_32(8, 0) +#define CSR_MSTLCDL1PHDSNAPVAL_LSB 9 +#define CSR_MSTLCDL1PHDSNAPVAL_MASK BIT(9) +#define CSR_MSTLCDL1STICKYLOCK_LSB 10 +#define CSR_MSTLCDL1STICKYLOCK_MASK BIT(10) +#define CSR_MSTLCDL1STICKYUNLOCK_LSB 11 +#define CSR_MSTLCDL1STICKYUNLOCK_MASK BIT(11) +#define CSR_MSTLCDL1LIVELOCK_LSB 12 +#define CSR_MSTLCDL1LIVELOCK_MASK BIT(12) +/* CSR_LCDLDBGCNTL */ +#define CSR_LCDLDBGCNTL_LSB 0 +#define CSR_LCDLDBGCNTL_MASK GENMASK_32(15, 0) +#define CSR_LCDLFINEOVRVAL_LSB 0 +#define CSR_LCDLFINEOVRVAL_MASK GENMASK_32(8, 0) +#define CSR_LCDLFINEOVR_LSB 9 +#define CSR_LCDLFINEOVR_MASK BIT(9) +#define CSR_LCDLFINESNAP_LSB 10 +#define CSR_LCDLFINESNAP_MASK BIT(10) +#define CSR_LCDLTSTENABLE_LSB 11 +#define CSR_LCDLTSTENABLE_MASK BIT(11) +#define CSR_LCDLSTATUSSEL_LSB 12 +#define CSR_LCDLSTATUSSEL_MASK GENMASK_32(15, 12) +/* CSR_ACLCDLSTATUS */ +#define CSR_ACLCDLSTATUS_LSB 0 +#define CSR_ACLCDLSTATUS_MASK GENMASK_32(13, 0) +#define CSR_ACLCDLFINESNAPVAL_LSB 0 +#define CSR_ACLCDLFINESNAPVAL_MASK GENMASK_32(9, 0) +#define CSR_ACLCDLPHDSNAPVAL_LSB 10 +#define CSR_ACLCDLPHDSNAPVAL_MASK BIT(10) +#define CSR_ACLCDLSTICKYLOCK_LSB 11 +#define CSR_ACLCDLSTICKYLOCK_MASK BIT(11) +#define CSR_ACLCDLSTICKYUNLOCK_LSB 12 +#define CSR_ACLCDLSTICKYUNLOCK_MASK BIT(12) +#define CSR_ACLCDLLIVELOCK_LSB 13 +#define CSR_ACLCDLLIVELOCK_MASK BIT(13) +/* CSR_CUSTPHYREV */ +#define CSR_CUSTPHYREV_LSB 0 +#define CSR_CUSTPHYREV_MASK GENMASK_32(5, 0) +/* CSR_PHYREV */ +#define CSR_PHYREV_LSB 0 +#define CSR_PHYREV_MASK GENMASK_32(15, 0) +#define CSR_PHYMNR_LSB 0 +#define CSR_PHYMNR_MASK GENMASK_32(3, 0) +#define CSR_PHYMDR_LSB 4 +#define CSR_PHYMDR_MASK GENMASK_32(7, 4) +#define CSR_PHYMJR_LSB 8 +#define CSR_PHYMJR_MASK GENMASK_32(15, 8) +/* CSR_LP3EXITSEQ0BSTARTVECTOR */ +#define CSR_LP3EXITSEQ0BSTARTVECTOR_LSB 0 +#define CSR_LP3EXITSEQ0BSTARTVECTOR_MASK GENMASK_32(7, 0) +#define CSR_LP3EXITSEQ0BSTARTVECPLLENABLED_LSB 0 +#define CSR_LP3EXITSEQ0BSTARTVECPLLENABLED_MASK GENMASK_32(3, 0) +#define CSR_LP3EXITSEQ0BSTARTVECPLLBYPASSED_LSB 4 +#define CSR_LP3EXITSEQ0BSTARTVECPLLBYPASSED_MASK GENMASK_32(7, 4) +/* CSR_DFIFREQXLAT0 */ +#define CSR_DFIFREQXLAT0_LSB 0 +#define CSR_DFIFREQXLAT0_MASK GENMASK_32(15, 0) +#define CSR_DFIFREQXLATVAL0_LSB 0 +#define CSR_DFIFREQXLATVAL0_MASK GENMASK_32(3, 0) +#define CSR_DFIFREQXLATVAL1_LSB 4 +#define CSR_DFIFREQXLATVAL1_MASK GENMASK_32(7, 4) +#define CSR_DFIFREQXLATVAL2_LSB 8 +#define CSR_DFIFREQXLATVAL2_MASK GENMASK_32(11, 8) +#define CSR_DFIFREQXLATVAL3_LSB 12 +#define CSR_DFIFREQXLATVAL3_MASK GENMASK_32(15, 12) +/* CSR_DFIFREQXLAT1 */ +#define CSR_DFIFREQXLAT1_LSB 0 +#define CSR_DFIFREQXLAT1_MASK GENMASK_32(15, 0) +#define CSR_DFIFREQXLATVAL4_LSB 0 +#define CSR_DFIFREQXLATVAL4_MASK GENMASK_32(3, 0) +#define CSR_DFIFREQXLATVAL5_LSB 4 +#define CSR_DFIFREQXLATVAL5_MASK GENMASK_32(7, 4) +#define CSR_DFIFREQXLATVAL6_LSB 8 +#define CSR_DFIFREQXLATVAL6_MASK GENMASK_32(11, 8) +#define CSR_DFIFREQXLATVAL7_LSB 12 +#define CSR_DFIFREQXLATVAL7_MASK GENMASK_32(15, 12) +/* CSR_DFIFREQXLAT2 */ +#define CSR_DFIFREQXLAT2_LSB 0 +#define CSR_DFIFREQXLAT2_MASK GENMASK_32(15, 0) +#define CSR_DFIFREQXLATVAL8_LSB 0 +#define CSR_DFIFREQXLATVAL8_MASK GENMASK_32(3, 0) +#define CSR_DFIFREQXLATVAL9_LSB 4 +#define CSR_DFIFREQXLATVAL9_MASK GENMASK_32(7, 4) +#define CSR_DFIFREQXLATVAL10_LSB 8 +#define CSR_DFIFREQXLATVAL10_MASK GENMASK_32(11, 8) +#define CSR_DFIFREQXLATVAL11_LSB 12 +#define CSR_DFIFREQXLATVAL11_MASK GENMASK_32(15, 12) +/* CSR_DFIFREQXLAT3 */ +#define CSR_DFIFREQXLAT3_LSB 0 +#define CSR_DFIFREQXLAT3_MASK GENMASK_32(15, 0) +#define CSR_DFIFREQXLATVAL12_LSB 0 +#define CSR_DFIFREQXLATVAL12_MASK GENMASK_32(3, 0) +#define CSR_DFIFREQXLATVAL13_LSB 4 +#define CSR_DFIFREQXLATVAL13_MASK GENMASK_32(7, 4) +#define CSR_DFIFREQXLATVAL14_LSB 8 +#define CSR_DFIFREQXLATVAL14_MASK GENMASK_32(11, 8) +#define CSR_DFIFREQXLATVAL15_LSB 12 +#define CSR_DFIFREQXLATVAL15_MASK GENMASK_32(15, 12) +/* CSR_DFIFREQXLAT4 */ +#define CSR_DFIFREQXLAT4_LSB 0 +#define CSR_DFIFREQXLAT4_MASK GENMASK_32(15, 0) +#define CSR_DFIFREQXLATVAL16_LSB 0 +#define CSR_DFIFREQXLATVAL16_MASK GENMASK_32(3, 0) +#define CSR_DFIFREQXLATVAL17_LSB 4 +#define CSR_DFIFREQXLATVAL17_MASK GENMASK_32(7, 4) +#define CSR_DFIFREQXLATVAL18_LSB 8 +#define CSR_DFIFREQXLATVAL18_MASK GENMASK_32(11, 8) +#define CSR_DFIFREQXLATVAL19_LSB 12 +#define CSR_DFIFREQXLATVAL19_MASK GENMASK_32(15, 12) +/* CSR_DFIFREQXLAT5 */ +#define CSR_DFIFREQXLAT5_LSB 0 +#define CSR_DFIFREQXLAT5_MASK GENMASK_32(15, 0) +#define CSR_DFIFREQXLATVAL20_LSB 0 +#define CSR_DFIFREQXLATVAL20_MASK GENMASK_32(3, 0) +#define CSR_DFIFREQXLATVAL21_LSB 4 +#define CSR_DFIFREQXLATVAL21_MASK GENMASK_32(7, 4) +#define CSR_DFIFREQXLATVAL22_LSB 8 +#define CSR_DFIFREQXLATVAL22_MASK GENMASK_32(11, 8) +#define CSR_DFIFREQXLATVAL23_LSB 12 +#define CSR_DFIFREQXLATVAL23_MASK GENMASK_32(15, 12) +/* CSR_DFIFREQXLAT6 */ +#define CSR_DFIFREQXLAT6_LSB 0 +#define CSR_DFIFREQXLAT6_MASK GENMASK_32(15, 0) +#define CSR_DFIFREQXLATVAL24_LSB 0 +#define CSR_DFIFREQXLATVAL24_MASK GENMASK_32(3, 0) +#define CSR_DFIFREQXLATVAL25_LSB 4 +#define CSR_DFIFREQXLATVAL25_MASK GENMASK_32(7, 4) +#define CSR_DFIFREQXLATVAL26_LSB 8 +#define CSR_DFIFREQXLATVAL26_MASK GENMASK_32(11, 8) +#define CSR_DFIFREQXLATVAL27_LSB 12 +#define CSR_DFIFREQXLATVAL27_MASK GENMASK_32(15, 12) +/* CSR_DFIFREQXLAT7 */ +#define CSR_DFIFREQXLAT7_LSB 0 +#define CSR_DFIFREQXLAT7_MASK GENMASK_32(15, 0) +#define CSR_DFIFREQXLATVAL28_LSB 0 +#define CSR_DFIFREQXLATVAL28_MASK GENMASK_32(3, 0) +#define CSR_DFIFREQXLATVAL29_LSB 4 +#define CSR_DFIFREQXLATVAL29_MASK GENMASK_32(7, 4) +#define CSR_DFIFREQXLATVAL30_LSB 8 +#define CSR_DFIFREQXLATVAL30_MASK GENMASK_32(11, 8) +#define CSR_DFIFREQXLATVAL31_LSB 12 +#define CSR_DFIFREQXLATVAL31_MASK GENMASK_32(15, 12) +/* CSR_TXRDPTRINIT */ +#define CSR_TXRDPTRINIT_LSB 0 +#define CSR_TXRDPTRINIT_MASK BIT(0) +/* CSR_DFIINITCOMPLETE */ +#define CSR_DFIINITCOMPLETE_LSB 0 +#define CSR_DFIINITCOMPLETE_MASK BIT(0) +/* CSR_DFIFREQRATIO */ +#define CSR_DFIFREQRATIO_LSB 0 +#define CSR_DFIFREQRATIO_MASK GENMASK_32(1, 0) +/* CSR_RXFIFOCHECKS */ +#define CSR_RXFIFOCHECKS_LSB 0 +#define CSR_RXFIFOCHECKS_MASK BIT(0) +#define CSR_DOFREQUENTRXFIFOCHECKS_LSB 0 +#define CSR_DOFREQUENTRXFIFOCHECKS_MASK BIT(0) +/* CSR_MTESTDTOCTRL */ +#define CSR_MTESTDTOCTRL_LSB 0 +#define CSR_MTESTDTOCTRL_MASK BIT(0) +#define CSR_MTESTDTOEN_LSB 0 +#define CSR_MTESTDTOEN_MASK BIT(0) +/* CSR_MAPCAA0TODFI */ +#define CSR_MAPCAA0TODFI_LSB 0 +#define CSR_MAPCAA0TODFI_MASK GENMASK_32(3, 0) +/* CSR_MAPCAA1TODFI */ +#define CSR_MAPCAA1TODFI_LSB 0 +#define CSR_MAPCAA1TODFI_MASK GENMASK_32(3, 0) +/* CSR_MAPCAA2TODFI */ +#define CSR_MAPCAA2TODFI_LSB 0 +#define CSR_MAPCAA2TODFI_MASK GENMASK_32(3, 0) +/* CSR_MAPCAA3TODFI */ +#define CSR_MAPCAA3TODFI_LSB 0 +#define CSR_MAPCAA3TODFI_MASK GENMASK_32(3, 0) +/* CSR_MAPCAA4TODFI */ +#define CSR_MAPCAA4TODFI_LSB 0 +#define CSR_MAPCAA4TODFI_MASK GENMASK_32(3, 0) +/* CSR_MAPCAA5TODFI */ +#define CSR_MAPCAA5TODFI_LSB 0 +#define CSR_MAPCAA5TODFI_MASK GENMASK_32(3, 0) +/* CSR_MAPCAA6TODFI */ +#define CSR_MAPCAA6TODFI_LSB 0 +#define CSR_MAPCAA6TODFI_MASK GENMASK_32(3, 0) +/* CSR_MAPCAA7TODFI */ +#define CSR_MAPCAA7TODFI_LSB 0 +#define CSR_MAPCAA7TODFI_MASK GENMASK_32(3, 0) +/* CSR_MAPCAA8TODFI */ +#define CSR_MAPCAA8TODFI_LSB 0 +#define CSR_MAPCAA8TODFI_MASK GENMASK_32(3, 0) +/* CSR_MAPCAA9TODFI */ +#define CSR_MAPCAA9TODFI_LSB 0 +#define CSR_MAPCAA9TODFI_MASK GENMASK_32(3, 0) +/* CSR_MAPCAB0TODFI */ +#define CSR_MAPCAB0TODFI_LSB 0 +#define CSR_MAPCAB0TODFI_MASK GENMASK_32(3, 0) +/* CSR_MAPCAB1TODFI */ +#define CSR_MAPCAB1TODFI_LSB 0 +#define CSR_MAPCAB1TODFI_MASK GENMASK_32(3, 0) +/* CSR_MAPCAB2TODFI */ +#define CSR_MAPCAB2TODFI_LSB 0 +#define CSR_MAPCAB2TODFI_MASK GENMASK_32(3, 0) +/* CSR_MAPCAB3TODFI */ +#define CSR_MAPCAB3TODFI_LSB 0 +#define CSR_MAPCAB3TODFI_MASK GENMASK_32(3, 0) +/* CSR_MAPCAB4TODFI */ +#define CSR_MAPCAB4TODFI_LSB 0 +#define CSR_MAPCAB4TODFI_MASK GENMASK_32(3, 0) +/* CSR_MAPCAB5TODFI */ +#define CSR_MAPCAB5TODFI_LSB 0 +#define CSR_MAPCAB5TODFI_MASK GENMASK_32(3, 0) +/* CSR_MAPCAB6TODFI */ +#define CSR_MAPCAB6TODFI_LSB 0 +#define CSR_MAPCAB6TODFI_MASK GENMASK_32(3, 0) +/* CSR_MAPCAB7TODFI */ +#define CSR_MAPCAB7TODFI_LSB 0 +#define CSR_MAPCAB7TODFI_MASK GENMASK_32(3, 0) +/* CSR_MAPCAB8TODFI */ +#define CSR_MAPCAB8TODFI_LSB 0 +#define CSR_MAPCAB8TODFI_MASK GENMASK_32(3, 0) +/* CSR_MAPCAB9TODFI */ +#define CSR_MAPCAB9TODFI_LSB 0 +#define CSR_MAPCAB9TODFI_MASK GENMASK_32(3, 0) +/* CSR_PHYINTERRUPTENABLE */ +#define CSR_PHYINTERRUPTENABLE_LSB 0 +#define CSR_PHYINTERRUPTENABLE_MASK GENMASK_32(15, 0) +#define CSR_PHYTRNGCMPLTEN_LSB 0 +#define CSR_PHYTRNGCMPLTEN_MASK BIT(0) +#define CSR_PHYINITCMPLTEN_LSB 1 +#define CSR_PHYINITCMPLTEN_MASK BIT(1) +#define CSR_PHYTRNGFAILEN_LSB 2 +#define CSR_PHYTRNGFAILEN_MASK BIT(2) +#define CSR_PHYFWRESERVEDEN_LSB 3 +#define CSR_PHYFWRESERVEDEN_MASK GENMASK_32(7, 3) +#define CSR_PHYVTDRIFTALARMEN_LSB 8 +#define CSR_PHYVTDRIFTALARMEN_MASK GENMASK_32(9, 8) +#define CSR_PHYRXFIFOCHECKEN_LSB 10 +#define CSR_PHYRXFIFOCHECKEN_MASK BIT(10) +#define CSR_PHYHWRESERVEDEN_LSB 11 +#define CSR_PHYHWRESERVEDEN_MASK GENMASK_32(15, 11) +/* CSR_PHYINTERRUPTFWCONTROL */ +#define CSR_PHYINTERRUPTFWCONTROL_LSB 0 +#define CSR_PHYINTERRUPTFWCONTROL_MASK GENMASK_32(7, 0) +#define CSR_PHYTRNGCMPLTFW_LSB 0 +#define CSR_PHYTRNGCMPLTFW_MASK BIT(0) +#define CSR_PHYINITCMPLTFW_LSB 1 +#define CSR_PHYINITCMPLTFW_MASK BIT(1) +#define CSR_PHYTRNGFAILFW_LSB 2 +#define CSR_PHYTRNGFAILFW_MASK BIT(2) +#define CSR_PHYFWRESERVEDFW_LSB 3 +#define CSR_PHYFWRESERVEDFW_MASK GENMASK_32(7, 3) +/* CSR_PHYINTERRUPTMASK */ +#define CSR_PHYINTERRUPTMASK_LSB 0 +#define CSR_PHYINTERRUPTMASK_MASK GENMASK_32(15, 0) +#define CSR_PHYTRNGCMPLTMSK_LSB 0 +#define CSR_PHYTRNGCMPLTMSK_MASK BIT(0) +#define CSR_PHYINITCMPLTMSK_LSB 1 +#define CSR_PHYINITCMPLTMSK_MASK BIT(1) +#define CSR_PHYTRNGFAILMSK_LSB 2 +#define CSR_PHYTRNGFAILMSK_MASK BIT(2) +#define CSR_PHYFWRESERVEDMSK_LSB 3 +#define CSR_PHYFWRESERVEDMSK_MASK GENMASK_32(7, 3) +#define CSR_PHYVTDRIFTALARMMSK_LSB 8 +#define CSR_PHYVTDRIFTALARMMSK_MASK GENMASK_32(9, 8) +#define CSR_PHYRXFIFOCHECKMSK_LSB 10 +#define CSR_PHYRXFIFOCHECKMSK_MASK BIT(10) +#define CSR_PHYHWRESERVEDMSK_LSB 11 +#define CSR_PHYHWRESERVEDMSK_MASK GENMASK_32(15, 11) +/* CSR_PHYINTERRUPTCLEAR */ +#define CSR_PHYINTERRUPTCLEAR_LSB 0 +#define CSR_PHYINTERRUPTCLEAR_MASK GENMASK_32(15, 0) +#define CSR_PHYTRNGCMPLTCLR_LSB 0 +#define CSR_PHYTRNGCMPLTCLR_MASK BIT(0) +#define CSR_PHYINITCMPLTCLR_LSB 1 +#define CSR_PHYINITCMPLTCLR_MASK BIT(1) +#define CSR_PHYTRNGFAILCLR_LSB 2 +#define CSR_PHYTRNGFAILCLR_MASK BIT(2) +#define CSR_PHYFWRESERVEDCLR_LSB 3 +#define CSR_PHYFWRESERVEDCLR_MASK GENMASK_32(7, 3) +#define CSR_PHYVTDRIFTALARMCLR_LSB 8 +#define CSR_PHYVTDRIFTALARMCLR_MASK GENMASK_32(9, 8) +#define CSR_PHYRXFIFOCHECKCLR_LSB 10 +#define CSR_PHYRXFIFOCHECKCLR_MASK BIT(10) +#define CSR_PHYHWRESERVEDCLR_LSB 11 +#define CSR_PHYHWRESERVEDCLR_MASK GENMASK_32(15, 11) +/* CSR_PHYINTERRUPTSTATUS */ +#define CSR_PHYINTERRUPTSTATUS_LSB 0 +#define CSR_PHYINTERRUPTSTATUS_MASK GENMASK_32(15, 0) +#define CSR_PHYTRNGCMPLT_LSB 0 +#define CSR_PHYTRNGCMPLT_MASK BIT(0) +#define CSR_PHYINITCMPLT_LSB 1 +#define CSR_PHYINITCMPLT_MASK BIT(1) +#define CSR_PHYTRNGFAIL_LSB 2 +#define CSR_PHYTRNGFAIL_MASK BIT(2) +#define CSR_PHYFWRESERVED_LSB 3 +#define CSR_PHYFWRESERVED_MASK GENMASK_32(7, 3) +#define CSR_VTDRIFTALARM_LSB 8 +#define CSR_VTDRIFTALARM_MASK GENMASK_32(9, 8) +#define CSR_PHYRXFIFOCHECK_LSB 10 +#define CSR_PHYRXFIFOCHECK_MASK BIT(10) +#define CSR_PHYHWRESERVED_LSB 11 +#define CSR_PHYHWRESERVED_MASK GENMASK_32(15, 11) +/* CSR_HWTSWIZZLEHWTADDRESS0 */ +#define CSR_HWTSWIZZLEHWTADDRESS0_LSB 0 +#define CSR_HWTSWIZZLEHWTADDRESS0_MASK GENMASK_32(4, 0) +/* CSR_HWTSWIZZLEHWTADDRESS1 */ +#define CSR_HWTSWIZZLEHWTADDRESS1_LSB 0 +#define CSR_HWTSWIZZLEHWTADDRESS1_MASK GENMASK_32(4, 0) +/* CSR_HWTSWIZZLEHWTADDRESS2 */ +#define CSR_HWTSWIZZLEHWTADDRESS2_LSB 0 +#define CSR_HWTSWIZZLEHWTADDRESS2_MASK GENMASK_32(4, 0) +/* CSR_HWTSWIZZLEHWTADDRESS3 */ +#define CSR_HWTSWIZZLEHWTADDRESS3_LSB 0 +#define CSR_HWTSWIZZLEHWTADDRESS3_MASK GENMASK_32(4, 0) +/* CSR_HWTSWIZZLEHWTADDRESS4 */ +#define CSR_HWTSWIZZLEHWTADDRESS4_LSB 0 +#define CSR_HWTSWIZZLEHWTADDRESS4_MASK GENMASK_32(4, 0) +/* CSR_HWTSWIZZLEHWTADDRESS5 */ +#define CSR_HWTSWIZZLEHWTADDRESS5_LSB 0 +#define CSR_HWTSWIZZLEHWTADDRESS5_MASK GENMASK_32(4, 0) +/* CSR_HWTSWIZZLEHWTADDRESS6 */ +#define CSR_HWTSWIZZLEHWTADDRESS6_LSB 0 +#define CSR_HWTSWIZZLEHWTADDRESS6_MASK GENMASK_32(4, 0) +/* CSR_HWTSWIZZLEHWTADDRESS7 */ +#define CSR_HWTSWIZZLEHWTADDRESS7_LSB 0 +#define CSR_HWTSWIZZLEHWTADDRESS7_MASK GENMASK_32(4, 0) +/* CSR_HWTSWIZZLEHWTADDRESS8 */ +#define CSR_HWTSWIZZLEHWTADDRESS8_LSB 0 +#define CSR_HWTSWIZZLEHWTADDRESS8_MASK GENMASK_32(4, 0) +/* CSR_HWTSWIZZLEHWTADDRESS9 */ +#define CSR_HWTSWIZZLEHWTADDRESS9_LSB 0 +#define CSR_HWTSWIZZLEHWTADDRESS9_MASK GENMASK_32(4, 0) +/* CSR_HWTSWIZZLEHWTADDRESS10 */ +#define CSR_HWTSWIZZLEHWTADDRESS10_LSB 0 +#define CSR_HWTSWIZZLEHWTADDRESS10_MASK GENMASK_32(4, 0) +/* CSR_HWTSWIZZLEHWTADDRESS11 */ +#define CSR_HWTSWIZZLEHWTADDRESS11_LSB 0 +#define CSR_HWTSWIZZLEHWTADDRESS11_MASK GENMASK_32(4, 0) +/* CSR_HWTSWIZZLEHWTADDRESS12 */ +#define CSR_HWTSWIZZLEHWTADDRESS12_LSB 0 +#define CSR_HWTSWIZZLEHWTADDRESS12_MASK GENMASK_32(4, 0) +/* CSR_HWTSWIZZLEHWTADDRESS13 */ +#define CSR_HWTSWIZZLEHWTADDRESS13_LSB 0 +#define CSR_HWTSWIZZLEHWTADDRESS13_MASK GENMASK_32(4, 0) +/* CSR_HWTSWIZZLEHWTADDRESS14 */ +#define CSR_HWTSWIZZLEHWTADDRESS14_LSB 0 +#define CSR_HWTSWIZZLEHWTADDRESS14_MASK GENMASK_32(4, 0) +/* CSR_HWTSWIZZLEHWTADDRESS15 */ +#define CSR_HWTSWIZZLEHWTADDRESS15_LSB 0 +#define CSR_HWTSWIZZLEHWTADDRESS15_MASK GENMASK_32(4, 0) +/* CSR_HWTSWIZZLEHWTADDRESS17 */ +#define CSR_HWTSWIZZLEHWTADDRESS17_LSB 0 +#define CSR_HWTSWIZZLEHWTADDRESS17_MASK GENMASK_32(4, 0) +/* CSR_HWTSWIZZLEHWTACTN */ +#define CSR_HWTSWIZZLEHWTACTN_LSB 0 +#define CSR_HWTSWIZZLEHWTACTN_MASK GENMASK_32(4, 0) +/* CSR_HWTSWIZZLEHWTBANK0 */ +#define CSR_HWTSWIZZLEHWTBANK0_LSB 0 +#define CSR_HWTSWIZZLEHWTBANK0_MASK GENMASK_32(4, 0) +/* CSR_HWTSWIZZLEHWTBANK1 */ +#define CSR_HWTSWIZZLEHWTBANK1_LSB 0 +#define CSR_HWTSWIZZLEHWTBANK1_MASK GENMASK_32(4, 0) +/* CSR_HWTSWIZZLEHWTBANK2 */ +#define CSR_HWTSWIZZLEHWTBANK2_LSB 0 +#define CSR_HWTSWIZZLEHWTBANK2_MASK GENMASK_32(4, 0) +/* CSR_HWTSWIZZLEHWTBG0 */ +#define CSR_HWTSWIZZLEHWTBG0_LSB 0 +#define CSR_HWTSWIZZLEHWTBG0_MASK GENMASK_32(4, 0) +/* CSR_HWTSWIZZLEHWTBG1 */ +#define CSR_HWTSWIZZLEHWTBG1_LSB 0 +#define CSR_HWTSWIZZLEHWTBG1_MASK GENMASK_32(4, 0) +/* CSR_HWTSWIZZLEHWTCASN */ +#define CSR_HWTSWIZZLEHWTCASN_LSB 0 +#define CSR_HWTSWIZZLEHWTCASN_MASK GENMASK_32(4, 0) +/* CSR_HWTSWIZZLEHWTRASN */ +#define CSR_HWTSWIZZLEHWTRASN_LSB 0 +#define CSR_HWTSWIZZLEHWTRASN_MASK GENMASK_32(4, 0) +/* CSR_HWTSWIZZLEHWTWEN */ +#define CSR_HWTSWIZZLEHWTWEN_LSB 0 +#define CSR_HWTSWIZZLEHWTWEN_MASK GENMASK_32(4, 0) +/* CSR_HWTSWIZZLEHWTPARITYIN */ +#define CSR_HWTSWIZZLEHWTPARITYIN_LSB 0 +#define CSR_HWTSWIZZLEHWTPARITYIN_MASK GENMASK_32(4, 0) +/* CSR_DFIHANDSHAKEDELAYS0 */ +#define CSR_DFIHANDSHAKEDELAYS0_LSB 0 +#define CSR_DFIHANDSHAKEDELAYS0_MASK GENMASK_32(15, 0) +#define CSR_PHYUPDACKDELAY0_LSB 0 +#define CSR_PHYUPDACKDELAY0_MASK GENMASK_32(3, 0) +#define CSR_PHYUPDREQDELAY0_LSB 4 +#define CSR_PHYUPDREQDELAY0_MASK GENMASK_32(7, 4) +#define CSR_CTRLUPDACKDELAY0_LSB 8 +#define CSR_CTRLUPDACKDELAY0_MASK GENMASK_32(11, 8) +#define CSR_CTRLUPDREQDELAY0_LSB 12 +#define CSR_CTRLUPDREQDELAY0_MASK GENMASK_32(15, 12) +/* CSR_DFIHANDSHAKEDELAYS1 */ +#define CSR_DFIHANDSHAKEDELAYS1_LSB 0 +#define CSR_DFIHANDSHAKEDELAYS1_MASK GENMASK_32(15, 0) +#define CSR_PHYUPDACKDELAY1_LSB 0 +#define CSR_PHYUPDACKDELAY1_MASK GENMASK_32(3, 0) +#define CSR_PHYUPDREQDELAY1_LSB 4 +#define CSR_PHYUPDREQDELAY1_MASK GENMASK_32(7, 4) +#define CSR_CTRLUPDACKDELAY1_LSB 8 +#define CSR_CTRLUPDACKDELAY1_MASK GENMASK_32(11, 8) +#define CSR_CTRLUPDREQDELAY1_LSB 12 +#define CSR_CTRLUPDREQDELAY1_MASK GENMASK_32(15, 12) +/* CSR_REMOTEIMPCAL */ +#define CSR_REMOTEIMPCAL_LSB 0 +#define CSR_REMOTEIMPCAL_MASK GENMASK_32(1, 0) +#define CSR_CALIBSLAVE_LSB 0 +#define CSR_CALIBSLAVE_MASK BIT(0) +#define CSR_SLAVECODEUPDATED_LSB 1 +#define CSR_SLAVECODEUPDATED_MASK BIT(1) +/* CSR_ACLOOPBACKCTL */ +#define CSR_ACLOOPBACKCTL_LSB 0 +#define CSR_ACLOOPBACKCTL_MASK GENMASK_32(1, 0) +#define CSR_TERMINATION_LSB 0 +#define CSR_TERMINATION_MASK BIT(0) +#define CSR_NOISECANCEL_LSB 1 +#define CSR_NOISECANCEL_MASK BIT(1) + +/* ACSM0 register offsets */ +/* CSR_ACSMSEQ0X0 */ +#define CSR_ACSMSEQ0X0_LSB 0 +#define CSR_ACSMSEQ0X0_MASK GENMASK_32(15, 0) +#define CSR_ACSMMCLKDLY0_LSB 0 +#define CSR_ACSMMCLKDLY0_MASK GENMASK_32(7, 0) +#define CSR_ACSMDDRWE0_LSB 8 +#define CSR_ACSMDDRWE0_MASK BIT(8) +#define CSR_ACSMDDRCAS0_LSB 9 +#define CSR_ACSMDDRCAS0_MASK BIT(9) +#define CSR_ACSMDDRRAS0_LSB 10 +#define CSR_ACSMDDRRAS0_MASK BIT(10) +#define CSR_ACSMDDRCKESET0_LSB 11 +#define CSR_ACSMDDRCKESET0_MASK BIT(11) +#define CSR_ACSMDDRCKECLR0_LSB 12 +#define CSR_ACSMDDRCKECLR0_MASK BIT(12) +#define CSR_ACSMSEQGATECMD0_LSB 13 +#define CSR_ACSMSEQGATECMD0_MASK BIT(13) +#define CSR_ACSMSEQTERM0_LSB 14 +#define CSR_ACSMSEQTERM0_MASK BIT(14) +#define CSR_ACSMLP3CA30_LSB 15 +#define CSR_ACSMLP3CA30_MASK BIT(15) +/* CSR_ACSMSEQ0X1 */ +#define CSR_ACSMSEQ0X1_LSB 0 +#define CSR_ACSMSEQ0X1_MASK GENMASK_32(15, 0) +#define CSR_ACSMMCLKDLY1_LSB 0 +#define CSR_ACSMMCLKDLY1_MASK GENMASK_32(7, 0) +#define CSR_ACSMDDRWE1_LSB 8 +#define CSR_ACSMDDRWE1_MASK BIT(8) +#define CSR_ACSMDDRCAS1_LSB 9 +#define CSR_ACSMDDRCAS1_MASK BIT(9) +#define CSR_ACSMDDRRAS1_LSB 10 +#define CSR_ACSMDDRRAS1_MASK BIT(10) +#define CSR_ACSMDDRCKESET1_LSB 11 +#define CSR_ACSMDDRCKESET1_MASK BIT(11) +#define CSR_ACSMDDRCKECLR1_LSB 12 +#define CSR_ACSMDDRCKECLR1_MASK BIT(12) +#define CSR_ACSMSEQGATECMD1_LSB 13 +#define CSR_ACSMSEQGATECMD1_MASK BIT(13) +#define CSR_ACSMSEQTERM1_LSB 14 +#define CSR_ACSMSEQTERM1_MASK BIT(14) +#define CSR_ACSMLP3CA31_LSB 15 +#define CSR_ACSMLP3CA31_MASK BIT(15) +/* CSR_ACSMSEQ0X2 */ +#define CSR_ACSMSEQ0X2_LSB 0 +#define CSR_ACSMSEQ0X2_MASK GENMASK_32(15, 0) +#define CSR_ACSMMCLKDLY2_LSB 0 +#define CSR_ACSMMCLKDLY2_MASK GENMASK_32(7, 0) +#define CSR_ACSMDDRWE2_LSB 8 +#define CSR_ACSMDDRWE2_MASK BIT(8) +#define CSR_ACSMDDRCAS2_LSB 9 +#define CSR_ACSMDDRCAS2_MASK BIT(9) +#define CSR_ACSMDDRRAS2_LSB 10 +#define CSR_ACSMDDRRAS2_MASK BIT(10) +#define CSR_ACSMDDRCKESET2_LSB 11 +#define CSR_ACSMDDRCKESET2_MASK BIT(11) +#define CSR_ACSMDDRCKECLR2_LSB 12 +#define CSR_ACSMDDRCKECLR2_MASK BIT(12) +#define CSR_ACSMSEQGATECMD2_LSB 13 +#define CSR_ACSMSEQGATECMD2_MASK BIT(13) +#define CSR_ACSMSEQTERM2_LSB 14 +#define CSR_ACSMSEQTERM2_MASK BIT(14) +#define CSR_ACSMLP3CA32_LSB 15 +#define CSR_ACSMLP3CA32_MASK BIT(15) +/* CSR_ACSMSEQ0X3 */ +#define CSR_ACSMSEQ0X3_LSB 0 +#define CSR_ACSMSEQ0X3_MASK GENMASK_32(15, 0) +#define CSR_ACSMMCLKDLY3_LSB 0 +#define CSR_ACSMMCLKDLY3_MASK GENMASK_32(7, 0) +#define CSR_ACSMDDRWE3_LSB 8 +#define CSR_ACSMDDRWE3_MASK BIT(8) +#define CSR_ACSMDDRCAS3_LSB 9 +#define CSR_ACSMDDRCAS3_MASK BIT(9) +#define CSR_ACSMDDRRAS3_LSB 10 +#define CSR_ACSMDDRRAS3_MASK BIT(10) +#define CSR_ACSMDDRCKESET3_LSB 11 +#define CSR_ACSMDDRCKESET3_MASK BIT(11) +#define CSR_ACSMDDRCKECLR3_LSB 12 +#define CSR_ACSMDDRCKECLR3_MASK BIT(12) +#define CSR_ACSMSEQGATECMD3_LSB 13 +#define CSR_ACSMSEQGATECMD3_MASK BIT(13) +#define CSR_ACSMSEQTERM3_LSB 14 +#define CSR_ACSMSEQTERM3_MASK BIT(14) +#define CSR_ACSMLP3CA33_LSB 15 +#define CSR_ACSMLP3CA33_MASK BIT(15) +/* CSR_ACSMSEQ0X4 */ +#define CSR_ACSMSEQ0X4_LSB 0 +#define CSR_ACSMSEQ0X4_MASK GENMASK_32(15, 0) +#define CSR_ACSMMCLKDLY4_LSB 0 +#define CSR_ACSMMCLKDLY4_MASK GENMASK_32(7, 0) +#define CSR_ACSMDDRWE4_LSB 8 +#define CSR_ACSMDDRWE4_MASK BIT(8) +#define CSR_ACSMDDRCAS4_LSB 9 +#define CSR_ACSMDDRCAS4_MASK BIT(9) +#define CSR_ACSMDDRRAS4_LSB 10 +#define CSR_ACSMDDRRAS4_MASK BIT(10) +#define CSR_ACSMDDRCKESET4_LSB 11 +#define CSR_ACSMDDRCKESET4_MASK BIT(11) +#define CSR_ACSMDDRCKECLR4_LSB 12 +#define CSR_ACSMDDRCKECLR4_MASK BIT(12) +#define CSR_ACSMSEQGATECMD4_LSB 13 +#define CSR_ACSMSEQGATECMD4_MASK BIT(13) +#define CSR_ACSMSEQTERM4_LSB 14 +#define CSR_ACSMSEQTERM4_MASK BIT(14) +#define CSR_ACSMLP3CA34_LSB 15 +#define CSR_ACSMLP3CA34_MASK BIT(15) +/* CSR_ACSMSEQ0X5 */ +#define CSR_ACSMSEQ0X5_LSB 0 +#define CSR_ACSMSEQ0X5_MASK GENMASK_32(15, 0) +#define CSR_ACSMMCLKDLY5_LSB 0 +#define CSR_ACSMMCLKDLY5_MASK GENMASK_32(7, 0) +#define CSR_ACSMDDRWE5_LSB 8 +#define CSR_ACSMDDRWE5_MASK BIT(8) +#define CSR_ACSMDDRCAS5_LSB 9 +#define CSR_ACSMDDRCAS5_MASK BIT(9) +#define CSR_ACSMDDRRAS5_LSB 10 +#define CSR_ACSMDDRRAS5_MASK BIT(10) +#define CSR_ACSMDDRCKESET5_LSB 11 +#define CSR_ACSMDDRCKESET5_MASK BIT(11) +#define CSR_ACSMDDRCKECLR5_LSB 12 +#define CSR_ACSMDDRCKECLR5_MASK BIT(12) +#define CSR_ACSMSEQGATECMD5_LSB 13 +#define CSR_ACSMSEQGATECMD5_MASK BIT(13) +#define CSR_ACSMSEQTERM5_LSB 14 +#define CSR_ACSMSEQTERM5_MASK BIT(14) +#define CSR_ACSMLP3CA35_LSB 15 +#define CSR_ACSMLP3CA35_MASK BIT(15) +/* CSR_ACSMSEQ0X6 */ +#define CSR_ACSMSEQ0X6_LSB 0 +#define CSR_ACSMSEQ0X6_MASK GENMASK_32(15, 0) +#define CSR_ACSMMCLKDLY6_LSB 0 +#define CSR_ACSMMCLKDLY6_MASK GENMASK_32(7, 0) +#define CSR_ACSMDDRWE6_LSB 8 +#define CSR_ACSMDDRWE6_MASK BIT(8) +#define CSR_ACSMDDRCAS6_LSB 9 +#define CSR_ACSMDDRCAS6_MASK BIT(9) +#define CSR_ACSMDDRRAS6_LSB 10 +#define CSR_ACSMDDRRAS6_MASK BIT(10) +#define CSR_ACSMDDRCKESET6_LSB 11 +#define CSR_ACSMDDRCKESET6_MASK BIT(11) +#define CSR_ACSMDDRCKECLR6_LSB 12 +#define CSR_ACSMDDRCKECLR6_MASK BIT(12) +#define CSR_ACSMSEQGATECMD6_LSB 13 +#define CSR_ACSMSEQGATECMD6_MASK BIT(13) +#define CSR_ACSMSEQTERM6_LSB 14 +#define CSR_ACSMSEQTERM6_MASK BIT(14) +#define CSR_ACSMLP3CA36_LSB 15 +#define CSR_ACSMLP3CA36_MASK BIT(15) +/* CSR_ACSMSEQ0X7 */ +#define CSR_ACSMSEQ0X7_LSB 0 +#define CSR_ACSMSEQ0X7_MASK GENMASK_32(15, 0) +#define CSR_ACSMMCLKDLY7_LSB 0 +#define CSR_ACSMMCLKDLY7_MASK GENMASK_32(7, 0) +#define CSR_ACSMDDRWE7_LSB 8 +#define CSR_ACSMDDRWE7_MASK BIT(8) +#define CSR_ACSMDDRCAS7_LSB 9 +#define CSR_ACSMDDRCAS7_MASK BIT(9) +#define CSR_ACSMDDRRAS7_LSB 10 +#define CSR_ACSMDDRRAS7_MASK BIT(10) +#define CSR_ACSMDDRCKESET7_LSB 11 +#define CSR_ACSMDDRCKESET7_MASK BIT(11) +#define CSR_ACSMDDRCKECLR7_LSB 12 +#define CSR_ACSMDDRCKECLR7_MASK BIT(12) +#define CSR_ACSMSEQGATECMD7_LSB 13 +#define CSR_ACSMSEQGATECMD7_MASK BIT(13) +#define CSR_ACSMSEQTERM7_LSB 14 +#define CSR_ACSMSEQTERM7_MASK BIT(14) +#define CSR_ACSMLP3CA37_LSB 15 +#define CSR_ACSMLP3CA37_MASK BIT(15) +/* CSR_ACSMSEQ0X8 */ +#define CSR_ACSMSEQ0X8_LSB 0 +#define CSR_ACSMSEQ0X8_MASK GENMASK_32(15, 0) +#define CSR_ACSMMCLKDLY8_LSB 0 +#define CSR_ACSMMCLKDLY8_MASK GENMASK_32(7, 0) +#define CSR_ACSMDDRWE8_LSB 8 +#define CSR_ACSMDDRWE8_MASK BIT(8) +#define CSR_ACSMDDRCAS8_LSB 9 +#define CSR_ACSMDDRCAS8_MASK BIT(9) +#define CSR_ACSMDDRRAS8_LSB 10 +#define CSR_ACSMDDRRAS8_MASK BIT(10) +#define CSR_ACSMDDRCKESET8_LSB 11 +#define CSR_ACSMDDRCKESET8_MASK BIT(11) +#define CSR_ACSMDDRCKECLR8_LSB 12 +#define CSR_ACSMDDRCKECLR8_MASK BIT(12) +#define CSR_ACSMSEQGATECMD8_LSB 13 +#define CSR_ACSMSEQGATECMD8_MASK BIT(13) +#define CSR_ACSMSEQTERM8_LSB 14 +#define CSR_ACSMSEQTERM8_MASK BIT(14) +#define CSR_ACSMLP3CA38_LSB 15 +#define CSR_ACSMLP3CA38_MASK BIT(15) +/* CSR_ACSMSEQ0X9 */ +#define CSR_ACSMSEQ0X9_LSB 0 +#define CSR_ACSMSEQ0X9_MASK GENMASK_32(15, 0) +#define CSR_ACSMMCLKDLY9_LSB 0 +#define CSR_ACSMMCLKDLY9_MASK GENMASK_32(7, 0) +#define CSR_ACSMDDRWE9_LSB 8 +#define CSR_ACSMDDRWE9_MASK BIT(8) +#define CSR_ACSMDDRCAS9_LSB 9 +#define CSR_ACSMDDRCAS9_MASK BIT(9) +#define CSR_ACSMDDRRAS9_LSB 10 +#define CSR_ACSMDDRRAS9_MASK BIT(10) +#define CSR_ACSMDDRCKESET9_LSB 11 +#define CSR_ACSMDDRCKESET9_MASK BIT(11) +#define CSR_ACSMDDRCKECLR9_LSB 12 +#define CSR_ACSMDDRCKECLR9_MASK BIT(12) +#define CSR_ACSMSEQGATECMD9_LSB 13 +#define CSR_ACSMSEQGATECMD9_MASK BIT(13) +#define CSR_ACSMSEQTERM9_LSB 14 +#define CSR_ACSMSEQTERM9_MASK BIT(14) +#define CSR_ACSMLP3CA39_LSB 15 +#define CSR_ACSMLP3CA39_MASK BIT(15) +/* CSR_ACSMSEQ0X10 */ +#define CSR_ACSMSEQ0X10_LSB 0 +#define CSR_ACSMSEQ0X10_MASK GENMASK_32(15, 0) +#define CSR_ACSMMCLKDLY10_LSB 0 +#define CSR_ACSMMCLKDLY10_MASK GENMASK_32(7, 0) +#define CSR_ACSMDDRWE10_LSB 8 +#define CSR_ACSMDDRWE10_MASK BIT(8) +#define CSR_ACSMDDRCAS10_LSB 9 +#define CSR_ACSMDDRCAS10_MASK BIT(9) +#define CSR_ACSMDDRRAS10_LSB 10 +#define CSR_ACSMDDRRAS10_MASK BIT(10) +#define CSR_ACSMDDRCKESET10_LSB 11 +#define CSR_ACSMDDRCKESET10_MASK BIT(11) +#define CSR_ACSMDDRCKECLR10_LSB 12 +#define CSR_ACSMDDRCKECLR10_MASK BIT(12) +#define CSR_ACSMSEQGATECMD10_LSB 13 +#define CSR_ACSMSEQGATECMD10_MASK BIT(13) +#define CSR_ACSMSEQTERM10_LSB 14 +#define CSR_ACSMSEQTERM10_MASK BIT(14) +#define CSR_ACSMLP3CA310_LSB 15 +#define CSR_ACSMLP3CA310_MASK BIT(15) +/* CSR_ACSMSEQ0X11 */ +#define CSR_ACSMSEQ0X11_LSB 0 +#define CSR_ACSMSEQ0X11_MASK GENMASK_32(15, 0) +#define CSR_ACSMMCLKDLY11_LSB 0 +#define CSR_ACSMMCLKDLY11_MASK GENMASK_32(7, 0) +#define CSR_ACSMDDRWE11_LSB 8 +#define CSR_ACSMDDRWE11_MASK BIT(8) +#define CSR_ACSMDDRCAS11_LSB 9 +#define CSR_ACSMDDRCAS11_MASK BIT(9) +#define CSR_ACSMDDRRAS11_LSB 10 +#define CSR_ACSMDDRRAS11_MASK BIT(10) +#define CSR_ACSMDDRCKESET11_LSB 11 +#define CSR_ACSMDDRCKESET11_MASK BIT(11) +#define CSR_ACSMDDRCKECLR11_LSB 12 +#define CSR_ACSMDDRCKECLR11_MASK BIT(12) +#define CSR_ACSMSEQGATECMD11_LSB 13 +#define CSR_ACSMSEQGATECMD11_MASK BIT(13) +#define CSR_ACSMSEQTERM11_LSB 14 +#define CSR_ACSMSEQTERM11_MASK BIT(14) +#define CSR_ACSMLP3CA311_LSB 15 +#define CSR_ACSMLP3CA311_MASK BIT(15) +/* CSR_ACSMSEQ0X12 */ +#define CSR_ACSMSEQ0X12_LSB 0 +#define CSR_ACSMSEQ0X12_MASK GENMASK_32(15, 0) +#define CSR_ACSMMCLKDLY12_LSB 0 +#define CSR_ACSMMCLKDLY12_MASK GENMASK_32(7, 0) +#define CSR_ACSMDDRWE12_LSB 8 +#define CSR_ACSMDDRWE12_MASK BIT(8) +#define CSR_ACSMDDRCAS12_LSB 9 +#define CSR_ACSMDDRCAS12_MASK BIT(9) +#define CSR_ACSMDDRRAS12_LSB 10 +#define CSR_ACSMDDRRAS12_MASK BIT(10) +#define CSR_ACSMDDRCKESET12_LSB 11 +#define CSR_ACSMDDRCKESET12_MASK BIT(11) +#define CSR_ACSMDDRCKECLR12_LSB 12 +#define CSR_ACSMDDRCKECLR12_MASK BIT(12) +#define CSR_ACSMSEQGATECMD12_LSB 13 +#define CSR_ACSMSEQGATECMD12_MASK BIT(13) +#define CSR_ACSMSEQTERM12_LSB 14 +#define CSR_ACSMSEQTERM12_MASK BIT(14) +#define CSR_ACSMLP3CA312_LSB 15 +#define CSR_ACSMLP3CA312_MASK BIT(15) +/* CSR_ACSMSEQ0X13 */ +#define CSR_ACSMSEQ0X13_LSB 0 +#define CSR_ACSMSEQ0X13_MASK GENMASK_32(15, 0) +#define CSR_ACSMMCLKDLY13_LSB 0 +#define CSR_ACSMMCLKDLY13_MASK GENMASK_32(7, 0) +#define CSR_ACSMDDRWE13_LSB 8 +#define CSR_ACSMDDRWE13_MASK BIT(8) +#define CSR_ACSMDDRCAS13_LSB 9 +#define CSR_ACSMDDRCAS13_MASK BIT(9) +#define CSR_ACSMDDRRAS13_LSB 10 +#define CSR_ACSMDDRRAS13_MASK BIT(10) +#define CSR_ACSMDDRCKESET13_LSB 11 +#define CSR_ACSMDDRCKESET13_MASK BIT(11) +#define CSR_ACSMDDRCKECLR13_LSB 12 +#define CSR_ACSMDDRCKECLR13_MASK BIT(12) +#define CSR_ACSMSEQGATECMD13_LSB 13 +#define CSR_ACSMSEQGATECMD13_MASK BIT(13) +#define CSR_ACSMSEQTERM13_LSB 14 +#define CSR_ACSMSEQTERM13_MASK BIT(14) +#define CSR_ACSMLP3CA313_LSB 15 +#define CSR_ACSMLP3CA313_MASK BIT(15) +/* CSR_ACSMSEQ0X14 */ +#define CSR_ACSMSEQ0X14_LSB 0 +#define CSR_ACSMSEQ0X14_MASK GENMASK_32(15, 0) +#define CSR_ACSMMCLKDLY14_LSB 0 +#define CSR_ACSMMCLKDLY14_MASK GENMASK_32(7, 0) +#define CSR_ACSMDDRWE14_LSB 8 +#define CSR_ACSMDDRWE14_MASK BIT(8) +#define CSR_ACSMDDRCAS14_LSB 9 +#define CSR_ACSMDDRCAS14_MASK BIT(9) +#define CSR_ACSMDDRRAS14_LSB 10 +#define CSR_ACSMDDRRAS14_MASK BIT(10) +#define CSR_ACSMDDRCKESET14_LSB 11 +#define CSR_ACSMDDRCKESET14_MASK BIT(11) +#define CSR_ACSMDDRCKECLR14_LSB 12 +#define CSR_ACSMDDRCKECLR14_MASK BIT(12) +#define CSR_ACSMSEQGATECMD14_LSB 13 +#define CSR_ACSMSEQGATECMD14_MASK BIT(13) +#define CSR_ACSMSEQTERM14_LSB 14 +#define CSR_ACSMSEQTERM14_MASK BIT(14) +#define CSR_ACSMLP3CA314_LSB 15 +#define CSR_ACSMLP3CA314_MASK BIT(15) +/* CSR_ACSMSEQ0X15 */ +#define CSR_ACSMSEQ0X15_LSB 0 +#define CSR_ACSMSEQ0X15_MASK GENMASK_32(15, 0) +#define CSR_ACSMMCLKDLY15_LSB 0 +#define CSR_ACSMMCLKDLY15_MASK GENMASK_32(7, 0) +#define CSR_ACSMDDRWE15_LSB 8 +#define CSR_ACSMDDRWE15_MASK BIT(8) +#define CSR_ACSMDDRCAS15_LSB 9 +#define CSR_ACSMDDRCAS15_MASK BIT(9) +#define CSR_ACSMDDRRAS15_LSB 10 +#define CSR_ACSMDDRRAS15_MASK BIT(10) +#define CSR_ACSMDDRCKESET15_LSB 11 +#define CSR_ACSMDDRCKESET15_MASK BIT(11) +#define CSR_ACSMDDRCKECLR15_LSB 12 +#define CSR_ACSMDDRCKECLR15_MASK BIT(12) +#define CSR_ACSMSEQGATECMD15_LSB 13 +#define CSR_ACSMSEQGATECMD15_MASK BIT(13) +#define CSR_ACSMSEQTERM15_LSB 14 +#define CSR_ACSMSEQTERM15_MASK BIT(14) +#define CSR_ACSMLP3CA315_LSB 15 +#define CSR_ACSMLP3CA315_MASK BIT(15) +/* CSR_ACSMSEQ0X16 */ +#define CSR_ACSMSEQ0X16_LSB 0 +#define CSR_ACSMSEQ0X16_MASK GENMASK_32(15, 0) +#define CSR_ACSMMCLKDLY16_LSB 0 +#define CSR_ACSMMCLKDLY16_MASK GENMASK_32(7, 0) +#define CSR_ACSMDDRWE16_LSB 8 +#define CSR_ACSMDDRWE16_MASK BIT(8) +#define CSR_ACSMDDRCAS16_LSB 9 +#define CSR_ACSMDDRCAS16_MASK BIT(9) +#define CSR_ACSMDDRRAS16_LSB 10 +#define CSR_ACSMDDRRAS16_MASK BIT(10) +#define CSR_ACSMDDRCKESET16_LSB 11 +#define CSR_ACSMDDRCKESET16_MASK BIT(11) +#define CSR_ACSMDDRCKECLR16_LSB 12 +#define CSR_ACSMDDRCKECLR16_MASK BIT(12) +#define CSR_ACSMSEQGATECMD16_LSB 13 +#define CSR_ACSMSEQGATECMD16_MASK BIT(13) +#define CSR_ACSMSEQTERM16_LSB 14 +#define CSR_ACSMSEQTERM16_MASK BIT(14) +#define CSR_ACSMLP3CA316_LSB 15 +#define CSR_ACSMLP3CA316_MASK BIT(15) +/* CSR_ACSMSEQ0X17 */ +#define CSR_ACSMSEQ0X17_LSB 0 +#define CSR_ACSMSEQ0X17_MASK GENMASK_32(15, 0) +#define CSR_ACSMMCLKDLY17_LSB 0 +#define CSR_ACSMMCLKDLY17_MASK GENMASK_32(7, 0) +#define CSR_ACSMDDRWE17_LSB 8 +#define CSR_ACSMDDRWE17_MASK BIT(8) +#define CSR_ACSMDDRCAS17_LSB 9 +#define CSR_ACSMDDRCAS17_MASK BIT(9) +#define CSR_ACSMDDRRAS17_LSB 10 +#define CSR_ACSMDDRRAS17_MASK BIT(10) +#define CSR_ACSMDDRCKESET17_LSB 11 +#define CSR_ACSMDDRCKESET17_MASK BIT(11) +#define CSR_ACSMDDRCKECLR17_LSB 12 +#define CSR_ACSMDDRCKECLR17_MASK BIT(12) +#define CSR_ACSMSEQGATECMD17_LSB 13 +#define CSR_ACSMSEQGATECMD17_MASK BIT(13) +#define CSR_ACSMSEQTERM17_LSB 14 +#define CSR_ACSMSEQTERM17_MASK BIT(14) +#define CSR_ACSMLP3CA317_LSB 15 +#define CSR_ACSMLP3CA317_MASK BIT(15) +/* CSR_ACSMSEQ0X18 */ +#define CSR_ACSMSEQ0X18_LSB 0 +#define CSR_ACSMSEQ0X18_MASK GENMASK_32(15, 0) +#define CSR_ACSMMCLKDLY18_LSB 0 +#define CSR_ACSMMCLKDLY18_MASK GENMASK_32(7, 0) +#define CSR_ACSMDDRWE18_LSB 8 +#define CSR_ACSMDDRWE18_MASK BIT(8) +#define CSR_ACSMDDRCAS18_LSB 9 +#define CSR_ACSMDDRCAS18_MASK BIT(9) +#define CSR_ACSMDDRRAS18_LSB 10 +#define CSR_ACSMDDRRAS18_MASK BIT(10) +#define CSR_ACSMDDRCKESET18_LSB 11 +#define CSR_ACSMDDRCKESET18_MASK BIT(11) +#define CSR_ACSMDDRCKECLR18_LSB 12 +#define CSR_ACSMDDRCKECLR18_MASK BIT(12) +#define CSR_ACSMSEQGATECMD18_LSB 13 +#define CSR_ACSMSEQGATECMD18_MASK BIT(13) +#define CSR_ACSMSEQTERM18_LSB 14 +#define CSR_ACSMSEQTERM18_MASK BIT(14) +#define CSR_ACSMLP3CA318_LSB 15 +#define CSR_ACSMLP3CA318_MASK BIT(15) +/* CSR_ACSMSEQ0X19 */ +#define CSR_ACSMSEQ0X19_LSB 0 +#define CSR_ACSMSEQ0X19_MASK GENMASK_32(15, 0) +#define CSR_ACSMMCLKDLY19_LSB 0 +#define CSR_ACSMMCLKDLY19_MASK GENMASK_32(7, 0) +#define CSR_ACSMDDRWE19_LSB 8 +#define CSR_ACSMDDRWE19_MASK BIT(8) +#define CSR_ACSMDDRCAS19_LSB 9 +#define CSR_ACSMDDRCAS19_MASK BIT(9) +#define CSR_ACSMDDRRAS19_LSB 10 +#define CSR_ACSMDDRRAS19_MASK BIT(10) +#define CSR_ACSMDDRCKESET19_LSB 11 +#define CSR_ACSMDDRCKESET19_MASK BIT(11) +#define CSR_ACSMDDRCKECLR19_LSB 12 +#define CSR_ACSMDDRCKECLR19_MASK BIT(12) +#define CSR_ACSMSEQGATECMD19_LSB 13 +#define CSR_ACSMSEQGATECMD19_MASK BIT(13) +#define CSR_ACSMSEQTERM19_LSB 14 +#define CSR_ACSMSEQTERM19_MASK BIT(14) +#define CSR_ACSMLP3CA319_LSB 15 +#define CSR_ACSMLP3CA319_MASK BIT(15) +/* CSR_ACSMSEQ0X20 */ +#define CSR_ACSMSEQ0X20_LSB 0 +#define CSR_ACSMSEQ0X20_MASK GENMASK_32(15, 0) +#define CSR_ACSMMCLKDLY20_LSB 0 +#define CSR_ACSMMCLKDLY20_MASK GENMASK_32(7, 0) +#define CSR_ACSMDDRWE20_LSB 8 +#define CSR_ACSMDDRWE20_MASK BIT(8) +#define CSR_ACSMDDRCAS20_LSB 9 +#define CSR_ACSMDDRCAS20_MASK BIT(9) +#define CSR_ACSMDDRRAS20_LSB 10 +#define CSR_ACSMDDRRAS20_MASK BIT(10) +#define CSR_ACSMDDRCKESET20_LSB 11 +#define CSR_ACSMDDRCKESET20_MASK BIT(11) +#define CSR_ACSMDDRCKECLR20_LSB 12 +#define CSR_ACSMDDRCKECLR20_MASK BIT(12) +#define CSR_ACSMSEQGATECMD20_LSB 13 +#define CSR_ACSMSEQGATECMD20_MASK BIT(13) +#define CSR_ACSMSEQTERM20_LSB 14 +#define CSR_ACSMSEQTERM20_MASK BIT(14) +#define CSR_ACSMLP3CA320_LSB 15 +#define CSR_ACSMLP3CA320_MASK BIT(15) +/* CSR_ACSMSEQ0X21 */ +#define CSR_ACSMSEQ0X21_LSB 0 +#define CSR_ACSMSEQ0X21_MASK GENMASK_32(15, 0) +#define CSR_ACSMMCLKDLY21_LSB 0 +#define CSR_ACSMMCLKDLY21_MASK GENMASK_32(7, 0) +#define CSR_ACSMDDRWE21_LSB 8 +#define CSR_ACSMDDRWE21_MASK BIT(8) +#define CSR_ACSMDDRCAS21_LSB 9 +#define CSR_ACSMDDRCAS21_MASK BIT(9) +#define CSR_ACSMDDRRAS21_LSB 10 +#define CSR_ACSMDDRRAS21_MASK BIT(10) +#define CSR_ACSMDDRCKESET21_LSB 11 +#define CSR_ACSMDDRCKESET21_MASK BIT(11) +#define CSR_ACSMDDRCKECLR21_LSB 12 +#define CSR_ACSMDDRCKECLR21_MASK BIT(12) +#define CSR_ACSMSEQGATECMD21_LSB 13 +#define CSR_ACSMSEQGATECMD21_MASK BIT(13) +#define CSR_ACSMSEQTERM21_LSB 14 +#define CSR_ACSMSEQTERM21_MASK BIT(14) +#define CSR_ACSMLP3CA321_LSB 15 +#define CSR_ACSMLP3CA321_MASK BIT(15) +/* CSR_ACSMSEQ0X22 */ +#define CSR_ACSMSEQ0X22_LSB 0 +#define CSR_ACSMSEQ0X22_MASK GENMASK_32(15, 0) +#define CSR_ACSMMCLKDLY22_LSB 0 +#define CSR_ACSMMCLKDLY22_MASK GENMASK_32(7, 0) +#define CSR_ACSMDDRWE22_LSB 8 +#define CSR_ACSMDDRWE22_MASK BIT(8) +#define CSR_ACSMDDRCAS22_LSB 9 +#define CSR_ACSMDDRCAS22_MASK BIT(9) +#define CSR_ACSMDDRRAS22_LSB 10 +#define CSR_ACSMDDRRAS22_MASK BIT(10) +#define CSR_ACSMDDRCKESET22_LSB 11 +#define CSR_ACSMDDRCKESET22_MASK BIT(11) +#define CSR_ACSMDDRCKECLR22_LSB 12 +#define CSR_ACSMDDRCKECLR22_MASK BIT(12) +#define CSR_ACSMSEQGATECMD22_LSB 13 +#define CSR_ACSMSEQGATECMD22_MASK BIT(13) +#define CSR_ACSMSEQTERM22_LSB 14 +#define CSR_ACSMSEQTERM22_MASK BIT(14) +#define CSR_ACSMLP3CA322_LSB 15 +#define CSR_ACSMLP3CA322_MASK BIT(15) +/* CSR_ACSMSEQ0X23 */ +#define CSR_ACSMSEQ0X23_LSB 0 +#define CSR_ACSMSEQ0X23_MASK GENMASK_32(15, 0) +#define CSR_ACSMMCLKDLY23_LSB 0 +#define CSR_ACSMMCLKDLY23_MASK GENMASK_32(7, 0) +#define CSR_ACSMDDRWE23_LSB 8 +#define CSR_ACSMDDRWE23_MASK BIT(8) +#define CSR_ACSMDDRCAS23_LSB 9 +#define CSR_ACSMDDRCAS23_MASK BIT(9) +#define CSR_ACSMDDRRAS23_LSB 10 +#define CSR_ACSMDDRRAS23_MASK BIT(10) +#define CSR_ACSMDDRCKESET23_LSB 11 +#define CSR_ACSMDDRCKESET23_MASK BIT(11) +#define CSR_ACSMDDRCKECLR23_LSB 12 +#define CSR_ACSMDDRCKECLR23_MASK BIT(12) +#define CSR_ACSMSEQGATECMD23_LSB 13 +#define CSR_ACSMSEQGATECMD23_MASK BIT(13) +#define CSR_ACSMSEQTERM23_LSB 14 +#define CSR_ACSMSEQTERM23_MASK BIT(14) +#define CSR_ACSMLP3CA323_LSB 15 +#define CSR_ACSMLP3CA323_MASK BIT(15) +/* CSR_ACSMSEQ0X24 */ +#define CSR_ACSMSEQ0X24_LSB 0 +#define CSR_ACSMSEQ0X24_MASK GENMASK_32(15, 0) +#define CSR_ACSMMCLKDLY24_LSB 0 +#define CSR_ACSMMCLKDLY24_MASK GENMASK_32(7, 0) +#define CSR_ACSMDDRWE24_LSB 8 +#define CSR_ACSMDDRWE24_MASK BIT(8) +#define CSR_ACSMDDRCAS24_LSB 9 +#define CSR_ACSMDDRCAS24_MASK BIT(9) +#define CSR_ACSMDDRRAS24_LSB 10 +#define CSR_ACSMDDRRAS24_MASK BIT(10) +#define CSR_ACSMDDRCKESET24_LSB 11 +#define CSR_ACSMDDRCKESET24_MASK BIT(11) +#define CSR_ACSMDDRCKECLR24_LSB 12 +#define CSR_ACSMDDRCKECLR24_MASK BIT(12) +#define CSR_ACSMSEQGATECMD24_LSB 13 +#define CSR_ACSMSEQGATECMD24_MASK BIT(13) +#define CSR_ACSMSEQTERM24_LSB 14 +#define CSR_ACSMSEQTERM24_MASK BIT(14) +#define CSR_ACSMLP3CA324_LSB 15 +#define CSR_ACSMLP3CA324_MASK BIT(15) +/* CSR_ACSMSEQ0X25 */ +#define CSR_ACSMSEQ0X25_LSB 0 +#define CSR_ACSMSEQ0X25_MASK GENMASK_32(15, 0) +#define CSR_ACSMMCLKDLY25_LSB 0 +#define CSR_ACSMMCLKDLY25_MASK GENMASK_32(7, 0) +#define CSR_ACSMDDRWE25_LSB 8 +#define CSR_ACSMDDRWE25_MASK BIT(8) +#define CSR_ACSMDDRCAS25_LSB 9 +#define CSR_ACSMDDRCAS25_MASK BIT(9) +#define CSR_ACSMDDRRAS25_LSB 10 +#define CSR_ACSMDDRRAS25_MASK BIT(10) +#define CSR_ACSMDDRCKESET25_LSB 11 +#define CSR_ACSMDDRCKESET25_MASK BIT(11) +#define CSR_ACSMDDRCKECLR25_LSB 12 +#define CSR_ACSMDDRCKECLR25_MASK BIT(12) +#define CSR_ACSMSEQGATECMD25_LSB 13 +#define CSR_ACSMSEQGATECMD25_MASK BIT(13) +#define CSR_ACSMSEQTERM25_LSB 14 +#define CSR_ACSMSEQTERM25_MASK BIT(14) +#define CSR_ACSMLP3CA325_LSB 15 +#define CSR_ACSMLP3CA325_MASK BIT(15) +/* CSR_ACSMSEQ0X26 */ +#define CSR_ACSMSEQ0X26_LSB 0 +#define CSR_ACSMSEQ0X26_MASK GENMASK_32(15, 0) +#define CSR_ACSMMCLKDLY26_LSB 0 +#define CSR_ACSMMCLKDLY26_MASK GENMASK_32(7, 0) +#define CSR_ACSMDDRWE26_LSB 8 +#define CSR_ACSMDDRWE26_MASK BIT(8) +#define CSR_ACSMDDRCAS26_LSB 9 +#define CSR_ACSMDDRCAS26_MASK BIT(9) +#define CSR_ACSMDDRRAS26_LSB 10 +#define CSR_ACSMDDRRAS26_MASK BIT(10) +#define CSR_ACSMDDRCKESET26_LSB 11 +#define CSR_ACSMDDRCKESET26_MASK BIT(11) +#define CSR_ACSMDDRCKECLR26_LSB 12 +#define CSR_ACSMDDRCKECLR26_MASK BIT(12) +#define CSR_ACSMSEQGATECMD26_LSB 13 +#define CSR_ACSMSEQGATECMD26_MASK BIT(13) +#define CSR_ACSMSEQTERM26_LSB 14 +#define CSR_ACSMSEQTERM26_MASK BIT(14) +#define CSR_ACSMLP3CA326_LSB 15 +#define CSR_ACSMLP3CA326_MASK BIT(15) +/* CSR_ACSMSEQ0X27 */ +#define CSR_ACSMSEQ0X27_LSB 0 +#define CSR_ACSMSEQ0X27_MASK GENMASK_32(15, 0) +#define CSR_ACSMMCLKDLY27_LSB 0 +#define CSR_ACSMMCLKDLY27_MASK GENMASK_32(7, 0) +#define CSR_ACSMDDRWE27_LSB 8 +#define CSR_ACSMDDRWE27_MASK BIT(8) +#define CSR_ACSMDDRCAS27_LSB 9 +#define CSR_ACSMDDRCAS27_MASK BIT(9) +#define CSR_ACSMDDRRAS27_LSB 10 +#define CSR_ACSMDDRRAS27_MASK BIT(10) +#define CSR_ACSMDDRCKESET27_LSB 11 +#define CSR_ACSMDDRCKESET27_MASK BIT(11) +#define CSR_ACSMDDRCKECLR27_LSB 12 +#define CSR_ACSMDDRCKECLR27_MASK BIT(12) +#define CSR_ACSMSEQGATECMD27_LSB 13 +#define CSR_ACSMSEQGATECMD27_MASK BIT(13) +#define CSR_ACSMSEQTERM27_LSB 14 +#define CSR_ACSMSEQTERM27_MASK BIT(14) +#define CSR_ACSMLP3CA327_LSB 15 +#define CSR_ACSMLP3CA327_MASK BIT(15) +/* CSR_ACSMSEQ0X28 */ +#define CSR_ACSMSEQ0X28_LSB 0 +#define CSR_ACSMSEQ0X28_MASK GENMASK_32(15, 0) +#define CSR_ACSMMCLKDLY28_LSB 0 +#define CSR_ACSMMCLKDLY28_MASK GENMASK_32(7, 0) +#define CSR_ACSMDDRWE28_LSB 8 +#define CSR_ACSMDDRWE28_MASK BIT(8) +#define CSR_ACSMDDRCAS28_LSB 9 +#define CSR_ACSMDDRCAS28_MASK BIT(9) +#define CSR_ACSMDDRRAS28_LSB 10 +#define CSR_ACSMDDRRAS28_MASK BIT(10) +#define CSR_ACSMDDRCKESET28_LSB 11 +#define CSR_ACSMDDRCKESET28_MASK BIT(11) +#define CSR_ACSMDDRCKECLR28_LSB 12 +#define CSR_ACSMDDRCKECLR28_MASK BIT(12) +#define CSR_ACSMSEQGATECMD28_LSB 13 +#define CSR_ACSMSEQGATECMD28_MASK BIT(13) +#define CSR_ACSMSEQTERM28_LSB 14 +#define CSR_ACSMSEQTERM28_MASK BIT(14) +#define CSR_ACSMLP3CA328_LSB 15 +#define CSR_ACSMLP3CA328_MASK BIT(15) +/* CSR_ACSMSEQ0X29 */ +#define CSR_ACSMSEQ0X29_LSB 0 +#define CSR_ACSMSEQ0X29_MASK GENMASK_32(15, 0) +#define CSR_ACSMMCLKDLY29_LSB 0 +#define CSR_ACSMMCLKDLY29_MASK GENMASK_32(7, 0) +#define CSR_ACSMDDRWE29_LSB 8 +#define CSR_ACSMDDRWE29_MASK BIT(8) +#define CSR_ACSMDDRCAS29_LSB 9 +#define CSR_ACSMDDRCAS29_MASK BIT(9) +#define CSR_ACSMDDRRAS29_LSB 10 +#define CSR_ACSMDDRRAS29_MASK BIT(10) +#define CSR_ACSMDDRCKESET29_LSB 11 +#define CSR_ACSMDDRCKESET29_MASK BIT(11) +#define CSR_ACSMDDRCKECLR29_LSB 12 +#define CSR_ACSMDDRCKECLR29_MASK BIT(12) +#define CSR_ACSMSEQGATECMD29_LSB 13 +#define CSR_ACSMSEQGATECMD29_MASK BIT(13) +#define CSR_ACSMSEQTERM29_LSB 14 +#define CSR_ACSMSEQTERM29_MASK BIT(14) +#define CSR_ACSMLP3CA329_LSB 15 +#define CSR_ACSMLP3CA329_MASK BIT(15) +/* CSR_ACSMSEQ0X30 */ +#define CSR_ACSMSEQ0X30_LSB 0 +#define CSR_ACSMSEQ0X30_MASK GENMASK_32(15, 0) +#define CSR_ACSMMCLKDLY30_LSB 0 +#define CSR_ACSMMCLKDLY30_MASK GENMASK_32(7, 0) +#define CSR_ACSMDDRWE30_LSB 8 +#define CSR_ACSMDDRWE30_MASK BIT(8) +#define CSR_ACSMDDRCAS30_LSB 9 +#define CSR_ACSMDDRCAS30_MASK BIT(9) +#define CSR_ACSMDDRRAS30_LSB 10 +#define CSR_ACSMDDRRAS30_MASK BIT(10) +#define CSR_ACSMDDRCKESET30_LSB 11 +#define CSR_ACSMDDRCKESET30_MASK BIT(11) +#define CSR_ACSMDDRCKECLR30_LSB 12 +#define CSR_ACSMDDRCKECLR30_MASK BIT(12) +#define CSR_ACSMSEQGATECMD30_LSB 13 +#define CSR_ACSMSEQGATECMD30_MASK BIT(13) +#define CSR_ACSMSEQTERM30_LSB 14 +#define CSR_ACSMSEQTERM30_MASK BIT(14) +#define CSR_ACSMLP3CA330_LSB 15 +#define CSR_ACSMLP3CA330_MASK BIT(15) +/* CSR_ACSMSEQ0X31 */ +#define CSR_ACSMSEQ0X31_LSB 0 +#define CSR_ACSMSEQ0X31_MASK GENMASK_32(15, 0) +#define CSR_ACSMMCLKDLY31_LSB 0 +#define CSR_ACSMMCLKDLY31_MASK GENMASK_32(7, 0) +#define CSR_ACSMDDRWE31_LSB 8 +#define CSR_ACSMDDRWE31_MASK BIT(8) +#define CSR_ACSMDDRCAS31_LSB 9 +#define CSR_ACSMDDRCAS31_MASK BIT(9) +#define CSR_ACSMDDRRAS31_LSB 10 +#define CSR_ACSMDDRRAS31_MASK BIT(10) +#define CSR_ACSMDDRCKESET31_LSB 11 +#define CSR_ACSMDDRCKESET31_MASK BIT(11) +#define CSR_ACSMDDRCKECLR31_LSB 12 +#define CSR_ACSMDDRCKECLR31_MASK BIT(12) +#define CSR_ACSMSEQGATECMD31_LSB 13 +#define CSR_ACSMSEQGATECMD31_MASK BIT(13) +#define CSR_ACSMSEQTERM31_LSB 14 +#define CSR_ACSMSEQTERM31_MASK BIT(14) +#define CSR_ACSMLP3CA331_LSB 15 +#define CSR_ACSMLP3CA331_MASK BIT(15) +/* CSR_ACSMSEQ1X0 */ +#define CSR_ACSMSEQ1X0_LSB 0 +#define CSR_ACSMSEQ1X0_MASK GENMASK_32(15, 0) +#define CSR_ACSMDDRCS0_LSB 0 +#define CSR_ACSMDDRCS0_MASK GENMASK_32(7, 0) +#define CSR_ACSMSAVEGEN0_LSB 8 +#define CSR_ACSMSAVEGEN0_MASK BIT(8) +#define CSR_ACSMLOADCHK0_LSB 9 +#define CSR_ACSMLOADCHK0_MASK BIT(9) +#define CSR_ACSMNORXENB0_LSB 10 +#define CSR_ACSMNORXENB0_MASK BIT(10) +#define CSR_ACSMNORXVAL0_LSB 11 +#define CSR_ACSMNORXVAL0_MASK BIT(11) +#define CSR_ACSMDDRBNK0_LSB 12 +#define CSR_ACSMDDRBNK0_MASK GENMASK_32(15, 12) +/* CSR_ACSMSEQ1X1 */ +#define CSR_ACSMSEQ1X1_LSB 0 +#define CSR_ACSMSEQ1X1_MASK GENMASK_32(15, 0) +#define CSR_ACSMDDRCS1_LSB 0 +#define CSR_ACSMDDRCS1_MASK GENMASK_32(7, 0) +#define CSR_ACSMSAVEGEN1_LSB 8 +#define CSR_ACSMSAVEGEN1_MASK BIT(8) +#define CSR_ACSMLOADCHK1_LSB 9 +#define CSR_ACSMLOADCHK1_MASK BIT(9) +#define CSR_ACSMNORXENB1_LSB 10 +#define CSR_ACSMNORXENB1_MASK BIT(10) +#define CSR_ACSMNORXVAL1_LSB 11 +#define CSR_ACSMNORXVAL1_MASK BIT(11) +#define CSR_ACSMDDRBNK1_LSB 12 +#define CSR_ACSMDDRBNK1_MASK GENMASK_32(15, 12) +/* CSR_ACSMSEQ1X2 */ +#define CSR_ACSMSEQ1X2_LSB 0 +#define CSR_ACSMSEQ1X2_MASK GENMASK_32(15, 0) +#define CSR_ACSMDDRCS2_LSB 0 +#define CSR_ACSMDDRCS2_MASK GENMASK_32(7, 0) +#define CSR_ACSMSAVEGEN2_LSB 8 +#define CSR_ACSMSAVEGEN2_MASK BIT(8) +#define CSR_ACSMLOADCHK2_LSB 9 +#define CSR_ACSMLOADCHK2_MASK BIT(9) +#define CSR_ACSMNORXENB2_LSB 10 +#define CSR_ACSMNORXENB2_MASK BIT(10) +#define CSR_ACSMNORXVAL2_LSB 11 +#define CSR_ACSMNORXVAL2_MASK BIT(11) +#define CSR_ACSMDDRBNK2_LSB 12 +#define CSR_ACSMDDRBNK2_MASK GENMASK_32(15, 12) +/* CSR_ACSMSEQ1X3 */ +#define CSR_ACSMSEQ1X3_LSB 0 +#define CSR_ACSMSEQ1X3_MASK GENMASK_32(15, 0) +#define CSR_ACSMDDRCS3_LSB 0 +#define CSR_ACSMDDRCS3_MASK GENMASK_32(7, 0) +#define CSR_ACSMSAVEGEN3_LSB 8 +#define CSR_ACSMSAVEGEN3_MASK BIT(8) +#define CSR_ACSMLOADCHK3_LSB 9 +#define CSR_ACSMLOADCHK3_MASK BIT(9) +#define CSR_ACSMNORXENB3_LSB 10 +#define CSR_ACSMNORXENB3_MASK BIT(10) +#define CSR_ACSMNORXVAL3_LSB 11 +#define CSR_ACSMNORXVAL3_MASK BIT(11) +#define CSR_ACSMDDRBNK3_LSB 12 +#define CSR_ACSMDDRBNK3_MASK GENMASK_32(15, 12) +/* CSR_ACSMSEQ1X4 */ +#define CSR_ACSMSEQ1X4_LSB 0 +#define CSR_ACSMSEQ1X4_MASK GENMASK_32(15, 0) +#define CSR_ACSMDDRCS4_LSB 0 +#define CSR_ACSMDDRCS4_MASK GENMASK_32(7, 0) +#define CSR_ACSMSAVEGEN4_LSB 8 +#define CSR_ACSMSAVEGEN4_MASK BIT(8) +#define CSR_ACSMLOADCHK4_LSB 9 +#define CSR_ACSMLOADCHK4_MASK BIT(9) +#define CSR_ACSMNORXENB4_LSB 10 +#define CSR_ACSMNORXENB4_MASK BIT(10) +#define CSR_ACSMNORXVAL4_LSB 11 +#define CSR_ACSMNORXVAL4_MASK BIT(11) +#define CSR_ACSMDDRBNK4_LSB 12 +#define CSR_ACSMDDRBNK4_MASK GENMASK_32(15, 12) +/* CSR_ACSMSEQ1X5 */ +#define CSR_ACSMSEQ1X5_LSB 0 +#define CSR_ACSMSEQ1X5_MASK GENMASK_32(15, 0) +#define CSR_ACSMDDRCS5_LSB 0 +#define CSR_ACSMDDRCS5_MASK GENMASK_32(7, 0) +#define CSR_ACSMSAVEGEN5_LSB 8 +#define CSR_ACSMSAVEGEN5_MASK BIT(8) +#define CSR_ACSMLOADCHK5_LSB 9 +#define CSR_ACSMLOADCHK5_MASK BIT(9) +#define CSR_ACSMNORXENB5_LSB 10 +#define CSR_ACSMNORXENB5_MASK BIT(10) +#define CSR_ACSMNORXVAL5_LSB 11 +#define CSR_ACSMNORXVAL5_MASK BIT(11) +#define CSR_ACSMDDRBNK5_LSB 12 +#define CSR_ACSMDDRBNK5_MASK GENMASK_32(15, 12) +/* CSR_ACSMSEQ1X6 */ +#define CSR_ACSMSEQ1X6_LSB 0 +#define CSR_ACSMSEQ1X6_MASK GENMASK_32(15, 0) +#define CSR_ACSMDDRCS6_LSB 0 +#define CSR_ACSMDDRCS6_MASK GENMASK_32(7, 0) +#define CSR_ACSMSAVEGEN6_LSB 8 +#define CSR_ACSMSAVEGEN6_MASK BIT(8) +#define CSR_ACSMLOADCHK6_LSB 9 +#define CSR_ACSMLOADCHK6_MASK BIT(9) +#define CSR_ACSMNORXENB6_LSB 10 +#define CSR_ACSMNORXENB6_MASK BIT(10) +#define CSR_ACSMNORXVAL6_LSB 11 +#define CSR_ACSMNORXVAL6_MASK BIT(11) +#define CSR_ACSMDDRBNK6_LSB 12 +#define CSR_ACSMDDRBNK6_MASK GENMASK_32(15, 12) +/* CSR_ACSMSEQ1X7 */ +#define CSR_ACSMSEQ1X7_LSB 0 +#define CSR_ACSMSEQ1X7_MASK GENMASK_32(15, 0) +#define CSR_ACSMDDRCS7_LSB 0 +#define CSR_ACSMDDRCS7_MASK GENMASK_32(7, 0) +#define CSR_ACSMSAVEGEN7_LSB 8 +#define CSR_ACSMSAVEGEN7_MASK BIT(8) +#define CSR_ACSMLOADCHK7_LSB 9 +#define CSR_ACSMLOADCHK7_MASK BIT(9) +#define CSR_ACSMNORXENB7_LSB 10 +#define CSR_ACSMNORXENB7_MASK BIT(10) +#define CSR_ACSMNORXVAL7_LSB 11 +#define CSR_ACSMNORXVAL7_MASK BIT(11) +#define CSR_ACSMDDRBNK7_LSB 12 +#define CSR_ACSMDDRBNK7_MASK GENMASK_32(15, 12) +/* CSR_ACSMSEQ1X8 */ +#define CSR_ACSMSEQ1X8_LSB 0 +#define CSR_ACSMSEQ1X8_MASK GENMASK_32(15, 0) +#define CSR_ACSMDDRCS8_LSB 0 +#define CSR_ACSMDDRCS8_MASK GENMASK_32(7, 0) +#define CSR_ACSMSAVEGEN8_LSB 8 +#define CSR_ACSMSAVEGEN8_MASK BIT(8) +#define CSR_ACSMLOADCHK8_LSB 9 +#define CSR_ACSMLOADCHK8_MASK BIT(9) +#define CSR_ACSMNORXENB8_LSB 10 +#define CSR_ACSMNORXENB8_MASK BIT(10) +#define CSR_ACSMNORXVAL8_LSB 11 +#define CSR_ACSMNORXVAL8_MASK BIT(11) +#define CSR_ACSMDDRBNK8_LSB 12 +#define CSR_ACSMDDRBNK8_MASK GENMASK_32(15, 12) +/* CSR_ACSMSEQ1X9 */ +#define CSR_ACSMSEQ1X9_LSB 0 +#define CSR_ACSMSEQ1X9_MASK GENMASK_32(15, 0) +#define CSR_ACSMDDRCS9_LSB 0 +#define CSR_ACSMDDRCS9_MASK GENMASK_32(7, 0) +#define CSR_ACSMSAVEGEN9_LSB 8 +#define CSR_ACSMSAVEGEN9_MASK BIT(8) +#define CSR_ACSMLOADCHK9_LSB 9 +#define CSR_ACSMLOADCHK9_MASK BIT(9) +#define CSR_ACSMNORXENB9_LSB 10 +#define CSR_ACSMNORXENB9_MASK BIT(10) +#define CSR_ACSMNORXVAL9_LSB 11 +#define CSR_ACSMNORXVAL9_MASK BIT(11) +#define CSR_ACSMDDRBNK9_LSB 12 +#define CSR_ACSMDDRBNK9_MASK GENMASK_32(15, 12) +/* CSR_ACSMSEQ1X10 */ +#define CSR_ACSMSEQ1X10_LSB 0 +#define CSR_ACSMSEQ1X10_MASK GENMASK_32(15, 0) +#define CSR_ACSMDDRCS10_LSB 0 +#define CSR_ACSMDDRCS10_MASK GENMASK_32(7, 0) +#define CSR_ACSMSAVEGEN10_LSB 8 +#define CSR_ACSMSAVEGEN10_MASK BIT(8) +#define CSR_ACSMLOADCHK10_LSB 9 +#define CSR_ACSMLOADCHK10_MASK BIT(9) +#define CSR_ACSMNORXENB10_LSB 10 +#define CSR_ACSMNORXENB10_MASK BIT(10) +#define CSR_ACSMNORXVAL10_LSB 11 +#define CSR_ACSMNORXVAL10_MASK BIT(11) +#define CSR_ACSMDDRBNK10_LSB 12 +#define CSR_ACSMDDRBNK10_MASK GENMASK_32(15, 12) +/* CSR_ACSMSEQ1X11 */ +#define CSR_ACSMSEQ1X11_LSB 0 +#define CSR_ACSMSEQ1X11_MASK GENMASK_32(15, 0) +#define CSR_ACSMDDRCS11_LSB 0 +#define CSR_ACSMDDRCS11_MASK GENMASK_32(7, 0) +#define CSR_ACSMSAVEGEN11_LSB 8 +#define CSR_ACSMSAVEGEN11_MASK BIT(8) +#define CSR_ACSMLOADCHK11_LSB 9 +#define CSR_ACSMLOADCHK11_MASK BIT(9) +#define CSR_ACSMNORXENB11_LSB 10 +#define CSR_ACSMNORXENB11_MASK BIT(10) +#define CSR_ACSMNORXVAL11_LSB 11 +#define CSR_ACSMNORXVAL11_MASK BIT(11) +#define CSR_ACSMDDRBNK11_LSB 12 +#define CSR_ACSMDDRBNK11_MASK GENMASK_32(15, 12) +/* CSR_ACSMSEQ1X12 */ +#define CSR_ACSMSEQ1X12_LSB 0 +#define CSR_ACSMSEQ1X12_MASK GENMASK_32(15, 0) +#define CSR_ACSMDDRCS12_LSB 0 +#define CSR_ACSMDDRCS12_MASK GENMASK_32(7, 0) +#define CSR_ACSMSAVEGEN12_LSB 8 +#define CSR_ACSMSAVEGEN12_MASK BIT(8) +#define CSR_ACSMLOADCHK12_LSB 9 +#define CSR_ACSMLOADCHK12_MASK BIT(9) +#define CSR_ACSMNORXENB12_LSB 10 +#define CSR_ACSMNORXENB12_MASK BIT(10) +#define CSR_ACSMNORXVAL12_LSB 11 +#define CSR_ACSMNORXVAL12_MASK BIT(11) +#define CSR_ACSMDDRBNK12_LSB 12 +#define CSR_ACSMDDRBNK12_MASK GENMASK_32(15, 12) +/* CSR_ACSMSEQ1X13 */ +#define CSR_ACSMSEQ1X13_LSB 0 +#define CSR_ACSMSEQ1X13_MASK GENMASK_32(15, 0) +#define CSR_ACSMDDRCS13_LSB 0 +#define CSR_ACSMDDRCS13_MASK GENMASK_32(7, 0) +#define CSR_ACSMSAVEGEN13_LSB 8 +#define CSR_ACSMSAVEGEN13_MASK BIT(8) +#define CSR_ACSMLOADCHK13_LSB 9 +#define CSR_ACSMLOADCHK13_MASK BIT(9) +#define CSR_ACSMNORXENB13_LSB 10 +#define CSR_ACSMNORXENB13_MASK BIT(10) +#define CSR_ACSMNORXVAL13_LSB 11 +#define CSR_ACSMNORXVAL13_MASK BIT(11) +#define CSR_ACSMDDRBNK13_LSB 12 +#define CSR_ACSMDDRBNK13_MASK GENMASK_32(15, 12) +/* CSR_ACSMSEQ1X14 */ +#define CSR_ACSMSEQ1X14_LSB 0 +#define CSR_ACSMSEQ1X14_MASK GENMASK_32(15, 0) +#define CSR_ACSMDDRCS14_LSB 0 +#define CSR_ACSMDDRCS14_MASK GENMASK_32(7, 0) +#define CSR_ACSMSAVEGEN14_LSB 8 +#define CSR_ACSMSAVEGEN14_MASK BIT(8) +#define CSR_ACSMLOADCHK14_LSB 9 +#define CSR_ACSMLOADCHK14_MASK BIT(9) +#define CSR_ACSMNORXENB14_LSB 10 +#define CSR_ACSMNORXENB14_MASK BIT(10) +#define CSR_ACSMNORXVAL14_LSB 11 +#define CSR_ACSMNORXVAL14_MASK BIT(11) +#define CSR_ACSMDDRBNK14_LSB 12 +#define CSR_ACSMDDRBNK14_MASK GENMASK_32(15, 12) +/* CSR_ACSMSEQ1X15 */ +#define CSR_ACSMSEQ1X15_LSB 0 +#define CSR_ACSMSEQ1X15_MASK GENMASK_32(15, 0) +#define CSR_ACSMDDRCS15_LSB 0 +#define CSR_ACSMDDRCS15_MASK GENMASK_32(7, 0) +#define CSR_ACSMSAVEGEN15_LSB 8 +#define CSR_ACSMSAVEGEN15_MASK BIT(8) +#define CSR_ACSMLOADCHK15_LSB 9 +#define CSR_ACSMLOADCHK15_MASK BIT(9) +#define CSR_ACSMNORXENB15_LSB 10 +#define CSR_ACSMNORXENB15_MASK BIT(10) +#define CSR_ACSMNORXVAL15_LSB 11 +#define CSR_ACSMNORXVAL15_MASK BIT(11) +#define CSR_ACSMDDRBNK15_LSB 12 +#define CSR_ACSMDDRBNK15_MASK GENMASK_32(15, 12) +/* CSR_ACSMSEQ1X16 */ +#define CSR_ACSMSEQ1X16_LSB 0 +#define CSR_ACSMSEQ1X16_MASK GENMASK_32(15, 0) +#define CSR_ACSMDDRCS16_LSB 0 +#define CSR_ACSMDDRCS16_MASK GENMASK_32(7, 0) +#define CSR_ACSMSAVEGEN16_LSB 8 +#define CSR_ACSMSAVEGEN16_MASK BIT(8) +#define CSR_ACSMLOADCHK16_LSB 9 +#define CSR_ACSMLOADCHK16_MASK BIT(9) +#define CSR_ACSMNORXENB16_LSB 10 +#define CSR_ACSMNORXENB16_MASK BIT(10) +#define CSR_ACSMNORXVAL16_LSB 11 +#define CSR_ACSMNORXVAL16_MASK BIT(11) +#define CSR_ACSMDDRBNK16_LSB 12 +#define CSR_ACSMDDRBNK16_MASK GENMASK_32(15, 12) +/* CSR_ACSMSEQ1X17 */ +#define CSR_ACSMSEQ1X17_LSB 0 +#define CSR_ACSMSEQ1X17_MASK GENMASK_32(15, 0) +#define CSR_ACSMDDRCS17_LSB 0 +#define CSR_ACSMDDRCS17_MASK GENMASK_32(7, 0) +#define CSR_ACSMSAVEGEN17_LSB 8 +#define CSR_ACSMSAVEGEN17_MASK BIT(8) +#define CSR_ACSMLOADCHK17_LSB 9 +#define CSR_ACSMLOADCHK17_MASK BIT(9) +#define CSR_ACSMNORXENB17_LSB 10 +#define CSR_ACSMNORXENB17_MASK BIT(10) +#define CSR_ACSMNORXVAL17_LSB 11 +#define CSR_ACSMNORXVAL17_MASK BIT(11) +#define CSR_ACSMDDRBNK17_LSB 12 +#define CSR_ACSMDDRBNK17_MASK GENMASK_32(15, 12) +/* CSR_ACSMSEQ1X18 */ +#define CSR_ACSMSEQ1X18_LSB 0 +#define CSR_ACSMSEQ1X18_MASK GENMASK_32(15, 0) +#define CSR_ACSMDDRCS18_LSB 0 +#define CSR_ACSMDDRCS18_MASK GENMASK_32(7, 0) +#define CSR_ACSMSAVEGEN18_LSB 8 +#define CSR_ACSMSAVEGEN18_MASK BIT(8) +#define CSR_ACSMLOADCHK18_LSB 9 +#define CSR_ACSMLOADCHK18_MASK BIT(9) +#define CSR_ACSMNORXENB18_LSB 10 +#define CSR_ACSMNORXENB18_MASK BIT(10) +#define CSR_ACSMNORXVAL18_LSB 11 +#define CSR_ACSMNORXVAL18_MASK BIT(11) +#define CSR_ACSMDDRBNK18_LSB 12 +#define CSR_ACSMDDRBNK18_MASK GENMASK_32(15, 12) +/* CSR_ACSMSEQ1X19 */ +#define CSR_ACSMSEQ1X19_LSB 0 +#define CSR_ACSMSEQ1X19_MASK GENMASK_32(15, 0) +#define CSR_ACSMDDRCS19_LSB 0 +#define CSR_ACSMDDRCS19_MASK GENMASK_32(7, 0) +#define CSR_ACSMSAVEGEN19_LSB 8 +#define CSR_ACSMSAVEGEN19_MASK BIT(8) +#define CSR_ACSMLOADCHK19_LSB 9 +#define CSR_ACSMLOADCHK19_MASK BIT(9) +#define CSR_ACSMNORXENB19_LSB 10 +#define CSR_ACSMNORXENB19_MASK BIT(10) +#define CSR_ACSMNORXVAL19_LSB 11 +#define CSR_ACSMNORXVAL19_MASK BIT(11) +#define CSR_ACSMDDRBNK19_LSB 12 +#define CSR_ACSMDDRBNK19_MASK GENMASK_32(15, 12) +/* CSR_ACSMSEQ1X20 */ +#define CSR_ACSMSEQ1X20_LSB 0 +#define CSR_ACSMSEQ1X20_MASK GENMASK_32(15, 0) +#define CSR_ACSMDDRCS20_LSB 0 +#define CSR_ACSMDDRCS20_MASK GENMASK_32(7, 0) +#define CSR_ACSMSAVEGEN20_LSB 8 +#define CSR_ACSMSAVEGEN20_MASK BIT(8) +#define CSR_ACSMLOADCHK20_LSB 9 +#define CSR_ACSMLOADCHK20_MASK BIT(9) +#define CSR_ACSMNORXENB20_LSB 10 +#define CSR_ACSMNORXENB20_MASK BIT(10) +#define CSR_ACSMNORXVAL20_LSB 11 +#define CSR_ACSMNORXVAL20_MASK BIT(11) +#define CSR_ACSMDDRBNK20_LSB 12 +#define CSR_ACSMDDRBNK20_MASK GENMASK_32(15, 12) +/* CSR_ACSMSEQ1X21 */ +#define CSR_ACSMSEQ1X21_LSB 0 +#define CSR_ACSMSEQ1X21_MASK GENMASK_32(15, 0) +#define CSR_ACSMDDRCS21_LSB 0 +#define CSR_ACSMDDRCS21_MASK GENMASK_32(7, 0) +#define CSR_ACSMSAVEGEN21_LSB 8 +#define CSR_ACSMSAVEGEN21_MASK BIT(8) +#define CSR_ACSMLOADCHK21_LSB 9 +#define CSR_ACSMLOADCHK21_MASK BIT(9) +#define CSR_ACSMNORXENB21_LSB 10 +#define CSR_ACSMNORXENB21_MASK BIT(10) +#define CSR_ACSMNORXVAL21_LSB 11 +#define CSR_ACSMNORXVAL21_MASK BIT(11) +#define CSR_ACSMDDRBNK21_LSB 12 +#define CSR_ACSMDDRBNK21_MASK GENMASK_32(15, 12) +/* CSR_ACSMSEQ1X22 */ +#define CSR_ACSMSEQ1X22_LSB 0 +#define CSR_ACSMSEQ1X22_MASK GENMASK_32(15, 0) +#define CSR_ACSMDDRCS22_LSB 0 +#define CSR_ACSMDDRCS22_MASK GENMASK_32(7, 0) +#define CSR_ACSMSAVEGEN22_LSB 8 +#define CSR_ACSMSAVEGEN22_MASK BIT(8) +#define CSR_ACSMLOADCHK22_LSB 9 +#define CSR_ACSMLOADCHK22_MASK BIT(9) +#define CSR_ACSMNORXENB22_LSB 10 +#define CSR_ACSMNORXENB22_MASK BIT(10) +#define CSR_ACSMNORXVAL22_LSB 11 +#define CSR_ACSMNORXVAL22_MASK BIT(11) +#define CSR_ACSMDDRBNK22_LSB 12 +#define CSR_ACSMDDRBNK22_MASK GENMASK_32(15, 12) +/* CSR_ACSMSEQ1X23 */ +#define CSR_ACSMSEQ1X23_LSB 0 +#define CSR_ACSMSEQ1X23_MASK GENMASK_32(15, 0) +#define CSR_ACSMDDRCS23_LSB 0 +#define CSR_ACSMDDRCS23_MASK GENMASK_32(7, 0) +#define CSR_ACSMSAVEGEN23_LSB 8 +#define CSR_ACSMSAVEGEN23_MASK BIT(8) +#define CSR_ACSMLOADCHK23_LSB 9 +#define CSR_ACSMLOADCHK23_MASK BIT(9) +#define CSR_ACSMNORXENB23_LSB 10 +#define CSR_ACSMNORXENB23_MASK BIT(10) +#define CSR_ACSMNORXVAL23_LSB 11 +#define CSR_ACSMNORXVAL23_MASK BIT(11) +#define CSR_ACSMDDRBNK23_LSB 12 +#define CSR_ACSMDDRBNK23_MASK GENMASK_32(15, 12) +/* CSR_ACSMSEQ1X24 */ +#define CSR_ACSMSEQ1X24_LSB 0 +#define CSR_ACSMSEQ1X24_MASK GENMASK_32(15, 0) +#define CSR_ACSMDDRCS24_LSB 0 +#define CSR_ACSMDDRCS24_MASK GENMASK_32(7, 0) +#define CSR_ACSMSAVEGEN24_LSB 8 +#define CSR_ACSMSAVEGEN24_MASK BIT(8) +#define CSR_ACSMLOADCHK24_LSB 9 +#define CSR_ACSMLOADCHK24_MASK BIT(9) +#define CSR_ACSMNORXENB24_LSB 10 +#define CSR_ACSMNORXENB24_MASK BIT(10) +#define CSR_ACSMNORXVAL24_LSB 11 +#define CSR_ACSMNORXVAL24_MASK BIT(11) +#define CSR_ACSMDDRBNK24_LSB 12 +#define CSR_ACSMDDRBNK24_MASK GENMASK_32(15, 12) +/* CSR_ACSMSEQ1X25 */ +#define CSR_ACSMSEQ1X25_LSB 0 +#define CSR_ACSMSEQ1X25_MASK GENMASK_32(15, 0) +#define CSR_ACSMDDRCS25_LSB 0 +#define CSR_ACSMDDRCS25_MASK GENMASK_32(7, 0) +#define CSR_ACSMSAVEGEN25_LSB 8 +#define CSR_ACSMSAVEGEN25_MASK BIT(8) +#define CSR_ACSMLOADCHK25_LSB 9 +#define CSR_ACSMLOADCHK25_MASK BIT(9) +#define CSR_ACSMNORXENB25_LSB 10 +#define CSR_ACSMNORXENB25_MASK BIT(10) +#define CSR_ACSMNORXVAL25_LSB 11 +#define CSR_ACSMNORXVAL25_MASK BIT(11) +#define CSR_ACSMDDRBNK25_LSB 12 +#define CSR_ACSMDDRBNK25_MASK GENMASK_32(15, 12) +/* CSR_ACSMSEQ1X26 */ +#define CSR_ACSMSEQ1X26_LSB 0 +#define CSR_ACSMSEQ1X26_MASK GENMASK_32(15, 0) +#define CSR_ACSMDDRCS26_LSB 0 +#define CSR_ACSMDDRCS26_MASK GENMASK_32(7, 0) +#define CSR_ACSMSAVEGEN26_LSB 8 +#define CSR_ACSMSAVEGEN26_MASK BIT(8) +#define CSR_ACSMLOADCHK26_LSB 9 +#define CSR_ACSMLOADCHK26_MASK BIT(9) +#define CSR_ACSMNORXENB26_LSB 10 +#define CSR_ACSMNORXENB26_MASK BIT(10) +#define CSR_ACSMNORXVAL26_LSB 11 +#define CSR_ACSMNORXVAL26_MASK BIT(11) +#define CSR_ACSMDDRBNK26_LSB 12 +#define CSR_ACSMDDRBNK26_MASK GENMASK_32(15, 12) +/* CSR_ACSMSEQ1X27 */ +#define CSR_ACSMSEQ1X27_LSB 0 +#define CSR_ACSMSEQ1X27_MASK GENMASK_32(15, 0) +#define CSR_ACSMDDRCS27_LSB 0 +#define CSR_ACSMDDRCS27_MASK GENMASK_32(7, 0) +#define CSR_ACSMSAVEGEN27_LSB 8 +#define CSR_ACSMSAVEGEN27_MASK BIT(8) +#define CSR_ACSMLOADCHK27_LSB 9 +#define CSR_ACSMLOADCHK27_MASK BIT(9) +#define CSR_ACSMNORXENB27_LSB 10 +#define CSR_ACSMNORXENB27_MASK BIT(10) +#define CSR_ACSMNORXVAL27_LSB 11 +#define CSR_ACSMNORXVAL27_MASK BIT(11) +#define CSR_ACSMDDRBNK27_LSB 12 +#define CSR_ACSMDDRBNK27_MASK GENMASK_32(15, 12) +/* CSR_ACSMSEQ1X28 */ +#define CSR_ACSMSEQ1X28_LSB 0 +#define CSR_ACSMSEQ1X28_MASK GENMASK_32(15, 0) +#define CSR_ACSMDDRCS28_LSB 0 +#define CSR_ACSMDDRCS28_MASK GENMASK_32(7, 0) +#define CSR_ACSMSAVEGEN28_LSB 8 +#define CSR_ACSMSAVEGEN28_MASK BIT(8) +#define CSR_ACSMLOADCHK28_LSB 9 +#define CSR_ACSMLOADCHK28_MASK BIT(9) +#define CSR_ACSMNORXENB28_LSB 10 +#define CSR_ACSMNORXENB28_MASK BIT(10) +#define CSR_ACSMNORXVAL28_LSB 11 +#define CSR_ACSMNORXVAL28_MASK BIT(11) +#define CSR_ACSMDDRBNK28_LSB 12 +#define CSR_ACSMDDRBNK28_MASK GENMASK_32(15, 12) +/* CSR_ACSMSEQ1X29 */ +#define CSR_ACSMSEQ1X29_LSB 0 +#define CSR_ACSMSEQ1X29_MASK GENMASK_32(15, 0) +#define CSR_ACSMDDRCS29_LSB 0 +#define CSR_ACSMDDRCS29_MASK GENMASK_32(7, 0) +#define CSR_ACSMSAVEGEN29_LSB 8 +#define CSR_ACSMSAVEGEN29_MASK BIT(8) +#define CSR_ACSMLOADCHK29_LSB 9 +#define CSR_ACSMLOADCHK29_MASK BIT(9) +#define CSR_ACSMNORXENB29_LSB 10 +#define CSR_ACSMNORXENB29_MASK BIT(10) +#define CSR_ACSMNORXVAL29_LSB 11 +#define CSR_ACSMNORXVAL29_MASK BIT(11) +#define CSR_ACSMDDRBNK29_LSB 12 +#define CSR_ACSMDDRBNK29_MASK GENMASK_32(15, 12) +/* CSR_ACSMSEQ1X30 */ +#define CSR_ACSMSEQ1X30_LSB 0 +#define CSR_ACSMSEQ1X30_MASK GENMASK_32(15, 0) +#define CSR_ACSMDDRCS30_LSB 0 +#define CSR_ACSMDDRCS30_MASK GENMASK_32(7, 0) +#define CSR_ACSMSAVEGEN30_LSB 8 +#define CSR_ACSMSAVEGEN30_MASK BIT(8) +#define CSR_ACSMLOADCHK30_LSB 9 +#define CSR_ACSMLOADCHK30_MASK BIT(9) +#define CSR_ACSMNORXENB30_LSB 10 +#define CSR_ACSMNORXENB30_MASK BIT(10) +#define CSR_ACSMNORXVAL30_LSB 11 +#define CSR_ACSMNORXVAL30_MASK BIT(11) +#define CSR_ACSMDDRBNK30_LSB 12 +#define CSR_ACSMDDRBNK30_MASK GENMASK_32(15, 12) +/* CSR_ACSMSEQ1X31 */ +#define CSR_ACSMSEQ1X31_LSB 0 +#define CSR_ACSMSEQ1X31_MASK GENMASK_32(15, 0) +#define CSR_ACSMDDRCS31_LSB 0 +#define CSR_ACSMDDRCS31_MASK GENMASK_32(7, 0) +#define CSR_ACSMSAVEGEN31_LSB 8 +#define CSR_ACSMSAVEGEN31_MASK BIT(8) +#define CSR_ACSMLOADCHK31_LSB 9 +#define CSR_ACSMLOADCHK31_MASK BIT(9) +#define CSR_ACSMNORXENB31_LSB 10 +#define CSR_ACSMNORXENB31_MASK BIT(10) +#define CSR_ACSMNORXVAL31_LSB 11 +#define CSR_ACSMNORXVAL31_MASK BIT(11) +#define CSR_ACSMDDRBNK31_LSB 12 +#define CSR_ACSMDDRBNK31_MASK GENMASK_32(15, 12) +/* CSR_ACSMSEQ2X0 */ +#define CSR_ACSMSEQ2X0_LSB 0 +#define CSR_ACSMSEQ2X0_MASK GENMASK_32(15, 0) +#define CSR_ACSMDDRADRX15X0X0_LSB 0 +#define CSR_ACSMDDRADRX15X0X0_MASK GENMASK_32(15, 0) +/* CSR_ACSMSEQ2X1 */ +#define CSR_ACSMSEQ2X1_LSB 0 +#define CSR_ACSMSEQ2X1_MASK GENMASK_32(15, 0) +#define CSR_ACSMDDRADRX15X0X1_LSB 0 +#define CSR_ACSMDDRADRX15X0X1_MASK GENMASK_32(15, 0) +/* CSR_ACSMSEQ2X2 */ +#define CSR_ACSMSEQ2X2_LSB 0 +#define CSR_ACSMSEQ2X2_MASK GENMASK_32(15, 0) +#define CSR_ACSMDDRADRX15X0X2_LSB 0 +#define CSR_ACSMDDRADRX15X0X2_MASK GENMASK_32(15, 0) +/* CSR_ACSMSEQ2X3 */ +#define CSR_ACSMSEQ2X3_LSB 0 +#define CSR_ACSMSEQ2X3_MASK GENMASK_32(15, 0) +#define CSR_ACSMDDRADRX15X0X3_LSB 0 +#define CSR_ACSMDDRADRX15X0X3_MASK GENMASK_32(15, 0) +/* CSR_ACSMSEQ2X4 */ +#define CSR_ACSMSEQ2X4_LSB 0 +#define CSR_ACSMSEQ2X4_MASK GENMASK_32(15, 0) +#define CSR_ACSMDDRADRX15X0X4_LSB 0 +#define CSR_ACSMDDRADRX15X0X4_MASK GENMASK_32(15, 0) +/* CSR_ACSMSEQ2X5 */ +#define CSR_ACSMSEQ2X5_LSB 0 +#define CSR_ACSMSEQ2X5_MASK GENMASK_32(15, 0) +#define CSR_ACSMDDRADRX15X0X5_LSB 0 +#define CSR_ACSMDDRADRX15X0X5_MASK GENMASK_32(15, 0) +/* CSR_ACSMSEQ2X6 */ +#define CSR_ACSMSEQ2X6_LSB 0 +#define CSR_ACSMSEQ2X6_MASK GENMASK_32(15, 0) +#define CSR_ACSMDDRADRX15X0X6_LSB 0 +#define CSR_ACSMDDRADRX15X0X6_MASK GENMASK_32(15, 0) +/* CSR_ACSMSEQ2X7 */ +#define CSR_ACSMSEQ2X7_LSB 0 +#define CSR_ACSMSEQ2X7_MASK GENMASK_32(15, 0) +#define CSR_ACSMDDRADRX15X0X7_LSB 0 +#define CSR_ACSMDDRADRX15X0X7_MASK GENMASK_32(15, 0) +/* CSR_ACSMSEQ2X8 */ +#define CSR_ACSMSEQ2X8_LSB 0 +#define CSR_ACSMSEQ2X8_MASK GENMASK_32(15, 0) +#define CSR_ACSMDDRADRX15X0X8_LSB 0 +#define CSR_ACSMDDRADRX15X0X8_MASK GENMASK_32(15, 0) +/* CSR_ACSMSEQ2X9 */ +#define CSR_ACSMSEQ2X9_LSB 0 +#define CSR_ACSMSEQ2X9_MASK GENMASK_32(15, 0) +#define CSR_ACSMDDRADRX15X0X9_LSB 0 +#define CSR_ACSMDDRADRX15X0X9_MASK GENMASK_32(15, 0) +/* CSR_ACSMSEQ2X10 */ +#define CSR_ACSMSEQ2X10_LSB 0 +#define CSR_ACSMSEQ2X10_MASK GENMASK_32(15, 0) +#define CSR_ACSMDDRADRX15X0X10_LSB 0 +#define CSR_ACSMDDRADRX15X0X10_MASK GENMASK_32(15, 0) +/* CSR_ACSMSEQ2X11 */ +#define CSR_ACSMSEQ2X11_LSB 0 +#define CSR_ACSMSEQ2X11_MASK GENMASK_32(15, 0) +#define CSR_ACSMDDRADRX15X0X11_LSB 0 +#define CSR_ACSMDDRADRX15X0X11_MASK GENMASK_32(15, 0) +/* CSR_ACSMSEQ2X12 */ +#define CSR_ACSMSEQ2X12_LSB 0 +#define CSR_ACSMSEQ2X12_MASK GENMASK_32(15, 0) +#define CSR_ACSMDDRADRX15X0X12_LSB 0 +#define CSR_ACSMDDRADRX15X0X12_MASK GENMASK_32(15, 0) +/* CSR_ACSMSEQ2X13 */ +#define CSR_ACSMSEQ2X13_LSB 0 +#define CSR_ACSMSEQ2X13_MASK GENMASK_32(15, 0) +#define CSR_ACSMDDRADRX15X0X13_LSB 0 +#define CSR_ACSMDDRADRX15X0X13_MASK GENMASK_32(15, 0) +/* CSR_ACSMSEQ2X14 */ +#define CSR_ACSMSEQ2X14_LSB 0 +#define CSR_ACSMSEQ2X14_MASK GENMASK_32(15, 0) +#define CSR_ACSMDDRADRX15X0X14_LSB 0 +#define CSR_ACSMDDRADRX15X0X14_MASK GENMASK_32(15, 0) +/* CSR_ACSMSEQ2X15 */ +#define CSR_ACSMSEQ2X15_LSB 0 +#define CSR_ACSMSEQ2X15_MASK GENMASK_32(15, 0) +#define CSR_ACSMDDRADRX15X0X15_LSB 0 +#define CSR_ACSMDDRADRX15X0X15_MASK GENMASK_32(15, 0) +/* CSR_ACSMSEQ2X16 */ +#define CSR_ACSMSEQ2X16_LSB 0 +#define CSR_ACSMSEQ2X16_MASK GENMASK_32(15, 0) +#define CSR_ACSMDDRADRX15X0X16_LSB 0 +#define CSR_ACSMDDRADRX15X0X16_MASK GENMASK_32(15, 0) +/* CSR_ACSMSEQ2X17 */ +#define CSR_ACSMSEQ2X17_LSB 0 +#define CSR_ACSMSEQ2X17_MASK GENMASK_32(15, 0) +#define CSR_ACSMDDRADRX15X0X17_LSB 0 +#define CSR_ACSMDDRADRX15X0X17_MASK GENMASK_32(15, 0) +/* CSR_ACSMSEQ2X18 */ +#define CSR_ACSMSEQ2X18_LSB 0 +#define CSR_ACSMSEQ2X18_MASK GENMASK_32(15, 0) +#define CSR_ACSMDDRADRX15X0X18_LSB 0 +#define CSR_ACSMDDRADRX15X0X18_MASK GENMASK_32(15, 0) +/* CSR_ACSMSEQ2X19 */ +#define CSR_ACSMSEQ2X19_LSB 0 +#define CSR_ACSMSEQ2X19_MASK GENMASK_32(15, 0) +#define CSR_ACSMDDRADRX15X0X19_LSB 0 +#define CSR_ACSMDDRADRX15X0X19_MASK GENMASK_32(15, 0) +/* CSR_ACSMSEQ2X20 */ +#define CSR_ACSMSEQ2X20_LSB 0 +#define CSR_ACSMSEQ2X20_MASK GENMASK_32(15, 0) +#define CSR_ACSMDDRADRX15X0X20_LSB 0 +#define CSR_ACSMDDRADRX15X0X20_MASK GENMASK_32(15, 0) +/* CSR_ACSMSEQ2X21 */ +#define CSR_ACSMSEQ2X21_LSB 0 +#define CSR_ACSMSEQ2X21_MASK GENMASK_32(15, 0) +#define CSR_ACSMDDRADRX15X0X21_LSB 0 +#define CSR_ACSMDDRADRX15X0X21_MASK GENMASK_32(15, 0) +/* CSR_ACSMSEQ2X22 */ +#define CSR_ACSMSEQ2X22_LSB 0 +#define CSR_ACSMSEQ2X22_MASK GENMASK_32(15, 0) +#define CSR_ACSMDDRADRX15X0X22_LSB 0 +#define CSR_ACSMDDRADRX15X0X22_MASK GENMASK_32(15, 0) +/* CSR_ACSMSEQ2X23 */ +#define CSR_ACSMSEQ2X23_LSB 0 +#define CSR_ACSMSEQ2X23_MASK GENMASK_32(15, 0) +#define CSR_ACSMDDRADRX15X0X23_LSB 0 +#define CSR_ACSMDDRADRX15X0X23_MASK GENMASK_32(15, 0) +/* CSR_ACSMSEQ2X24 */ +#define CSR_ACSMSEQ2X24_LSB 0 +#define CSR_ACSMSEQ2X24_MASK GENMASK_32(15, 0) +#define CSR_ACSMDDRADRX15X0X24_LSB 0 +#define CSR_ACSMDDRADRX15X0X24_MASK GENMASK_32(15, 0) +/* CSR_ACSMSEQ2X25 */ +#define CSR_ACSMSEQ2X25_LSB 0 +#define CSR_ACSMSEQ2X25_MASK GENMASK_32(15, 0) +#define CSR_ACSMDDRADRX15X0X25_LSB 0 +#define CSR_ACSMDDRADRX15X0X25_MASK GENMASK_32(15, 0) +/* CSR_ACSMSEQ2X26 */ +#define CSR_ACSMSEQ2X26_LSB 0 +#define CSR_ACSMSEQ2X26_MASK GENMASK_32(15, 0) +#define CSR_ACSMDDRADRX15X0X26_LSB 0 +#define CSR_ACSMDDRADRX15X0X26_MASK GENMASK_32(15, 0) +/* CSR_ACSMSEQ2X27 */ +#define CSR_ACSMSEQ2X27_LSB 0 +#define CSR_ACSMSEQ2X27_MASK GENMASK_32(15, 0) +#define CSR_ACSMDDRADRX15X0X27_LSB 0 +#define CSR_ACSMDDRADRX15X0X27_MASK GENMASK_32(15, 0) +/* CSR_ACSMSEQ2X28 */ +#define CSR_ACSMSEQ2X28_LSB 0 +#define CSR_ACSMSEQ2X28_MASK GENMASK_32(15, 0) +#define CSR_ACSMDDRADRX15X0X28_LSB 0 +#define CSR_ACSMDDRADRX15X0X28_MASK GENMASK_32(15, 0) +/* CSR_ACSMSEQ2X29 */ +#define CSR_ACSMSEQ2X29_LSB 0 +#define CSR_ACSMSEQ2X29_MASK GENMASK_32(15, 0) +#define CSR_ACSMDDRADRX15X0X29_LSB 0 +#define CSR_ACSMDDRADRX15X0X29_MASK GENMASK_32(15, 0) +/* CSR_ACSMSEQ2X30 */ +#define CSR_ACSMSEQ2X30_LSB 0 +#define CSR_ACSMSEQ2X30_MASK GENMASK_32(15, 0) +#define CSR_ACSMDDRADRX15X0X30_LSB 0 +#define CSR_ACSMDDRADRX15X0X30_MASK GENMASK_32(15, 0) +/* CSR_ACSMSEQ2X31 */ +#define CSR_ACSMSEQ2X31_LSB 0 +#define CSR_ACSMSEQ2X31_MASK GENMASK_32(15, 0) +#define CSR_ACSMDDRADRX15X0X31_LSB 0 +#define CSR_ACSMDDRADRX15X0X31_MASK GENMASK_32(15, 0) +/* CSR_ACSMSEQ3X0 */ +#define CSR_ACSMSEQ3X0_LSB 0 +#define CSR_ACSMSEQ3X0_MASK GENMASK_32(15, 0) +#define CSR_ACSMCMDREPCNT0_LSB 0 +#define CSR_ACSMCMDREPCNT0_MASK GENMASK_32(7, 0) +#define CSR_ACSMADRADV0_LSB 8 +#define CSR_ACSMADRADV0_MASK GENMASK_32(9, 8) +#define CSR_ACSMBNKADV0_LSB 10 +#define CSR_ACSMBNKADV0_MASK GENMASK_32(11, 10) +#define CSR_ACSMADRSELLOAD0_LSB 12 +#define CSR_ACSMADRSELLOAD0_MASK GENMASK_32(13, 12) +#define CSR_ACSMBNKSELLOAD0_LSB 14 +#define CSR_ACSMBNKSELLOAD0_MASK BIT(14) +#define CSR_ACSMLONGBUBBLE0_LSB 15 +#define CSR_ACSMLONGBUBBLE0_MASK BIT(15) +/* CSR_ACSMSEQ3X1 */ +#define CSR_ACSMSEQ3X1_LSB 0 +#define CSR_ACSMSEQ3X1_MASK GENMASK_32(15, 0) +#define CSR_ACSMCMDREPCNT1_LSB 0 +#define CSR_ACSMCMDREPCNT1_MASK GENMASK_32(7, 0) +#define CSR_ACSMADRADV1_LSB 8 +#define CSR_ACSMADRADV1_MASK GENMASK_32(9, 8) +#define CSR_ACSMBNKADV1_LSB 10 +#define CSR_ACSMBNKADV1_MASK GENMASK_32(11, 10) +#define CSR_ACSMADRSELLOAD1_LSB 12 +#define CSR_ACSMADRSELLOAD1_MASK GENMASK_32(13, 12) +#define CSR_ACSMBNKSELLOAD1_LSB 14 +#define CSR_ACSMBNKSELLOAD1_MASK BIT(14) +#define CSR_ACSMLONGBUBBLE1_LSB 15 +#define CSR_ACSMLONGBUBBLE1_MASK BIT(15) +/* CSR_ACSMSEQ3X2 */ +#define CSR_ACSMSEQ3X2_LSB 0 +#define CSR_ACSMSEQ3X2_MASK GENMASK_32(15, 0) +#define CSR_ACSMCMDREPCNT2_LSB 0 +#define CSR_ACSMCMDREPCNT2_MASK GENMASK_32(7, 0) +#define CSR_ACSMADRADV2_LSB 8 +#define CSR_ACSMADRADV2_MASK GENMASK_32(9, 8) +#define CSR_ACSMBNKADV2_LSB 10 +#define CSR_ACSMBNKADV2_MASK GENMASK_32(11, 10) +#define CSR_ACSMADRSELLOAD2_LSB 12 +#define CSR_ACSMADRSELLOAD2_MASK GENMASK_32(13, 12) +#define CSR_ACSMBNKSELLOAD2_LSB 14 +#define CSR_ACSMBNKSELLOAD2_MASK BIT(14) +#define CSR_ACSMLONGBUBBLE2_LSB 15 +#define CSR_ACSMLONGBUBBLE2_MASK BIT(15) +/* CSR_ACSMSEQ3X3 */ +#define CSR_ACSMSEQ3X3_LSB 0 +#define CSR_ACSMSEQ3X3_MASK GENMASK_32(15, 0) +#define CSR_ACSMCMDREPCNT3_LSB 0 +#define CSR_ACSMCMDREPCNT3_MASK GENMASK_32(7, 0) +#define CSR_ACSMADRADV3_LSB 8 +#define CSR_ACSMADRADV3_MASK GENMASK_32(9, 8) +#define CSR_ACSMBNKADV3_LSB 10 +#define CSR_ACSMBNKADV3_MASK GENMASK_32(11, 10) +#define CSR_ACSMADRSELLOAD3_LSB 12 +#define CSR_ACSMADRSELLOAD3_MASK GENMASK_32(13, 12) +#define CSR_ACSMBNKSELLOAD3_LSB 14 +#define CSR_ACSMBNKSELLOAD3_MASK BIT(14) +#define CSR_ACSMLONGBUBBLE3_LSB 15 +#define CSR_ACSMLONGBUBBLE3_MASK BIT(15) +/* CSR_ACSMSEQ3X4 */ +#define CSR_ACSMSEQ3X4_LSB 0 +#define CSR_ACSMSEQ3X4_MASK GENMASK_32(15, 0) +#define CSR_ACSMCMDREPCNT4_LSB 0 +#define CSR_ACSMCMDREPCNT4_MASK GENMASK_32(7, 0) +#define CSR_ACSMADRADV4_LSB 8 +#define CSR_ACSMADRADV4_MASK GENMASK_32(9, 8) +#define CSR_ACSMBNKADV4_LSB 10 +#define CSR_ACSMBNKADV4_MASK GENMASK_32(11, 10) +#define CSR_ACSMADRSELLOAD4_LSB 12 +#define CSR_ACSMADRSELLOAD4_MASK GENMASK_32(13, 12) +#define CSR_ACSMBNKSELLOAD4_LSB 14 +#define CSR_ACSMBNKSELLOAD4_MASK BIT(14) +#define CSR_ACSMLONGBUBBLE4_LSB 15 +#define CSR_ACSMLONGBUBBLE4_MASK BIT(15) +/* CSR_ACSMSEQ3X5 */ +#define CSR_ACSMSEQ3X5_LSB 0 +#define CSR_ACSMSEQ3X5_MASK GENMASK_32(15, 0) +#define CSR_ACSMCMDREPCNT5_LSB 0 +#define CSR_ACSMCMDREPCNT5_MASK GENMASK_32(7, 0) +#define CSR_ACSMADRADV5_LSB 8 +#define CSR_ACSMADRADV5_MASK GENMASK_32(9, 8) +#define CSR_ACSMBNKADV5_LSB 10 +#define CSR_ACSMBNKADV5_MASK GENMASK_32(11, 10) +#define CSR_ACSMADRSELLOAD5_LSB 12 +#define CSR_ACSMADRSELLOAD5_MASK GENMASK_32(13, 12) +#define CSR_ACSMBNKSELLOAD5_LSB 14 +#define CSR_ACSMBNKSELLOAD5_MASK BIT(14) +#define CSR_ACSMLONGBUBBLE5_LSB 15 +#define CSR_ACSMLONGBUBBLE5_MASK BIT(15) +/* CSR_ACSMSEQ3X6 */ +#define CSR_ACSMSEQ3X6_LSB 0 +#define CSR_ACSMSEQ3X6_MASK GENMASK_32(15, 0) +#define CSR_ACSMCMDREPCNT6_LSB 0 +#define CSR_ACSMCMDREPCNT6_MASK GENMASK_32(7, 0) +#define CSR_ACSMADRADV6_LSB 8 +#define CSR_ACSMADRADV6_MASK GENMASK_32(9, 8) +#define CSR_ACSMBNKADV6_LSB 10 +#define CSR_ACSMBNKADV6_MASK GENMASK_32(11, 10) +#define CSR_ACSMADRSELLOAD6_LSB 12 +#define CSR_ACSMADRSELLOAD6_MASK GENMASK_32(13, 12) +#define CSR_ACSMBNKSELLOAD6_LSB 14 +#define CSR_ACSMBNKSELLOAD6_MASK BIT(14) +#define CSR_ACSMLONGBUBBLE6_LSB 15 +#define CSR_ACSMLONGBUBBLE6_MASK BIT(15) +/* CSR_ACSMSEQ3X7 */ +#define CSR_ACSMSEQ3X7_LSB 0 +#define CSR_ACSMSEQ3X7_MASK GENMASK_32(15, 0) +#define CSR_ACSMCMDREPCNT7_LSB 0 +#define CSR_ACSMCMDREPCNT7_MASK GENMASK_32(7, 0) +#define CSR_ACSMADRADV7_LSB 8 +#define CSR_ACSMADRADV7_MASK GENMASK_32(9, 8) +#define CSR_ACSMBNKADV7_LSB 10 +#define CSR_ACSMBNKADV7_MASK GENMASK_32(11, 10) +#define CSR_ACSMADRSELLOAD7_LSB 12 +#define CSR_ACSMADRSELLOAD7_MASK GENMASK_32(13, 12) +#define CSR_ACSMBNKSELLOAD7_LSB 14 +#define CSR_ACSMBNKSELLOAD7_MASK BIT(14) +#define CSR_ACSMLONGBUBBLE7_LSB 15 +#define CSR_ACSMLONGBUBBLE7_MASK BIT(15) +/* CSR_ACSMSEQ3X8 */ +#define CSR_ACSMSEQ3X8_LSB 0 +#define CSR_ACSMSEQ3X8_MASK GENMASK_32(15, 0) +#define CSR_ACSMCMDREPCNT8_LSB 0 +#define CSR_ACSMCMDREPCNT8_MASK GENMASK_32(7, 0) +#define CSR_ACSMADRADV8_LSB 8 +#define CSR_ACSMADRADV8_MASK GENMASK_32(9, 8) +#define CSR_ACSMBNKADV8_LSB 10 +#define CSR_ACSMBNKADV8_MASK GENMASK_32(11, 10) +#define CSR_ACSMADRSELLOAD8_LSB 12 +#define CSR_ACSMADRSELLOAD8_MASK GENMASK_32(13, 12) +#define CSR_ACSMBNKSELLOAD8_LSB 14 +#define CSR_ACSMBNKSELLOAD8_MASK BIT(14) +#define CSR_ACSMLONGBUBBLE8_LSB 15 +#define CSR_ACSMLONGBUBBLE8_MASK BIT(15) +/* CSR_ACSMSEQ3X9 */ +#define CSR_ACSMSEQ3X9_LSB 0 +#define CSR_ACSMSEQ3X9_MASK GENMASK_32(15, 0) +#define CSR_ACSMCMDREPCNT9_LSB 0 +#define CSR_ACSMCMDREPCNT9_MASK GENMASK_32(7, 0) +#define CSR_ACSMADRADV9_LSB 8 +#define CSR_ACSMADRADV9_MASK GENMASK_32(9, 8) +#define CSR_ACSMBNKADV9_LSB 10 +#define CSR_ACSMBNKADV9_MASK GENMASK_32(11, 10) +#define CSR_ACSMADRSELLOAD9_LSB 12 +#define CSR_ACSMADRSELLOAD9_MASK GENMASK_32(13, 12) +#define CSR_ACSMBNKSELLOAD9_LSB 14 +#define CSR_ACSMBNKSELLOAD9_MASK BIT(14) +#define CSR_ACSMLONGBUBBLE9_LSB 15 +#define CSR_ACSMLONGBUBBLE9_MASK BIT(15) +/* CSR_ACSMSEQ3X10 */ +#define CSR_ACSMSEQ3X10_LSB 0 +#define CSR_ACSMSEQ3X10_MASK GENMASK_32(15, 0) +#define CSR_ACSMCMDREPCNT10_LSB 0 +#define CSR_ACSMCMDREPCNT10_MASK GENMASK_32(7, 0) +#define CSR_ACSMADRADV10_LSB 8 +#define CSR_ACSMADRADV10_MASK GENMASK_32(9, 8) +#define CSR_ACSMBNKADV10_LSB 10 +#define CSR_ACSMBNKADV10_MASK GENMASK_32(11, 10) +#define CSR_ACSMADRSELLOAD10_LSB 12 +#define CSR_ACSMADRSELLOAD10_MASK GENMASK_32(13, 12) +#define CSR_ACSMBNKSELLOAD10_LSB 14 +#define CSR_ACSMBNKSELLOAD10_MASK BIT(14) +#define CSR_ACSMLONGBUBBLE10_LSB 15 +#define CSR_ACSMLONGBUBBLE10_MASK BIT(15) +/* CSR_ACSMSEQ3X11 */ +#define CSR_ACSMSEQ3X11_LSB 0 +#define CSR_ACSMSEQ3X11_MASK GENMASK_32(15, 0) +#define CSR_ACSMCMDREPCNT11_LSB 0 +#define CSR_ACSMCMDREPCNT11_MASK GENMASK_32(7, 0) +#define CSR_ACSMADRADV11_LSB 8 +#define CSR_ACSMADRADV11_MASK GENMASK_32(9, 8) +#define CSR_ACSMBNKADV11_LSB 10 +#define CSR_ACSMBNKADV11_MASK GENMASK_32(11, 10) +#define CSR_ACSMADRSELLOAD11_LSB 12 +#define CSR_ACSMADRSELLOAD11_MASK GENMASK_32(13, 12) +#define CSR_ACSMBNKSELLOAD11_LSB 14 +#define CSR_ACSMBNKSELLOAD11_MASK BIT(14) +#define CSR_ACSMLONGBUBBLE11_LSB 15 +#define CSR_ACSMLONGBUBBLE11_MASK BIT(15) +/* CSR_ACSMSEQ3X12 */ +#define CSR_ACSMSEQ3X12_LSB 0 +#define CSR_ACSMSEQ3X12_MASK GENMASK_32(15, 0) +#define CSR_ACSMCMDREPCNT12_LSB 0 +#define CSR_ACSMCMDREPCNT12_MASK GENMASK_32(7, 0) +#define CSR_ACSMADRADV12_LSB 8 +#define CSR_ACSMADRADV12_MASK GENMASK_32(9, 8) +#define CSR_ACSMBNKADV12_LSB 10 +#define CSR_ACSMBNKADV12_MASK GENMASK_32(11, 10) +#define CSR_ACSMADRSELLOAD12_LSB 12 +#define CSR_ACSMADRSELLOAD12_MASK GENMASK_32(13, 12) +#define CSR_ACSMBNKSELLOAD12_LSB 14 +#define CSR_ACSMBNKSELLOAD12_MASK BIT(14) +#define CSR_ACSMLONGBUBBLE12_LSB 15 +#define CSR_ACSMLONGBUBBLE12_MASK BIT(15) +/* CSR_ACSMSEQ3X13 */ +#define CSR_ACSMSEQ3X13_LSB 0 +#define CSR_ACSMSEQ3X13_MASK GENMASK_32(15, 0) +#define CSR_ACSMCMDREPCNT13_LSB 0 +#define CSR_ACSMCMDREPCNT13_MASK GENMASK_32(7, 0) +#define CSR_ACSMADRADV13_LSB 8 +#define CSR_ACSMADRADV13_MASK GENMASK_32(9, 8) +#define CSR_ACSMBNKADV13_LSB 10 +#define CSR_ACSMBNKADV13_MASK GENMASK_32(11, 10) +#define CSR_ACSMADRSELLOAD13_LSB 12 +#define CSR_ACSMADRSELLOAD13_MASK GENMASK_32(13, 12) +#define CSR_ACSMBNKSELLOAD13_LSB 14 +#define CSR_ACSMBNKSELLOAD13_MASK BIT(14) +#define CSR_ACSMLONGBUBBLE13_LSB 15 +#define CSR_ACSMLONGBUBBLE13_MASK BIT(15) +/* CSR_ACSMSEQ3X14 */ +#define CSR_ACSMSEQ3X14_LSB 0 +#define CSR_ACSMSEQ3X14_MASK GENMASK_32(15, 0) +#define CSR_ACSMCMDREPCNT14_LSB 0 +#define CSR_ACSMCMDREPCNT14_MASK GENMASK_32(7, 0) +#define CSR_ACSMADRADV14_LSB 8 +#define CSR_ACSMADRADV14_MASK GENMASK_32(9, 8) +#define CSR_ACSMBNKADV14_LSB 10 +#define CSR_ACSMBNKADV14_MASK GENMASK_32(11, 10) +#define CSR_ACSMADRSELLOAD14_LSB 12 +#define CSR_ACSMADRSELLOAD14_MASK GENMASK_32(13, 12) +#define CSR_ACSMBNKSELLOAD14_LSB 14 +#define CSR_ACSMBNKSELLOAD14_MASK BIT(14) +#define CSR_ACSMLONGBUBBLE14_LSB 15 +#define CSR_ACSMLONGBUBBLE14_MASK BIT(15) +/* CSR_ACSMSEQ3X15 */ +#define CSR_ACSMSEQ3X15_LSB 0 +#define CSR_ACSMSEQ3X15_MASK GENMASK_32(15, 0) +#define CSR_ACSMCMDREPCNT15_LSB 0 +#define CSR_ACSMCMDREPCNT15_MASK GENMASK_32(7, 0) +#define CSR_ACSMADRADV15_LSB 8 +#define CSR_ACSMADRADV15_MASK GENMASK_32(9, 8) +#define CSR_ACSMBNKADV15_LSB 10 +#define CSR_ACSMBNKADV15_MASK GENMASK_32(11, 10) +#define CSR_ACSMADRSELLOAD15_LSB 12 +#define CSR_ACSMADRSELLOAD15_MASK GENMASK_32(13, 12) +#define CSR_ACSMBNKSELLOAD15_LSB 14 +#define CSR_ACSMBNKSELLOAD15_MASK BIT(14) +#define CSR_ACSMLONGBUBBLE15_LSB 15 +#define CSR_ACSMLONGBUBBLE15_MASK BIT(15) +/* CSR_ACSMSEQ3X16 */ +#define CSR_ACSMSEQ3X16_LSB 0 +#define CSR_ACSMSEQ3X16_MASK GENMASK_32(15, 0) +#define CSR_ACSMCMDREPCNT16_LSB 0 +#define CSR_ACSMCMDREPCNT16_MASK GENMASK_32(7, 0) +#define CSR_ACSMADRADV16_LSB 8 +#define CSR_ACSMADRADV16_MASK GENMASK_32(9, 8) +#define CSR_ACSMBNKADV16_LSB 10 +#define CSR_ACSMBNKADV16_MASK GENMASK_32(11, 10) +#define CSR_ACSMADRSELLOAD16_LSB 12 +#define CSR_ACSMADRSELLOAD16_MASK GENMASK_32(13, 12) +#define CSR_ACSMBNKSELLOAD16_LSB 14 +#define CSR_ACSMBNKSELLOAD16_MASK BIT(14) +#define CSR_ACSMLONGBUBBLE16_LSB 15 +#define CSR_ACSMLONGBUBBLE16_MASK BIT(15) +/* CSR_ACSMSEQ3X17 */ +#define CSR_ACSMSEQ3X17_LSB 0 +#define CSR_ACSMSEQ3X17_MASK GENMASK_32(15, 0) +#define CSR_ACSMCMDREPCNT17_LSB 0 +#define CSR_ACSMCMDREPCNT17_MASK GENMASK_32(7, 0) +#define CSR_ACSMADRADV17_LSB 8 +#define CSR_ACSMADRADV17_MASK GENMASK_32(9, 8) +#define CSR_ACSMBNKADV17_LSB 10 +#define CSR_ACSMBNKADV17_MASK GENMASK_32(11, 10) +#define CSR_ACSMADRSELLOAD17_LSB 12 +#define CSR_ACSMADRSELLOAD17_MASK GENMASK_32(13, 12) +#define CSR_ACSMBNKSELLOAD17_LSB 14 +#define CSR_ACSMBNKSELLOAD17_MASK BIT(14) +#define CSR_ACSMLONGBUBBLE17_LSB 15 +#define CSR_ACSMLONGBUBBLE17_MASK BIT(15) +/* CSR_ACSMSEQ3X18 */ +#define CSR_ACSMSEQ3X18_LSB 0 +#define CSR_ACSMSEQ3X18_MASK GENMASK_32(15, 0) +#define CSR_ACSMCMDREPCNT18_LSB 0 +#define CSR_ACSMCMDREPCNT18_MASK GENMASK_32(7, 0) +#define CSR_ACSMADRADV18_LSB 8 +#define CSR_ACSMADRADV18_MASK GENMASK_32(9, 8) +#define CSR_ACSMBNKADV18_LSB 10 +#define CSR_ACSMBNKADV18_MASK GENMASK_32(11, 10) +#define CSR_ACSMADRSELLOAD18_LSB 12 +#define CSR_ACSMADRSELLOAD18_MASK GENMASK_32(13, 12) +#define CSR_ACSMBNKSELLOAD18_LSB 14 +#define CSR_ACSMBNKSELLOAD18_MASK BIT(14) +#define CSR_ACSMLONGBUBBLE18_LSB 15 +#define CSR_ACSMLONGBUBBLE18_MASK BIT(15) +/* CSR_ACSMSEQ3X19 */ +#define CSR_ACSMSEQ3X19_LSB 0 +#define CSR_ACSMSEQ3X19_MASK GENMASK_32(15, 0) +#define CSR_ACSMCMDREPCNT19_LSB 0 +#define CSR_ACSMCMDREPCNT19_MASK GENMASK_32(7, 0) +#define CSR_ACSMADRADV19_LSB 8 +#define CSR_ACSMADRADV19_MASK GENMASK_32(9, 8) +#define CSR_ACSMBNKADV19_LSB 10 +#define CSR_ACSMBNKADV19_MASK GENMASK_32(11, 10) +#define CSR_ACSMADRSELLOAD19_LSB 12 +#define CSR_ACSMADRSELLOAD19_MASK GENMASK_32(13, 12) +#define CSR_ACSMBNKSELLOAD19_LSB 14 +#define CSR_ACSMBNKSELLOAD19_MASK BIT(14) +#define CSR_ACSMLONGBUBBLE19_LSB 15 +#define CSR_ACSMLONGBUBBLE19_MASK BIT(15) +/* CSR_ACSMSEQ3X20 */ +#define CSR_ACSMSEQ3X20_LSB 0 +#define CSR_ACSMSEQ3X20_MASK GENMASK_32(15, 0) +#define CSR_ACSMCMDREPCNT20_LSB 0 +#define CSR_ACSMCMDREPCNT20_MASK GENMASK_32(7, 0) +#define CSR_ACSMADRADV20_LSB 8 +#define CSR_ACSMADRADV20_MASK GENMASK_32(9, 8) +#define CSR_ACSMBNKADV20_LSB 10 +#define CSR_ACSMBNKADV20_MASK GENMASK_32(11, 10) +#define CSR_ACSMADRSELLOAD20_LSB 12 +#define CSR_ACSMADRSELLOAD20_MASK GENMASK_32(13, 12) +#define CSR_ACSMBNKSELLOAD20_LSB 14 +#define CSR_ACSMBNKSELLOAD20_MASK BIT(14) +#define CSR_ACSMLONGBUBBLE20_LSB 15 +#define CSR_ACSMLONGBUBBLE20_MASK BIT(15) +/* CSR_ACSMSEQ3X21 */ +#define CSR_ACSMSEQ3X21_LSB 0 +#define CSR_ACSMSEQ3X21_MASK GENMASK_32(15, 0) +#define CSR_ACSMCMDREPCNT21_LSB 0 +#define CSR_ACSMCMDREPCNT21_MASK GENMASK_32(7, 0) +#define CSR_ACSMADRADV21_LSB 8 +#define CSR_ACSMADRADV21_MASK GENMASK_32(9, 8) +#define CSR_ACSMBNKADV21_LSB 10 +#define CSR_ACSMBNKADV21_MASK GENMASK_32(11, 10) +#define CSR_ACSMADRSELLOAD21_LSB 12 +#define CSR_ACSMADRSELLOAD21_MASK GENMASK_32(13, 12) +#define CSR_ACSMBNKSELLOAD21_LSB 14 +#define CSR_ACSMBNKSELLOAD21_MASK BIT(14) +#define CSR_ACSMLONGBUBBLE21_LSB 15 +#define CSR_ACSMLONGBUBBLE21_MASK BIT(15) +/* CSR_ACSMSEQ3X22 */ +#define CSR_ACSMSEQ3X22_LSB 0 +#define CSR_ACSMSEQ3X22_MASK GENMASK_32(15, 0) +#define CSR_ACSMCMDREPCNT22_LSB 0 +#define CSR_ACSMCMDREPCNT22_MASK GENMASK_32(7, 0) +#define CSR_ACSMADRADV22_LSB 8 +#define CSR_ACSMADRADV22_MASK GENMASK_32(9, 8) +#define CSR_ACSMBNKADV22_LSB 10 +#define CSR_ACSMBNKADV22_MASK GENMASK_32(11, 10) +#define CSR_ACSMADRSELLOAD22_LSB 12 +#define CSR_ACSMADRSELLOAD22_MASK GENMASK_32(13, 12) +#define CSR_ACSMBNKSELLOAD22_LSB 14 +#define CSR_ACSMBNKSELLOAD22_MASK BIT(14) +#define CSR_ACSMLONGBUBBLE22_LSB 15 +#define CSR_ACSMLONGBUBBLE22_MASK BIT(15) +/* CSR_ACSMSEQ3X23 */ +#define CSR_ACSMSEQ3X23_LSB 0 +#define CSR_ACSMSEQ3X23_MASK GENMASK_32(15, 0) +#define CSR_ACSMCMDREPCNT23_LSB 0 +#define CSR_ACSMCMDREPCNT23_MASK GENMASK_32(7, 0) +#define CSR_ACSMADRADV23_LSB 8 +#define CSR_ACSMADRADV23_MASK GENMASK_32(9, 8) +#define CSR_ACSMBNKADV23_LSB 10 +#define CSR_ACSMBNKADV23_MASK GENMASK_32(11, 10) +#define CSR_ACSMADRSELLOAD23_LSB 12 +#define CSR_ACSMADRSELLOAD23_MASK GENMASK_32(13, 12) +#define CSR_ACSMBNKSELLOAD23_LSB 14 +#define CSR_ACSMBNKSELLOAD23_MASK BIT(14) +#define CSR_ACSMLONGBUBBLE23_LSB 15 +#define CSR_ACSMLONGBUBBLE23_MASK BIT(15) +/* CSR_ACSMSEQ3X24 */ +#define CSR_ACSMSEQ3X24_LSB 0 +#define CSR_ACSMSEQ3X24_MASK GENMASK_32(15, 0) +#define CSR_ACSMCMDREPCNT24_LSB 0 +#define CSR_ACSMCMDREPCNT24_MASK GENMASK_32(7, 0) +#define CSR_ACSMADRADV24_LSB 8 +#define CSR_ACSMADRADV24_MASK GENMASK_32(9, 8) +#define CSR_ACSMBNKADV24_LSB 10 +#define CSR_ACSMBNKADV24_MASK GENMASK_32(11, 10) +#define CSR_ACSMADRSELLOAD24_LSB 12 +#define CSR_ACSMADRSELLOAD24_MASK GENMASK_32(13, 12) +#define CSR_ACSMBNKSELLOAD24_LSB 14 +#define CSR_ACSMBNKSELLOAD24_MASK BIT(14) +#define CSR_ACSMLONGBUBBLE24_LSB 15 +#define CSR_ACSMLONGBUBBLE24_MASK BIT(15) +/* CSR_ACSMSEQ3X25 */ +#define CSR_ACSMSEQ3X25_LSB 0 +#define CSR_ACSMSEQ3X25_MASK GENMASK_32(15, 0) +#define CSR_ACSMCMDREPCNT25_LSB 0 +#define CSR_ACSMCMDREPCNT25_MASK GENMASK_32(7, 0) +#define CSR_ACSMADRADV25_LSB 8 +#define CSR_ACSMADRADV25_MASK GENMASK_32(9, 8) +#define CSR_ACSMBNKADV25_LSB 10 +#define CSR_ACSMBNKADV25_MASK GENMASK_32(11, 10) +#define CSR_ACSMADRSELLOAD25_LSB 12 +#define CSR_ACSMADRSELLOAD25_MASK GENMASK_32(13, 12) +#define CSR_ACSMBNKSELLOAD25_LSB 14 +#define CSR_ACSMBNKSELLOAD25_MASK BIT(14) +#define CSR_ACSMLONGBUBBLE25_LSB 15 +#define CSR_ACSMLONGBUBBLE25_MASK BIT(15) +/* CSR_ACSMSEQ3X26 */ +#define CSR_ACSMSEQ3X26_LSB 0 +#define CSR_ACSMSEQ3X26_MASK GENMASK_32(15, 0) +#define CSR_ACSMCMDREPCNT26_LSB 0 +#define CSR_ACSMCMDREPCNT26_MASK GENMASK_32(7, 0) +#define CSR_ACSMADRADV26_LSB 8 +#define CSR_ACSMADRADV26_MASK GENMASK_32(9, 8) +#define CSR_ACSMBNKADV26_LSB 10 +#define CSR_ACSMBNKADV26_MASK GENMASK_32(11, 10) +#define CSR_ACSMADRSELLOAD26_LSB 12 +#define CSR_ACSMADRSELLOAD26_MASK GENMASK_32(13, 12) +#define CSR_ACSMBNKSELLOAD26_LSB 14 +#define CSR_ACSMBNKSELLOAD26_MASK BIT(14) +#define CSR_ACSMLONGBUBBLE26_LSB 15 +#define CSR_ACSMLONGBUBBLE26_MASK BIT(15) +/* CSR_ACSMSEQ3X27 */ +#define CSR_ACSMSEQ3X27_LSB 0 +#define CSR_ACSMSEQ3X27_MASK GENMASK_32(15, 0) +#define CSR_ACSMCMDREPCNT27_LSB 0 +#define CSR_ACSMCMDREPCNT27_MASK GENMASK_32(7, 0) +#define CSR_ACSMADRADV27_LSB 8 +#define CSR_ACSMADRADV27_MASK GENMASK_32(9, 8) +#define CSR_ACSMBNKADV27_LSB 10 +#define CSR_ACSMBNKADV27_MASK GENMASK_32(11, 10) +#define CSR_ACSMADRSELLOAD27_LSB 12 +#define CSR_ACSMADRSELLOAD27_MASK GENMASK_32(13, 12) +#define CSR_ACSMBNKSELLOAD27_LSB 14 +#define CSR_ACSMBNKSELLOAD27_MASK BIT(14) +#define CSR_ACSMLONGBUBBLE27_LSB 15 +#define CSR_ACSMLONGBUBBLE27_MASK BIT(15) +/* CSR_ACSMSEQ3X28 */ +#define CSR_ACSMSEQ3X28_LSB 0 +#define CSR_ACSMSEQ3X28_MASK GENMASK_32(15, 0) +#define CSR_ACSMCMDREPCNT28_LSB 0 +#define CSR_ACSMCMDREPCNT28_MASK GENMASK_32(7, 0) +#define CSR_ACSMADRADV28_LSB 8 +#define CSR_ACSMADRADV28_MASK GENMASK_32(9, 8) +#define CSR_ACSMBNKADV28_LSB 10 +#define CSR_ACSMBNKADV28_MASK GENMASK_32(11, 10) +#define CSR_ACSMADRSELLOAD28_LSB 12 +#define CSR_ACSMADRSELLOAD28_MASK GENMASK_32(13, 12) +#define CSR_ACSMBNKSELLOAD28_LSB 14 +#define CSR_ACSMBNKSELLOAD28_MASK BIT(14) +#define CSR_ACSMLONGBUBBLE28_LSB 15 +#define CSR_ACSMLONGBUBBLE28_MASK BIT(15) +/* CSR_ACSMSEQ3X29 */ +#define CSR_ACSMSEQ3X29_LSB 0 +#define CSR_ACSMSEQ3X29_MASK GENMASK_32(15, 0) +#define CSR_ACSMCMDREPCNT29_LSB 0 +#define CSR_ACSMCMDREPCNT29_MASK GENMASK_32(7, 0) +#define CSR_ACSMADRADV29_LSB 8 +#define CSR_ACSMADRADV29_MASK GENMASK_32(9, 8) +#define CSR_ACSMBNKADV29_LSB 10 +#define CSR_ACSMBNKADV29_MASK GENMASK_32(11, 10) +#define CSR_ACSMADRSELLOAD29_LSB 12 +#define CSR_ACSMADRSELLOAD29_MASK GENMASK_32(13, 12) +#define CSR_ACSMBNKSELLOAD29_LSB 14 +#define CSR_ACSMBNKSELLOAD29_MASK BIT(14) +#define CSR_ACSMLONGBUBBLE29_LSB 15 +#define CSR_ACSMLONGBUBBLE29_MASK BIT(15) +/* CSR_ACSMSEQ3X30 */ +#define CSR_ACSMSEQ3X30_LSB 0 +#define CSR_ACSMSEQ3X30_MASK GENMASK_32(15, 0) +#define CSR_ACSMCMDREPCNT30_LSB 0 +#define CSR_ACSMCMDREPCNT30_MASK GENMASK_32(7, 0) +#define CSR_ACSMADRADV30_LSB 8 +#define CSR_ACSMADRADV30_MASK GENMASK_32(9, 8) +#define CSR_ACSMBNKADV30_LSB 10 +#define CSR_ACSMBNKADV30_MASK GENMASK_32(11, 10) +#define CSR_ACSMADRSELLOAD30_LSB 12 +#define CSR_ACSMADRSELLOAD30_MASK GENMASK_32(13, 12) +#define CSR_ACSMBNKSELLOAD30_LSB 14 +#define CSR_ACSMBNKSELLOAD30_MASK BIT(14) +#define CSR_ACSMLONGBUBBLE30_LSB 15 +#define CSR_ACSMLONGBUBBLE30_MASK BIT(15) +/* CSR_ACSMSEQ3X31 */ +#define CSR_ACSMSEQ3X31_LSB 0 +#define CSR_ACSMSEQ3X31_MASK GENMASK_32(15, 0) +#define CSR_ACSMCMDREPCNT31_LSB 0 +#define CSR_ACSMCMDREPCNT31_MASK GENMASK_32(7, 0) +#define CSR_ACSMADRADV31_LSB 8 +#define CSR_ACSMADRADV31_MASK GENMASK_32(9, 8) +#define CSR_ACSMBNKADV31_LSB 10 +#define CSR_ACSMBNKADV31_MASK GENMASK_32(11, 10) +#define CSR_ACSMADRSELLOAD31_LSB 12 +#define CSR_ACSMADRSELLOAD31_MASK GENMASK_32(13, 12) +#define CSR_ACSMBNKSELLOAD31_LSB 14 +#define CSR_ACSMBNKSELLOAD31_MASK BIT(14) +#define CSR_ACSMLONGBUBBLE31_LSB 15 +#define CSR_ACSMLONGBUBBLE31_MASK BIT(15) +/* CSR_ACSMPLAYBACK0X0 */ +#define CSR_ACSMPLAYBACK0X0_LSB 0 +#define CSR_ACSMPLAYBACK0X0_MASK GENMASK_32(11, 0) +/* CSR_ACSMPLAYBACK1X0 */ +#define CSR_ACSMPLAYBACK1X0_LSB 0 +#define CSR_ACSMPLAYBACK1X0_MASK GENMASK_32(11, 0) +/* CSR_ACSMPLAYBACK0X1 */ +#define CSR_ACSMPLAYBACK0X1_LSB 0 +#define CSR_ACSMPLAYBACK0X1_MASK GENMASK_32(11, 0) +/* CSR_ACSMPLAYBACK1X1 */ +#define CSR_ACSMPLAYBACK1X1_LSB 0 +#define CSR_ACSMPLAYBACK1X1_MASK GENMASK_32(11, 0) +/* CSR_ACSMPLAYBACK0X2 */ +#define CSR_ACSMPLAYBACK0X2_LSB 0 +#define CSR_ACSMPLAYBACK0X2_MASK GENMASK_32(11, 0) +/* CSR_ACSMPLAYBACK1X2 */ +#define CSR_ACSMPLAYBACK1X2_LSB 0 +#define CSR_ACSMPLAYBACK1X2_MASK GENMASK_32(11, 0) +/* CSR_ACSMPLAYBACK0X3 */ +#define CSR_ACSMPLAYBACK0X3_LSB 0 +#define CSR_ACSMPLAYBACK0X3_MASK GENMASK_32(11, 0) +/* CSR_ACSMPLAYBACK1X3 */ +#define CSR_ACSMPLAYBACK1X3_LSB 0 +#define CSR_ACSMPLAYBACK1X3_MASK GENMASK_32(11, 0) +/* CSR_ACSMPLAYBACK0X4 */ +#define CSR_ACSMPLAYBACK0X4_LSB 0 +#define CSR_ACSMPLAYBACK0X4_MASK GENMASK_32(11, 0) +/* CSR_ACSMPLAYBACK1X4 */ +#define CSR_ACSMPLAYBACK1X4_LSB 0 +#define CSR_ACSMPLAYBACK1X4_MASK GENMASK_32(11, 0) +/* CSR_ACSMPLAYBACK0X5 */ +#define CSR_ACSMPLAYBACK0X5_LSB 0 +#define CSR_ACSMPLAYBACK0X5_MASK GENMASK_32(11, 0) +/* CSR_ACSMPLAYBACK1X5 */ +#define CSR_ACSMPLAYBACK1X5_LSB 0 +#define CSR_ACSMPLAYBACK1X5_MASK GENMASK_32(11, 0) +/* CSR_ACSMPLAYBACK0X6 */ +#define CSR_ACSMPLAYBACK0X6_LSB 0 +#define CSR_ACSMPLAYBACK0X6_MASK GENMASK_32(11, 0) +/* CSR_ACSMPLAYBACK1X6 */ +#define CSR_ACSMPLAYBACK1X6_LSB 0 +#define CSR_ACSMPLAYBACK1X6_MASK GENMASK_32(11, 0) +/* CSR_ACSMPLAYBACK0X7 */ +#define CSR_ACSMPLAYBACK0X7_LSB 0 +#define CSR_ACSMPLAYBACK0X7_MASK GENMASK_32(11, 0) +/* CSR_ACSMPLAYBACK1X7 */ +#define CSR_ACSMPLAYBACK1X7_LSB 0 +#define CSR_ACSMPLAYBACK1X7_MASK GENMASK_32(11, 0) +/* CSR_ACSMPSTATEOVREN */ +#define CSR_ACSMPSTATEOVREN_LSB 0 +#define CSR_ACSMPSTATEOVREN_MASK BIT(0) +/* CSR_ACSMPSTATEOVRVAL */ +#define CSR_ACSMPSTATEOVRVAL_LSB 0 +#define CSR_ACSMPSTATEOVRVAL_MASK GENMASK_32(3, 0) +/* CSR_ACSMCTRL23 */ +#define CSR_ACSMCTRL23_LSB 0 +#define CSR_ACSMCTRL23_MASK GENMASK_32(12, 0) +#define CSR_ACSMCSMASK_LSB 0 +#define CSR_ACSMCSMASK_MASK GENMASK_32(7, 0) +#define CSR_ACSMCSMODE_LSB 8 +#define CSR_ACSMCSMODE_MASK BIT(8) +#define CSR_ACSMPARMASK_LSB 9 +#define CSR_ACSMPARMASK_MASK GENMASK_32(12, 9) +/* CSR_ACSMCKEVAL */ +#define CSR_ACSMCKEVAL_LSB 0 +#define CSR_ACSMCKEVAL_MASK GENMASK_32(3, 0) +/* CSR_LOWSPEEDCLOCKDIVIDER */ +#define CSR_LOWSPEEDCLOCKDIVIDER_LSB 0 +#define CSR_LOWSPEEDCLOCKDIVIDER_MASK GENMASK_32(5, 0) +/* CSR_ACSMCSMAPCTRL0 */ +#define CSR_ACSMCSMAPCTRL0_LSB 0 +#define CSR_ACSMCSMAPCTRL0_MASK GENMASK_32(14, 0) +#define CSR_ACSMCSMAP0_LSB 0 +#define CSR_ACSMCSMAP0_MASK GENMASK_32(7, 0) +#define CSR_ACSMDESTMAP0_LSB 8 +#define CSR_ACSMDESTMAP0_MASK GENMASK_32(11, 8) +#define CSR_ACSMODTMAP0_LSB 12 +#define CSR_ACSMODTMAP0_MASK GENMASK_32(14, 12) +/* CSR_ACSMCSMAPCTRL1 */ +#define CSR_ACSMCSMAPCTRL1_LSB 0 +#define CSR_ACSMCSMAPCTRL1_MASK GENMASK_32(14, 0) +#define CSR_ACSMCSMAP1_LSB 0 +#define CSR_ACSMCSMAP1_MASK GENMASK_32(7, 0) +#define CSR_ACSMDESTMAP1_LSB 8 +#define CSR_ACSMDESTMAP1_MASK GENMASK_32(11, 8) +#define CSR_ACSMODTMAP1_LSB 12 +#define CSR_ACSMODTMAP1_MASK GENMASK_32(14, 12) +/* CSR_ACSMCSMAPCTRL2 */ +#define CSR_ACSMCSMAPCTRL2_LSB 0 +#define CSR_ACSMCSMAPCTRL2_MASK GENMASK_32(14, 0) +#define CSR_ACSMCSMAP2_LSB 0 +#define CSR_ACSMCSMAP2_MASK GENMASK_32(7, 0) +#define CSR_ACSMDESTMAP2_LSB 8 +#define CSR_ACSMDESTMAP2_MASK GENMASK_32(11, 8) +#define CSR_ACSMODTMAP2_LSB 12 +#define CSR_ACSMODTMAP2_MASK GENMASK_32(14, 12) +/* CSR_ACSMCSMAPCTRL3 */ +#define CSR_ACSMCSMAPCTRL3_LSB 0 +#define CSR_ACSMCSMAPCTRL3_MASK GENMASK_32(14, 0) +#define CSR_ACSMCSMAP3_LSB 0 +#define CSR_ACSMCSMAP3_MASK GENMASK_32(7, 0) +#define CSR_ACSMDESTMAP3_LSB 8 +#define CSR_ACSMDESTMAP3_MASK GENMASK_32(11, 8) +#define CSR_ACSMODTMAP3_LSB 12 +#define CSR_ACSMODTMAP3_MASK GENMASK_32(14, 12) +/* CSR_ACSMCSMAPCTRL4 */ +#define CSR_ACSMCSMAPCTRL4_LSB 0 +#define CSR_ACSMCSMAPCTRL4_MASK GENMASK_32(14, 0) +#define CSR_ACSMCSMAP4_LSB 0 +#define CSR_ACSMCSMAP4_MASK GENMASK_32(7, 0) +#define CSR_ACSMDESTMAP4_LSB 8 +#define CSR_ACSMDESTMAP4_MASK GENMASK_32(11, 8) +#define CSR_ACSMODTMAP4_LSB 12 +#define CSR_ACSMODTMAP4_MASK GENMASK_32(14, 12) +/* CSR_ACSMCSMAPCTRL5 */ +#define CSR_ACSMCSMAPCTRL5_LSB 0 +#define CSR_ACSMCSMAPCTRL5_MASK GENMASK_32(14, 0) +#define CSR_ACSMCSMAP5_LSB 0 +#define CSR_ACSMCSMAP5_MASK GENMASK_32(7, 0) +#define CSR_ACSMDESTMAP5_LSB 8 +#define CSR_ACSMDESTMAP5_MASK GENMASK_32(11, 8) +#define CSR_ACSMODTMAP5_LSB 12 +#define CSR_ACSMODTMAP5_MASK GENMASK_32(14, 12) +/* CSR_ACSMCSMAPCTRL6 */ +#define CSR_ACSMCSMAPCTRL6_LSB 0 +#define CSR_ACSMCSMAPCTRL6_MASK GENMASK_32(14, 0) +#define CSR_ACSMCSMAP6_LSB 0 +#define CSR_ACSMCSMAP6_MASK GENMASK_32(7, 0) +#define CSR_ACSMDESTMAP6_LSB 8 +#define CSR_ACSMDESTMAP6_MASK GENMASK_32(11, 8) +#define CSR_ACSMODTMAP6_LSB 12 +#define CSR_ACSMODTMAP6_MASK GENMASK_32(14, 12) +/* CSR_ACSMCSMAPCTRL7 */ +#define CSR_ACSMCSMAPCTRL7_LSB 0 +#define CSR_ACSMCSMAPCTRL7_MASK GENMASK_32(14, 0) +#define CSR_ACSMCSMAP7_LSB 0 +#define CSR_ACSMCSMAP7_MASK GENMASK_32(7, 0) +#define CSR_ACSMDESTMAP7_LSB 8 +#define CSR_ACSMDESTMAP7_MASK GENMASK_32(11, 8) +#define CSR_ACSMODTMAP7_LSB 12 +#define CSR_ACSMODTMAP7_MASK GENMASK_32(14, 12) +/* CSR_ACSMCSMAPCTRL8 */ +#define CSR_ACSMCSMAPCTRL8_LSB 0 +#define CSR_ACSMCSMAPCTRL8_MASK GENMASK_32(14, 0) +#define CSR_ACSMCSMAP8_LSB 0 +#define CSR_ACSMCSMAP8_MASK GENMASK_32(7, 0) +#define CSR_ACSMDESTMAP8_LSB 8 +#define CSR_ACSMDESTMAP8_MASK GENMASK_32(11, 8) +#define CSR_ACSMODTMAP8_LSB 12 +#define CSR_ACSMODTMAP8_MASK GENMASK_32(14, 12) +/* CSR_ACSMCSMAPCTRL9 */ +#define CSR_ACSMCSMAPCTRL9_LSB 0 +#define CSR_ACSMCSMAPCTRL9_MASK GENMASK_32(14, 0) +#define CSR_ACSMCSMAP9_LSB 0 +#define CSR_ACSMCSMAP9_MASK GENMASK_32(7, 0) +#define CSR_ACSMDESTMAP9_LSB 8 +#define CSR_ACSMDESTMAP9_MASK GENMASK_32(11, 8) +#define CSR_ACSMODTMAP9_LSB 12 +#define CSR_ACSMODTMAP9_MASK GENMASK_32(14, 12) +/* CSR_ACSMCSMAPCTRL10 */ +#define CSR_ACSMCSMAPCTRL10_LSB 0 +#define CSR_ACSMCSMAPCTRL10_MASK GENMASK_32(14, 0) +#define CSR_ACSMCSMAP10_LSB 0 +#define CSR_ACSMCSMAP10_MASK GENMASK_32(7, 0) +#define CSR_ACSMDESTMAP10_LSB 8 +#define CSR_ACSMDESTMAP10_MASK GENMASK_32(11, 8) +#define CSR_ACSMODTMAP10_LSB 12 +#define CSR_ACSMODTMAP10_MASK GENMASK_32(14, 12) +/* CSR_ACSMCSMAPCTRL11 */ +#define CSR_ACSMCSMAPCTRL11_LSB 0 +#define CSR_ACSMCSMAPCTRL11_MASK GENMASK_32(14, 0) +#define CSR_ACSMCSMAP11_LSB 0 +#define CSR_ACSMCSMAP11_MASK GENMASK_32(7, 0) +#define CSR_ACSMDESTMAP11_LSB 8 +#define CSR_ACSMDESTMAP11_MASK GENMASK_32(11, 8) +#define CSR_ACSMODTMAP11_LSB 12 +#define CSR_ACSMODTMAP11_MASK GENMASK_32(14, 12) +/* CSR_ACSMCSMAPCTRL12 */ +#define CSR_ACSMCSMAPCTRL12_LSB 0 +#define CSR_ACSMCSMAPCTRL12_MASK GENMASK_32(14, 0) +#define CSR_ACSMCSMAP12_LSB 0 +#define CSR_ACSMCSMAP12_MASK GENMASK_32(7, 0) +#define CSR_ACSMDESTMAP12_LSB 8 +#define CSR_ACSMDESTMAP12_MASK GENMASK_32(11, 8) +#define CSR_ACSMODTMAP12_LSB 12 +#define CSR_ACSMODTMAP12_MASK GENMASK_32(14, 12) +/* CSR_ACSMCSMAPCTRL13 */ +#define CSR_ACSMCSMAPCTRL13_LSB 0 +#define CSR_ACSMCSMAPCTRL13_MASK GENMASK_32(14, 0) +#define CSR_ACSMCSMAP13_LSB 0 +#define CSR_ACSMCSMAP13_MASK GENMASK_32(7, 0) +#define CSR_ACSMDESTMAP13_LSB 8 +#define CSR_ACSMDESTMAP13_MASK GENMASK_32(11, 8) +#define CSR_ACSMODTMAP13_LSB 12 +#define CSR_ACSMODTMAP13_MASK GENMASK_32(14, 12) +/* CSR_ACSMCSMAPCTRL14 */ +#define CSR_ACSMCSMAPCTRL14_LSB 0 +#define CSR_ACSMCSMAPCTRL14_MASK GENMASK_32(14, 0) +#define CSR_ACSMCSMAP14_LSB 0 +#define CSR_ACSMCSMAP14_MASK GENMASK_32(7, 0) +#define CSR_ACSMDESTMAP14_LSB 8 +#define CSR_ACSMDESTMAP14_MASK GENMASK_32(11, 8) +#define CSR_ACSMODTMAP14_LSB 12 +#define CSR_ACSMODTMAP14_MASK GENMASK_32(14, 12) +/* CSR_ACSMCSMAPCTRL15 */ +#define CSR_ACSMCSMAPCTRL15_LSB 0 +#define CSR_ACSMCSMAPCTRL15_MASK GENMASK_32(14, 0) +#define CSR_ACSMCSMAP15_LSB 0 +#define CSR_ACSMCSMAP15_MASK GENMASK_32(7, 0) +#define CSR_ACSMDESTMAP15_LSB 8 +#define CSR_ACSMDESTMAP15_MASK GENMASK_32(11, 8) +#define CSR_ACSMODTMAP15_LSB 12 +#define CSR_ACSMODTMAP15_MASK GENMASK_32(14, 12) +/* CSR_ACSMODTCTRL0 */ +#define CSR_ACSMODTCTRL0_LSB 0 +#define CSR_ACSMODTCTRL0_MASK GENMASK_32(7, 0) +#define CSR_ACSMODTWRPATCS0_LSB 0 +#define CSR_ACSMODTWRPATCS0_MASK GENMASK_32(3, 0) +#define CSR_ACSMODTRDPATCS0_LSB 4 +#define CSR_ACSMODTRDPATCS0_MASK GENMASK_32(7, 4) +/* CSR_ACSMODTCTRL1 */ +#define CSR_ACSMODTCTRL1_LSB 0 +#define CSR_ACSMODTCTRL1_MASK GENMASK_32(7, 0) +#define CSR_ACSMODTWRPATCS1_LSB 0 +#define CSR_ACSMODTWRPATCS1_MASK GENMASK_32(3, 0) +#define CSR_ACSMODTRDPATCS1_LSB 4 +#define CSR_ACSMODTRDPATCS1_MASK GENMASK_32(7, 4) +/* CSR_ACSMODTCTRL2 */ +#define CSR_ACSMODTCTRL2_LSB 0 +#define CSR_ACSMODTCTRL2_MASK GENMASK_32(7, 0) +#define CSR_ACSMODTWRPATCS2_LSB 0 +#define CSR_ACSMODTWRPATCS2_MASK GENMASK_32(3, 0) +#define CSR_ACSMODTRDPATCS2_LSB 4 +#define CSR_ACSMODTRDPATCS2_MASK GENMASK_32(7, 4) +/* CSR_ACSMODTCTRL3 */ +#define CSR_ACSMODTCTRL3_LSB 0 +#define CSR_ACSMODTCTRL3_MASK GENMASK_32(7, 0) +#define CSR_ACSMODTWRPATCS3_LSB 0 +#define CSR_ACSMODTWRPATCS3_MASK GENMASK_32(3, 0) +#define CSR_ACSMODTRDPATCS3_LSB 4 +#define CSR_ACSMODTRDPATCS3_MASK GENMASK_32(7, 4) +/* CSR_ACSMODTCTRL4 */ +#define CSR_ACSMODTCTRL4_LSB 0 +#define CSR_ACSMODTCTRL4_MASK GENMASK_32(7, 0) +#define CSR_ACSMODTWRPATCS4_LSB 0 +#define CSR_ACSMODTWRPATCS4_MASK GENMASK_32(3, 0) +#define CSR_ACSMODTRDPATCS4_LSB 4 +#define CSR_ACSMODTRDPATCS4_MASK GENMASK_32(7, 4) +/* CSR_ACSMODTCTRL5 */ +#define CSR_ACSMODTCTRL5_LSB 0 +#define CSR_ACSMODTCTRL5_MASK GENMASK_32(7, 0) +#define CSR_ACSMODTWRPATCS5_LSB 0 +#define CSR_ACSMODTWRPATCS5_MASK GENMASK_32(3, 0) +#define CSR_ACSMODTRDPATCS5_LSB 4 +#define CSR_ACSMODTRDPATCS5_MASK GENMASK_32(7, 4) +/* CSR_ACSMODTCTRL6 */ +#define CSR_ACSMODTCTRL6_LSB 0 +#define CSR_ACSMODTCTRL6_MASK GENMASK_32(7, 0) +#define CSR_ACSMODTWRPATCS6_LSB 0 +#define CSR_ACSMODTWRPATCS6_MASK GENMASK_32(3, 0) +#define CSR_ACSMODTRDPATCS6_LSB 4 +#define CSR_ACSMODTRDPATCS6_MASK GENMASK_32(7, 4) +/* CSR_ACSMODTCTRL7 */ +#define CSR_ACSMODTCTRL7_LSB 0 +#define CSR_ACSMODTCTRL7_MASK GENMASK_32(7, 0) +#define CSR_ACSMODTWRPATCS7_LSB 0 +#define CSR_ACSMODTWRPATCS7_MASK GENMASK_32(3, 0) +#define CSR_ACSMODTRDPATCS7_LSB 4 +#define CSR_ACSMODTRDPATCS7_MASK GENMASK_32(7, 4) +/* CSR_ACSMODTCTRL8 */ +#define CSR_ACSMODTCTRL8_LSB 0 +#define CSR_ACSMODTCTRL8_MASK GENMASK_32(15, 0) +#define CSR_ACSMODTWRDURCTRL_LSB 0 +#define CSR_ACSMODTWRDURCTRL_MASK GENMASK_32(3, 0) +#define CSR_ACSMODTRDDURCTRL_LSB 4 +#define CSR_ACSMODTRDDURCTRL_MASK GENMASK_32(7, 4) +#define CSR_ACSMODTWRSTRTCTRL_LSB 8 +#define CSR_ACSMODTWRSTRTCTRL_MASK GENMASK_32(11, 8) +#define CSR_ACSMODTRDSTRTCTRL_LSB 12 +#define CSR_ACSMODTRDSTRTCTRL_MASK GENMASK_32(15, 12) +/* CSR_ACSMCTRL16 */ +#define CSR_ACSMCTRL16_LSB 0 +#define CSR_ACSMCTRL16_MASK GENMASK_32(15, 0) +#define CSR_ACSMDDRADRUP_LSB 0 +#define CSR_ACSMDDRADRUP_MASK GENMASK_32(3, 0) +#define CSR_ACSMHIGHADDR_LSB 4 +#define CSR_ACSMHIGHADDR_MASK BIT(4) +#define CSR_ACSMADR13PLUGHOLE_LSB 5 +#define CSR_ACSMADR13PLUGHOLE_MASK BIT(5) +#define CSR_ACSMCTRL16RSVD_LSB 6 +#define CSR_ACSMCTRL16RSVD_MASK BIT(6) +#define CSR_ACSMWRTLVLODTCTRL_LSB 7 +#define CSR_ACSMWRTLVLODTCTRL_MASK BIT(7) +#define CSR_ACSMWRTLVLODT_LSB 8 +#define CSR_ACSMWRTLVLODT_MASK GENMASK_32(11, 8) +#define CSR_ACSM2TGRPINHIBIT_LSB 12 +#define CSR_ACSM2TGRPINHIBIT_MASK GENMASK_32(15, 12) +/* CSR_LOWSPEEDCLOCKSTOPVAL */ +#define CSR_LOWSPEEDCLOCKSTOPVAL_LSB 0 +#define CSR_LOWSPEEDCLOCKSTOPVAL_MASK BIT(0) +/* CSR_ACSMCTRL18 */ +#define CSR_ACSMCTRL18_LSB 0 +#define CSR_ACSMCTRL18_MASK GENMASK_32(1, 0) +#define CSR_ACSMLOCALDONE_LSB 0 +#define CSR_ACSMLOCALDONE_MASK BIT(0) +#define CSR_ACSMSTOPONERRASRTD_LSB 1 +#define CSR_ACSMSTOPONERRASRTD_MASK BIT(1) +/* CSR_ACSMCTRL19 */ +#define CSR_ACSMCTRL19_LSB 0 +#define CSR_ACSMCTRL19_MASK GENMASK_32(2, 0) +#define CSR_ACSMVISSEL_LSB 0 +#define CSR_ACSMVISSEL_MASK GENMASK_32(2, 0) +/* CSR_ACSMCTRL20 */ +#define CSR_ACSMCTRL20_LSB 0 +#define CSR_ACSMCTRL20_MASK GENMASK_32(15, 0) +#define CSR_ACSMVISVAL_LSB 0 +#define CSR_ACSMVISVAL_MASK GENMASK_32(15, 0) +/* CSR_ACSMCTRL21 */ +#define CSR_ACSMCTRL21_LSB 0 +#define CSR_ACSMCTRL21_MASK GENMASK_32(11, 0) +#define CSR_ACSMMAPDIMMCS0_LSB 0 +#define CSR_ACSMMAPDIMMCS0_MASK GENMASK_32(2, 0) +#define CSR_ACSMMAPDIMMCS1_LSB 3 +#define CSR_ACSMMAPDIMMCS1_MASK GENMASK_32(5, 3) +#define CSR_ACSMMAPDIMMCS2_LSB 6 +#define CSR_ACSMMAPDIMMCS2_MASK GENMASK_32(8, 6) +#define CSR_ACSMMAPDIMMCS3_LSB 9 +#define CSR_ACSMMAPDIMMCS3_MASK GENMASK_32(11, 9) +/* CSR_ACSMCTRL22 */ +#define CSR_ACSMCTRL22_LSB 0 +#define CSR_ACSMCTRL22_MASK GENMASK_32(11, 0) +#define CSR_ACSMMAPDIMMCS4_LSB 0 +#define CSR_ACSMMAPDIMMCS4_MASK GENMASK_32(2, 0) +#define CSR_ACSMMAPDIMMCS5_LSB 3 +#define CSR_ACSMMAPDIMMCS5_MASK GENMASK_32(5, 3) +#define CSR_ACSMMAPDIMMCS6_LSB 6 +#define CSR_ACSMMAPDIMMCS6_MASK GENMASK_32(8, 6) +#define CSR_ACSMMAPDIMMCS7_LSB 9 +#define CSR_ACSMMAPDIMMCS7_MASK GENMASK_32(11, 9) +/* CSR_ACSMCTRL0 */ +#define CSR_ACSMCTRL0_LSB 0 +#define CSR_ACSMCTRL0_MASK GENMASK_32(15, 0) +#define CSR_ACSMRSVDCTRL00_LSB 0 +#define CSR_ACSMRSVDCTRL00_MASK BIT(0) +#define CSR_ACSMDYNBLMODE_LSB 1 +#define CSR_ACSMDYNBLMODE_MASK BIT(1) +#define CSR_ACSMBURSTLEN_LSB 2 +#define CSR_ACSMBURSTLEN_MASK BIT(2) +#define CSR_ACSMINFLOOP_LSB 3 +#define CSR_ACSMINFLOOP_MASK BIT(3) +#define CSR_ACSMRXVALMODE_LSB 4 +#define CSR_ACSMRXVALMODE_MASK BIT(4) +#define CSR_ACSMSTPONERRMODE_LSB 5 +#define CSR_ACSMSTPONERRMODE_MASK BIT(5) +#define CSR_ACSM2TMODE_LSB 6 +#define CSR_ACSM2TMODE_MASK BIT(6) +#define CSR_ACSMTRAINSOEMODE_LSB 7 +#define CSR_ACSMTRAINSOEMODE_MASK BIT(7) +#define CSR_ACSMGATEDDRCMD_LSB 8 +#define CSR_ACSMGATEDDRCMD_MASK BIT(8) +#define CSR_ACSMGEARDOWNMODE_LSB 9 +#define CSR_ACSMGEARDOWNMODE_MASK BIT(9) +#define CSR_ACSMGEARDOWNPHASE_LSB 10 +#define CSR_ACSMGEARDOWNPHASE_MASK BIT(10) +#define CSR_ACSMGEARDOWNSYNC_LSB 11 +#define CSR_ACSMGEARDOWNSYNC_MASK BIT(11) +#define CSR_ACSMCAPRBSMODE_LSB 12 +#define CSR_ACSMCAPRBSMODE_MASK BIT(12) +#define CSR_ACSMGATERXFIFOWRITE_LSB 13 +#define CSR_ACSMGATERXFIFOWRITE_MASK BIT(13) +#define CSR_ACSMPARMODE_LSB 14 +#define CSR_ACSMPARMODE_MASK BIT(14) +#define CSR_ACSMTDSMODE_LSB 15 +#define CSR_ACSMTDSMODE_MASK BIT(15) +/* CSR_ACSMCTRL1 */ +#define CSR_ACSMCTRL1_LSB 0 +#define CSR_ACSMCTRL1_MASK GENMASK_32(15, 0) +#define CSR_ACSMREPCNT_LSB 0 +#define CSR_ACSMREPCNT_MASK GENMASK_32(15, 0) +/* CSR_ACSMCTRL2 */ +#define CSR_ACSMCTRL2_LSB 0 +#define CSR_ACSMCTRL2_MASK GENMASK_32(4, 0) +#define CSR_ACSMSTARTPTR_LSB 0 +#define CSR_ACSMSTARTPTR_MASK GENMASK_32(4, 0) +/* CSR_ACSMCTRL3 */ +#define CSR_ACSMCTRL3_LSB 0 +#define CSR_ACSMCTRL3_MASK GENMASK_32(4, 0) +#define CSR_ACSMLOOPPTR_LSB 0 +#define CSR_ACSMLOOPPTR_MASK GENMASK_32(4, 0) +/* CSR_ACSMCTRL4 */ +#define CSR_ACSMCTRL4_LSB 0 +#define CSR_ACSMCTRL4_MASK GENMASK_32(4, 0) +#define CSR_ACSMENDPTR_LSB 0 +#define CSR_ACSMENDPTR_MASK GENMASK_32(4, 0) +/* CSR_ACSMCTRL5 */ +#define CSR_ACSMCTRL5_LSB 0 +#define CSR_ACSMCTRL5_MASK GENMASK_32(13, 0) +#define CSR_ACSMMXRDLAT_LSB 0 +#define CSR_ACSMMXRDLAT_MASK GENMASK_32(7, 0) +#define CSR_ACSMRCASLAT_LSB 8 +#define CSR_ACSMRCASLAT_MASK GENMASK_32(13, 8) +/* CSR_ACSMCTRL6 */ +#define CSR_ACSMCTRL6_LSB 0 +#define CSR_ACSMCTRL6_MASK GENMASK_32(10, 0) +#define CSR_ACSMWCASLAT_LSB 0 +#define CSR_ACSMWCASLAT_MASK GENMASK_32(5, 0) +#define CSR_ACSMWRRSVD_LSB 6 +#define CSR_ACSMWRRSVD_MASK GENMASK_32(7, 6) +#define CSR_ACSMWRDATLAT_LSB 8 +#define CSR_ACSMWRDATLAT_MASK GENMASK_32(10, 8) +/* CSR_ACSMCTRL7 */ +#define CSR_ACSMCTRL7_LSB 0 +#define CSR_ACSMCTRL7_MASK GENMASK_32(15, 0) +#define CSR_ACSMRASPCFG_LSB 0 +#define CSR_ACSMRASPCFG_MASK GENMASK_32(15, 0) +/* CSR_ACSMCTRL8 */ +#define CSR_ACSMCTRL8_LSB 0 +#define CSR_ACSMCTRL8_MASK GENMASK_32(15, 0) +#define CSR_ACSMRASPSEED_LSB 0 +#define CSR_ACSMRASPSEED_MASK GENMASK_32(15, 0) +/* CSR_ACSMCTRL9 */ +#define CSR_ACSMCTRL9_LSB 0 +#define CSR_ACSMCTRL9_MASK GENMASK_32(15, 0) +#define CSR_ACSMCASPCFG_LSB 0 +#define CSR_ACSMCASPCFG_MASK GENMASK_32(15, 0) +/* CSR_ACSMCTRL10 */ +#define CSR_ACSMCTRL10_LSB 0 +#define CSR_ACSMCTRL10_MASK GENMASK_32(15, 0) +#define CSR_ACSMCASPSEED_LSB 0 +#define CSR_ACSMCASPSEED_MASK GENMASK_32(15, 0) +/* CSR_ACSMCTRL11 */ +#define CSR_ACSMCTRL11_LSB 0 +#define CSR_ACSMCTRL11_MASK GENMASK_32(15, 0) +#define CSR_ACSMRASADRINC_LSB 0 +#define CSR_ACSMRASADRINC_MASK GENMASK_32(7, 0) +#define CSR_ACSMCASADRINC_LSB 8 +#define CSR_ACSMCASADRINC_MASK GENMASK_32(15, 8) +/* CSR_ACSMCTRL12 */ +#define CSR_ACSMCTRL12_LSB 0 +#define CSR_ACSMCTRL12_MASK GENMASK_32(11, 0) +#define CSR_ACSMBNKPCFG_LSB 0 +#define CSR_ACSMBNKPCFG_MASK GENMASK_32(3, 0) +#define CSR_ACSMBNKPSEED_LSB 4 +#define CSR_ACSMBNKPSEED_MASK GENMASK_32(7, 4) +#define CSR_ACSMBNKADRINC_LSB 8 +#define CSR_ACSMBNKADRINC_MASK GENMASK_32(11, 8) +/* CSR_ACSMCTRL13 */ +#define CSR_ACSMCTRL13_LSB 0 +#define CSR_ACSMCTRL13_MASK GENMASK_32(3, 0) +#define CSR_ACSMCKEENB_LSB 0 +#define CSR_ACSMCKEENB_MASK GENMASK_32(3, 0) +/* CSR_ACSMCTRL14 */ +#define CSR_ACSMCTRL14_LSB 0 +#define CSR_ACSMCTRL14_MASK GENMASK_32(3, 0) +#define CSR_ACSMRASPCFGUP_LSB 0 +#define CSR_ACSMRASPCFGUP_MASK GENMASK_32(3, 0) +/* CSR_ACSMCTRL15 */ +#define CSR_ACSMCTRL15_LSB 0 +#define CSR_ACSMCTRL15_MASK GENMASK_32(3, 0) +#define CSR_ACSMRASPSEEDUP_LSB 0 +#define CSR_ACSMRASPSEEDUP_MASK GENMASK_32(3, 0) + +/* PPGC0 register offsets */ +/* CSR_PPGCCTRL1 */ +#define CSR_PPGCCTRL1_LSB 1 +#define CSR_PPGCCTRL1_MASK GENMASK_32(4, 1) +#define CSR_HWTTXDBIEN_LSB 1 +#define CSR_HWTTXDBIEN_MASK BIT(1) +#define CSR_HWTRXDBIEN_LSB 2 +#define CSR_HWTRXDBIEN_MASK BIT(2) +#define CSR_HWTTXDMDBIVAL_LSB 3 +#define CSR_HWTTXDMDBIVAL_MASK BIT(3) +#define CSR_HWTTXDMDBISEL_LSB 4 +#define CSR_HWTTXDMDBISEL_MASK BIT(4) +/* CSR_PPGCLANE2CRCINMAP0 */ +#define CSR_PPGCLANE2CRCINMAP0_LSB 0 +#define CSR_PPGCLANE2CRCINMAP0_MASK GENMASK_32(11, 0) +#define CSR_PPGCCRCLANEMAP0_LSB 0 +#define CSR_PPGCCRCLANEMAP0_MASK GENMASK_32(2, 0) +#define CSR_PPGCCRCLANEMAP1_LSB 3 +#define CSR_PPGCCRCLANEMAP1_MASK GENMASK_32(5, 3) +#define CSR_PPGCCRCLANEMAP2_LSB 6 +#define CSR_PPGCCRCLANEMAP2_MASK GENMASK_32(8, 6) +#define CSR_PPGCCRCLANEMAP3_LSB 9 +#define CSR_PPGCCRCLANEMAP3_MASK GENMASK_32(11, 9) +/* CSR_PPGCLANE2CRCINMAP1 */ +#define CSR_PPGCLANE2CRCINMAP1_LSB 0 +#define CSR_PPGCLANE2CRCINMAP1_MASK GENMASK_32(11, 0) +#define CSR_PPGCCRCLANEMAP4_LSB 0 +#define CSR_PPGCCRCLANEMAP4_MASK GENMASK_32(2, 0) +#define CSR_PPGCCRCLANEMAP5_LSB 3 +#define CSR_PPGCCRCLANEMAP5_MASK GENMASK_32(5, 3) +#define CSR_PPGCCRCLANEMAP6_LSB 6 +#define CSR_PPGCCRCLANEMAP6_MASK GENMASK_32(8, 6) +#define CSR_PPGCCRCLANEMAP7_LSB 9 +#define CSR_PPGCCRCLANEMAP7_MASK GENMASK_32(11, 9) +/* CSR_PRBSTAPDLY0 */ +#define CSR_PRBSTAPDLY0_LSB 0 +#define CSR_PRBSTAPDLY0_MASK GENMASK_32(15, 0) +/* CSR_PRBSTAPDLY1 */ +#define CSR_PRBSTAPDLY1_LSB 0 +#define CSR_PRBSTAPDLY1_MASK GENMASK_32(15, 0) +/* CSR_PRBSTAPDLY2 */ +#define CSR_PRBSTAPDLY2_LSB 0 +#define CSR_PRBSTAPDLY2_MASK GENMASK_32(15, 0) +/* CSR_PRBSTAPDLY3 */ +#define CSR_PRBSTAPDLY3_LSB 0 +#define CSR_PRBSTAPDLY3_MASK GENMASK_32(15, 0) +/* CSR_GENPRBSBYTE0 */ +#define CSR_GENPRBSBYTE0_LSB 0 +#define CSR_GENPRBSBYTE0_MASK GENMASK_32(15, 0) +/* CSR_GENPRBSBYTE1² */ +#define CSR_GENPRBSBYTE1_LSB 0 +#define CSR_GENPRBSBYTE1_MASK GENMASK_32(15, 0) +/* CSR_GENPRBSBYTE2 */ +#define CSR_GENPRBSBYTE2_LSB 0 +#define CSR_GENPRBSBYTE2_MASK GENMASK_32(15, 0) +/* CSR_GENPRBSBYTE3 */ +#define CSR_GENPRBSBYTE3_LSB 0 +#define CSR_GENPRBSBYTE3_MASK GENMASK_32(15, 0) +/* CSR_GENPRBSBYTE4 */ +#define CSR_GENPRBSBYTE4_LSB 0 +#define CSR_GENPRBSBYTE4_MASK GENMASK_32(15, 0) +/* CSR_GENPRBSBYTE5 */ +#define CSR_GENPRBSBYTE5_LSB 0 +#define CSR_GENPRBSBYTE5_MASK GENMASK_32(15, 0) +/* CSR_GENPRBSBYTE6 */ +#define CSR_GENPRBSBYTE6_LSB 0 +#define CSR_GENPRBSBYTE6_MASK GENMASK_32(15, 0) +/* CSR_GENPRBSBYTE7 */ +#define CSR_GENPRBSBYTE7_LSB 0 +#define CSR_GENPRBSBYTE7_MASK GENMASK_32(15, 0) +/* CSR_GENPRBSBYTE8 */ +#define CSR_GENPRBSBYTE8_LSB 0 +#define CSR_GENPRBSBYTE8_MASK GENMASK_32(15, 0) +/* CSR_GENPRBSBYTE9 */ +#define CSR_GENPRBSBYTE9_LSB 0 +#define CSR_GENPRBSBYTE9_MASK GENMASK_32(15, 0) +/* CSR_GENPRBSBYTE10 */ +#define CSR_GENPRBSBYTE10_LSB 0 +#define CSR_GENPRBSBYTE10_MASK GENMASK_32(15, 0) +/* CSR_GENPRBSBYTE11 */ +#define CSR_GENPRBSBYTE11_LSB 0 +#define CSR_GENPRBSBYTE11_MASK GENMASK_32(15, 0) +/* CSR_GENPRBSBYTE12 */ +#define CSR_GENPRBSBYTE12_LSB 0 +#define CSR_GENPRBSBYTE12_MASK GENMASK_32(15, 0) +/* CSR_GENPRBSBYTE13 */ +#define CSR_GENPRBSBYTE13_LSB 0 +#define CSR_GENPRBSBYTE13_MASK GENMASK_32(15, 0) +/* CSR_GENPRBSBYTE14 */ +#define CSR_GENPRBSBYTE14_LSB 0 +#define CSR_GENPRBSBYTE14_MASK GENMASK_32(15, 0) +/* CSR_GENPRBSBYTE15 */ +#define CSR_GENPRBSBYTE15_LSB 0 +#define CSR_GENPRBSBYTE15_MASK GENMASK_32(15, 0) +/* CSR_PRBSGENCTL */ +#define CSR_PRBSGENCTL_LSB 0 +#define CSR_PRBSGENCTL_MASK GENMASK_32(6, 0) +#define CSR_PPGCMODE_LSB 0 +#define CSR_PPGCMODE_MASK BIT(0) +#define CSR_PPGCDMMODE_LSB 1 +#define CSR_PPGCDMMODE_MASK BIT(1) +#define CSR_PPGCLDFFMODE_LSB 2 +#define CSR_PPGCLDFFMODE_MASK BIT(2) +#define CSR_PPGCSEL23BPRBS_LSB 3 +#define CSR_PPGCSEL23BPRBS_MASK BIT(3) +#define CSR_PPGCPATADV_LSB 4 +#define CSR_PPGCPATADV_MASK GENMASK_32(5, 4) +#define CSR_PPGCENBPATSTRESSMODE_LSB 6 +#define CSR_PPGCENBPATSTRESSMODE_MASK BIT(6) +/* CSR_PRBSGENSTATELO */ +#define CSR_PRBSGENSTATELO_LSB 0 +#define CSR_PRBSGENSTATELO_MASK GENMASK_32(15, 0) +/* CSR_PRBSGENSTATEHI */ +#define CSR_PRBSGENSTATEHI_LSB 0 +#define CSR_PRBSGENSTATEHI_MASK GENMASK_32(6, 0) +/* CSR_PRBSCHKSTATELO */ +#define CSR_PRBSCHKSTATELO_LSB 0 +#define CSR_PRBSCHKSTATELO_MASK GENMASK_32(15, 0) +/* CSR_PRBSCHKSTATEHI */ +#define CSR_PRBSCHKSTATEHI_LSB 0 +#define CSR_PRBSCHKSTATEHI_MASK GENMASK_32(6, 0) +/* CSR_PRBSGENCTL1 */ +#define CSR_PRBSGENCTL1_LSB 0 +#define CSR_PRBSGENCTL1_MASK GENMASK_32(8, 0) +#define CSR_PPGCMODELANE_LSB 0 +#define CSR_PPGCMODELANE_MASK GENMASK_32(8, 0) +/* CSR_PRBSGENCTL2 */ +#define CSR_PRBSGENCTL2_LSB 0 +#define CSR_PRBSGENCTL2_MASK GENMASK_32(15, 0) +#define CSR_PPGCMSKPERIODLIM_LSB 0 +#define CSR_PPGCMSKPERIODLIM_MASK GENMASK_32(15, 0) + +/* INITENG0 register offsets */ +/* CSR_PRESEQUENCEREG0B0S0 */ +#define CSR_PRESEQUENCEREG0B0S0_LSB 0 +#define CSR_PRESEQUENCEREG0B0S0_MASK GENMASK_32(15, 0) +/* CSR_PRESEQUENCEREG0B0S1 */ +#define CSR_PRESEQUENCEREG0B0S1_LSB 0 +#define CSR_PRESEQUENCEREG0B0S1_MASK GENMASK_32(15, 0) +/* CSR_PRESEQUENCEREG0B0S2 */ +#define CSR_PRESEQUENCEREG0B0S2_LSB 0 +#define CSR_PRESEQUENCEREG0B0S2_MASK GENMASK_32(8, 0) +/* CSR_PRESEQUENCEREG0B1S0 */ +#define CSR_PRESEQUENCEREG0B1S0_LSB 0 +#define CSR_PRESEQUENCEREG0B1S0_MASK GENMASK_32(15, 0) +/* CSR_PRESEQUENCEREG0B1S1 */ +#define CSR_PRESEQUENCEREG0B1S1_LSB 0 +#define CSR_PRESEQUENCEREG0B1S1_MASK GENMASK_32(15, 0) +/* CSR_PRESEQUENCEREG0B1S2 */ +#define CSR_PRESEQUENCEREG0B1S2_LSB 0 +#define CSR_PRESEQUENCEREG0B1S2_MASK GENMASK_32(8, 0) +/* CSR_POSTSEQUENCEREG0B0S0 */ +#define CSR_POSTSEQUENCEREG0B0S0_LSB 0 +#define CSR_POSTSEQUENCEREG0B0S0_MASK GENMASK_32(15, 0) +/* CSR_POSTSEQUENCEREG0B0S1 */ +#define CSR_POSTSEQUENCEREG0B0S1_LSB 0 +#define CSR_POSTSEQUENCEREG0B0S1_MASK GENMASK_32(15, 0) +/* CSR_POSTSEQUENCEREG0B0S2 */ +#define CSR_POSTSEQUENCEREG0B0S2_LSB 0 +#define CSR_POSTSEQUENCEREG0B0S2_MASK GENMASK_32(8, 0) +/* CSR_POSTSEQUENCEREG0B1S0 */ +#define CSR_POSTSEQUENCEREG0B1S0_LSB 0 +#define CSR_POSTSEQUENCEREG0B1S0_MASK GENMASK_32(15, 0) +/* CSR_POSTSEQUENCEREG0B1S1 */ +#define CSR_POSTSEQUENCEREG0B1S1_LSB 0 +#define CSR_POSTSEQUENCEREG0B1S1_MASK GENMASK_32(15, 0) +/* CSR_POSTSEQUENCEREG0B1S2 */ +#define CSR_POSTSEQUENCEREG0B1S2_LSB 0 +#define CSR_POSTSEQUENCEREG0B1S2_MASK GENMASK_32(8, 0) +/* CSR_SEQ0BDISABLEFLAG0 */ +#define CSR_SEQ0BDISABLEFLAG0_LSB 0 +#define CSR_SEQ0BDISABLEFLAG0_MASK GENMASK_32(15, 0) +/* CSR_SEQ0BDISABLEFLAG1 */ +#define CSR_SEQ0BDISABLEFLAG1_LSB 0 +#define CSR_SEQ0BDISABLEFLAG1_MASK GENMASK_32(15, 0) +/* CSR_SEQ0BDISABLEFLAG2 */ +#define CSR_SEQ0BDISABLEFLAG2_LSB 0 +#define CSR_SEQ0BDISABLEFLAG2_MASK GENMASK_32(15, 0) +/* CSR_SEQ0BDISABLEFLAG3 */ +#define CSR_SEQ0BDISABLEFLAG3_LSB 0 +#define CSR_SEQ0BDISABLEFLAG3_MASK GENMASK_32(15, 0) +/* CSR_SEQ0BDISABLEFLAG4 */ +#define CSR_SEQ0BDISABLEFLAG4_LSB 0 +#define CSR_SEQ0BDISABLEFLAG4_MASK GENMASK_32(15, 0) +/* CSR_SEQ0BDISABLEFLAG5 */ +#define CSR_SEQ0BDISABLEFLAG5_LSB 0 +#define CSR_SEQ0BDISABLEFLAG5_MASK GENMASK_32(15, 0) +/* CSR_SEQ0BDISABLEFLAG6 */ +#define CSR_SEQ0BDISABLEFLAG6_LSB 0 +#define CSR_SEQ0BDISABLEFLAG6_MASK GENMASK_32(15, 0) +/* CSR_SEQ0BDISABLEFLAG7 */ +#define CSR_SEQ0BDISABLEFLAG7_LSB 0 +#define CSR_SEQ0BDISABLEFLAG7_MASK GENMASK_32(15, 0) +/* CSR_STARTVECTOR0B0 */ +#define CSR_STARTVECTOR0B0_LSB 0 +#define CSR_STARTVECTOR0B0_MASK GENMASK_32(6, 0) +#define CSR_SEQ0BSTARTVEC0_LSB 0 +#define CSR_SEQ0BSTARTVEC0_MASK GENMASK_32(6, 0) +/* CSR_STARTVECTOR0B1 */ +#define CSR_STARTVECTOR0B1_LSB 0 +#define CSR_STARTVECTOR0B1_MASK GENMASK_32(6, 0) +#define CSR_SEQ0BSTARTVEC1_LSB 0 +#define CSR_SEQ0BSTARTVEC1_MASK GENMASK_32(6, 0) +/* CSR_STARTVECTOR0B2 */ +#define CSR_STARTVECTOR0B2_LSB 0 +#define CSR_STARTVECTOR0B2_MASK GENMASK_32(6, 0) +#define CSR_SEQ0BSTARTVEC2_LSB 0 +#define CSR_SEQ0BSTARTVEC2_MASK GENMASK_32(6, 0) +/* CSR_STARTVECTOR0B3 */ +#define CSR_STARTVECTOR0B3_LSB 0 +#define CSR_STARTVECTOR0B3_MASK GENMASK_32(6, 0) +#define CSR_SEQ0BSTARTVEC3_LSB 0 +#define CSR_SEQ0BSTARTVEC3_MASK GENMASK_32(6, 0) +/* CSR_STARTVECTOR0B4 */ +#define CSR_STARTVECTOR0B4_LSB 0 +#define CSR_STARTVECTOR0B4_MASK GENMASK_32(6, 0) +#define CSR_SEQ0BSTARTVEC4_LSB 0 +#define CSR_SEQ0BSTARTVEC4_MASK GENMASK_32(6, 0) +/* CSR_STARTVECTOR0B5 */ +#define CSR_STARTVECTOR0B5_LSB 0 +#define CSR_STARTVECTOR0B5_MASK GENMASK_32(6, 0) +#define CSR_SEQ0BSTARTVEC5_LSB 0 +#define CSR_SEQ0BSTARTVEC5_MASK GENMASK_32(6, 0) +/* CSR_STARTVECTOR0B6 */ +#define CSR_STARTVECTOR0B6_LSB 0 +#define CSR_STARTVECTOR0B6_MASK GENMASK_32(6, 0) +#define CSR_SEQ0BSTARTVEC6_LSB 0 +#define CSR_SEQ0BSTARTVEC6_MASK GENMASK_32(6, 0) +/* CSR_STARTVECTOR0B7 */ +#define CSR_STARTVECTOR0B7_LSB 0 +#define CSR_STARTVECTOR0B7_MASK GENMASK_32(6, 0) +#define CSR_SEQ0BSTARTVEC7_LSB 0 +#define CSR_SEQ0BSTARTVEC7_MASK GENMASK_32(6, 0) +/* CSR_STARTVECTOR0B8 */ +#define CSR_STARTVECTOR0B8_LSB 0 +#define CSR_STARTVECTOR0B8_MASK GENMASK_32(6, 0) +#define CSR_SEQ0BSTARTVEC8_LSB 0 +#define CSR_SEQ0BSTARTVEC8_MASK GENMASK_32(6, 0) +/* CSR_STARTVECTOR0B9 */ +#define CSR_STARTVECTOR0B9_LSB 0 +#define CSR_STARTVECTOR0B9_MASK GENMASK_32(6, 0) +#define CSR_SEQ0BSTARTVEC9_LSB 0 +#define CSR_SEQ0BSTARTVEC9_MASK GENMASK_32(6, 0) +/* CSR_STARTVECTOR0B10 */ +#define CSR_STARTVECTOR0B10_LSB 0 +#define CSR_STARTVECTOR0B10_MASK GENMASK_32(6, 0) +#define CSR_SEQ0BSTARTVEC10_LSB 0 +#define CSR_SEQ0BSTARTVEC10_MASK GENMASK_32(6, 0) +/* CSR_STARTVECTOR0B11 */ +#define CSR_STARTVECTOR0B11_LSB 0 +#define CSR_STARTVECTOR0B11_MASK GENMASK_32(6, 0) +#define CSR_SEQ0BSTARTVEC11_LSB 0 +#define CSR_SEQ0BSTARTVEC11_MASK GENMASK_32(6, 0) +/* CSR_STARTVECTOR0B12 */ +#define CSR_STARTVECTOR0B12_LSB 0 +#define CSR_STARTVECTOR0B12_MASK GENMASK_32(6, 0) +#define CSR_SEQ0BSTARTVEC12_LSB 0 +#define CSR_SEQ0BSTARTVEC12_MASK GENMASK_32(6, 0) +/* CSR_STARTVECTOR0B13 */ +#define CSR_STARTVECTOR0B13_LSB 0 +#define CSR_STARTVECTOR0B13_MASK GENMASK_32(6, 0) +#define CSR_SEQ0BSTARTVEC13_LSB 0 +#define CSR_SEQ0BSTARTVEC13_MASK GENMASK_32(6, 0) +/* CSR_STARTVECTOR0B14 */ +#define CSR_STARTVECTOR0B14_LSB 0 +#define CSR_STARTVECTOR0B14_MASK GENMASK_32(6, 0) +#define CSR_SEQ0BSTARTVEC14_LSB 0 +#define CSR_SEQ0BSTARTVEC14_MASK GENMASK_32(6, 0) +/* CSR_STARTVECTOR0B15 */ +#define CSR_STARTVECTOR0B15_LSB 0 +#define CSR_STARTVECTOR0B15_MASK GENMASK_32(6, 0) +#define CSR_SEQ0BSTARTVEC15_LSB 0 +#define CSR_SEQ0BSTARTVEC15_MASK GENMASK_32(6, 0) +/* CSR_SEQ0BWAITCONDSEL */ +#define CSR_SEQ0BWAITCONDSEL_LSB 0 +#define CSR_SEQ0BWAITCONDSEL_MASK GENMASK_32(2, 0) +/* CSR_PHYINLP3 */ +#define CSR_PHYINLP3_LSB 0 +#define CSR_PHYINLP3_MASK BIT(0) +/* CSR_SEQUENCEREG0B0S0 */ +#define CSR_SEQUENCEREG0B0S0_LSB 0 +#define CSR_SEQUENCEREG0B0S0_MASK GENMASK_32(15, 0) +/* CSR_SEQUENCEREG0B0S1 */ +#define CSR_SEQUENCEREG0B0S1_LSB 0 +#define CSR_SEQUENCEREG0B0S1_MASK GENMASK_32(15, 0) +/* CSR_SEQUENCEREG0B0S2 */ +#define CSR_SEQUENCEREG0B0S2_LSB 0 +#define CSR_SEQUENCEREG0B0S2_MASK GENMASK_32(8, 0) +/* CSR_SEQUENCEREG0B1S0 */ +#define CSR_SEQUENCEREG0B1S0_LSB 0 +#define CSR_SEQUENCEREG0B1S0_MASK GENMASK_32(15, 0) +/* CSR_SEQUENCEREG0B1S1 */ +#define CSR_SEQUENCEREG0B1S1_LSB 0 +#define CSR_SEQUENCEREG0B1S1_MASK GENMASK_32(15, 0) +/* CSR_SEQUENCEREG0B1S2 */ +#define CSR_SEQUENCEREG0B1S2_LSB 0 +#define CSR_SEQUENCEREG0B1S2_MASK GENMASK_32(8, 0) +/* CSR_SEQUENCEREG0B2S0 */ +#define CSR_SEQUENCEREG0B2S0_LSB 0 +#define CSR_SEQUENCEREG0B2S0_MASK GENMASK_32(15, 0) +/* CSR_SEQUENCEREG0B2S1 */ +#define CSR_SEQUENCEREG0B2S1_LSB 0 +#define CSR_SEQUENCEREG0B2S1_MASK GENMASK_32(15, 0) +/* CSR_SEQUENCEREG0B2S2 */ +#define CSR_SEQUENCEREG0B2S2_LSB 0 +#define CSR_SEQUENCEREG0B2S2_MASK GENMASK_32(8, 0) +/* CSR_SEQUENCEREG0B3S0 */ +#define CSR_SEQUENCEREG0B3S0_LSB 0 +#define CSR_SEQUENCEREG0B3S0_MASK GENMASK_32(15, 0) +/* CSR_SEQUENCEREG0B3S1 */ +#define CSR_SEQUENCEREG0B3S1_LSB 0 +#define CSR_SEQUENCEREG0B3S1_MASK GENMASK_32(15, 0) +/* CSR_SEQUENCEREG0B3S2 */ +#define CSR_SEQUENCEREG0B3S2_LSB 0 +#define CSR_SEQUENCEREG0B3S2_MASK GENMASK_32(8, 0) +/* CSR_SEQUENCEREG0B4S0 */ +#define CSR_SEQUENCEREG0B4S0_LSB 0 +#define CSR_SEQUENCEREG0B4S0_MASK GENMASK_32(15, 0) +/* CSR_SEQUENCEREG0B4S1 */ +#define CSR_SEQUENCEREG0B4S1_LSB 0 +#define CSR_SEQUENCEREG0B4S1_MASK GENMASK_32(15, 0) +/* CSR_SEQUENCEREG0B4S2 */ +#define CSR_SEQUENCEREG0B4S2_LSB 0 +#define CSR_SEQUENCEREG0B4S2_MASK GENMASK_32(8, 0) +/* CSR_SEQUENCEREG0B5S0 */ +#define CSR_SEQUENCEREG0B5S0_LSB 0 +#define CSR_SEQUENCEREG0B5S0_MASK GENMASK_32(15, 0) +/* CSR_SEQUENCEREG0B5S1 */ +#define CSR_SEQUENCEREG0B5S1_LSB 0 +#define CSR_SEQUENCEREG0B5S1_MASK GENMASK_32(15, 0) +/* CSR_SEQUENCEREG0B5S2 */ +#define CSR_SEQUENCEREG0B5S2_LSB 0 +#define CSR_SEQUENCEREG0B5S2_MASK GENMASK_32(8, 0) +/* CSR_SEQUENCEREG0B6S0 */ +#define CSR_SEQUENCEREG0B6S0_LSB 0 +#define CSR_SEQUENCEREG0B6S0_MASK GENMASK_32(15, 0) +/* CSR_SEQUENCEREG0B6S1 */ +#define CSR_SEQUENCEREG0B6S1_LSB 0 +#define CSR_SEQUENCEREG0B6S1_MASK GENMASK_32(15, 0) +/* CSR_SEQUENCEREG0B6S2 */ +#define CSR_SEQUENCEREG0B6S2_LSB 0 +#define CSR_SEQUENCEREG0B6S2_MASK GENMASK_32(8, 0) +/* CSR_SEQUENCEREG0B7S0 */ +#define CSR_SEQUENCEREG0B7S0_LSB 0 +#define CSR_SEQUENCEREG0B7S0_MASK GENMASK_32(15, 0) +/* CSR_SEQUENCEREG0B7S1 */ +#define CSR_SEQUENCEREG0B7S1_LSB 0 +#define CSR_SEQUENCEREG0B7S1_MASK GENMASK_32(15, 0) +/* CSR_SEQUENCEREG0B7S2 */ +#define CSR_SEQUENCEREG0B7S2_LSB 0 +#define CSR_SEQUENCEREG0B7S2_MASK GENMASK_32(8, 0) +/* CSR_SEQUENCEREG0B8S0 */ +#define CSR_SEQUENCEREG0B8S0_LSB 0 +#define CSR_SEQUENCEREG0B8S0_MASK GENMASK_32(15, 0) +/* CSR_SEQUENCEREG0B8S1 */ +#define CSR_SEQUENCEREG0B8S1_LSB 0 +#define CSR_SEQUENCEREG0B8S1_MASK GENMASK_32(15, 0) +/* CSR_SEQUENCEREG0B8S2 */ +#define CSR_SEQUENCEREG0B8S2_LSB 0 +#define CSR_SEQUENCEREG0B8S2_MASK GENMASK_32(8, 0) +/* CSR_SEQUENCEREG0B9S0 */ +#define CSR_SEQUENCEREG0B9S0_LSB 0 +#define CSR_SEQUENCEREG0B9S0_MASK GENMASK_32(15, 0) +/* CSR_SEQUENCEREG0B9S1 */ +#define CSR_SEQUENCEREG0B9S1_LSB 0 +#define CSR_SEQUENCEREG0B9S1_MASK GENMASK_32(15, 0) +/* CSR_SEQUENCEREG0B9S2 */ +#define CSR_SEQUENCEREG0B9S2_LSB 0 +#define CSR_SEQUENCEREG0B9S2_MASK GENMASK_32(8, 0) +/* CSR_SEQUENCEREG0B10S0 */ +#define CSR_SEQUENCEREG0B10S0_LSB 0 +#define CSR_SEQUENCEREG0B10S0_MASK GENMASK_32(15, 0) +/* CSR_SEQUENCEREG0B10S1 */ +#define CSR_SEQUENCEREG0B10S1_LSB 0 +#define CSR_SEQUENCEREG0B10S1_MASK GENMASK_32(15, 0) +/* CSR_SEQUENCEREG0B10S2 */ +#define CSR_SEQUENCEREG0B10S2_LSB 0 +#define CSR_SEQUENCEREG0B10S2_MASK GENMASK_32(8, 0) +/* CSR_SEQUENCEREG0B11S0 */ +#define CSR_SEQUENCEREG0B11S0_LSB 0 +#define CSR_SEQUENCEREG0B11S0_MASK GENMASK_32(15, 0) +/* CSR_SEQUENCEREG0B11S1 */ +#define CSR_SEQUENCEREG0B11S1_LSB 0 +#define CSR_SEQUENCEREG0B11S1_MASK GENMASK_32(15, 0) +/* CSR_SEQUENCEREG0B11S2 */ +#define CSR_SEQUENCEREG0B11S2_LSB 0 +#define CSR_SEQUENCEREG0B11S2_MASK GENMASK_32(8, 0) +/* CSR_SEQUENCEREG0B12S0 */ +#define CSR_SEQUENCEREG0B12S0_LSB 0 +#define CSR_SEQUENCEREG0B12S0_MASK GENMASK_32(15, 0) +/* CSR_SEQUENCEREG0B12S1 */ +#define CSR_SEQUENCEREG0B12S1_LSB 0 +#define CSR_SEQUENCEREG0B12S1_MASK GENMASK_32(15, 0) +/* CSR_SEQUENCEREG0B12S2 */ +#define CSR_SEQUENCEREG0B12S2_LSB 0 +#define CSR_SEQUENCEREG0B12S2_MASK GENMASK_32(8, 0) +/* CSR_SEQUENCEREG0B13S0 */ +#define CSR_SEQUENCEREG0B13S0_LSB 0 +#define CSR_SEQUENCEREG0B13S0_MASK GENMASK_32(15, 0) +/* CSR_SEQUENCEREG0B13S1 */ +#define CSR_SEQUENCEREG0B13S1_LSB 0 +#define CSR_SEQUENCEREG0B13S1_MASK GENMASK_32(15, 0) +/* CSR_SEQUENCEREG0B13S2 */ +#define CSR_SEQUENCEREG0B13S2_LSB 0 +#define CSR_SEQUENCEREG0B13S2_MASK GENMASK_32(8, 0) +/* CSR_SEQUENCEREG0B14S0 */ +#define CSR_SEQUENCEREG0B14S0_LSB 0 +#define CSR_SEQUENCEREG0B14S0_MASK GENMASK_32(15, 0) +/* CSR_SEQUENCEREG0B14S1 */ +#define CSR_SEQUENCEREG0B14S1_LSB 0 +#define CSR_SEQUENCEREG0B14S1_MASK GENMASK_32(15, 0) +/* CSR_SEQUENCEREG0B14S2 */ +#define CSR_SEQUENCEREG0B14S2_LSB 0 +#define CSR_SEQUENCEREG0B14S2_MASK GENMASK_32(8, 0) +/* CSR_SEQUENCEREG0B15S0 */ +#define CSR_SEQUENCEREG0B15S0_LSB 0 +#define CSR_SEQUENCEREG0B15S0_MASK GENMASK_32(15, 0) +/* CSR_SEQUENCEREG0B15S1 */ +#define CSR_SEQUENCEREG0B15S1_LSB 0 +#define CSR_SEQUENCEREG0B15S1_MASK GENMASK_32(15, 0) +/* CSR_SEQUENCEREG0B15S2 */ +#define CSR_SEQUENCEREG0B15S2_LSB 0 +#define CSR_SEQUENCEREG0B15S2_MASK GENMASK_32(8, 0) +/* CSR_SEQUENCEREG0B16S0 */ +#define CSR_SEQUENCEREG0B16S0_LSB 0 +#define CSR_SEQUENCEREG0B16S0_MASK GENMASK_32(15, 0) +/* CSR_SEQUENCEREG0B16S1 */ +#define CSR_SEQUENCEREG0B16S1_LSB 0 +#define CSR_SEQUENCEREG0B16S1_MASK GENMASK_32(15, 0) +/* CSR_SEQUENCEREG0B16S2 */ +#define CSR_SEQUENCEREG0B16S2_LSB 0 +#define CSR_SEQUENCEREG0B16S2_MASK GENMASK_32(8, 0) +/* CSR_SEQUENCEREG0B17S0 */ +#define CSR_SEQUENCEREG0B17S0_LSB 0 +#define CSR_SEQUENCEREG0B17S0_MASK GENMASK_32(15, 0) +/* CSR_SEQUENCEREG0B17S1 */ +#define CSR_SEQUENCEREG0B17S1_LSB 0 +#define CSR_SEQUENCEREG0B17S1_MASK GENMASK_32(15, 0) +/* CSR_SEQUENCEREG0B17S2 */ +#define CSR_SEQUENCEREG0B17S2_LSB 0 +#define CSR_SEQUENCEREG0B17S2_MASK GENMASK_32(8, 0) +/* CSR_SEQUENCEREG0B18S0 */ +#define CSR_SEQUENCEREG0B18S0_LSB 0 +#define CSR_SEQUENCEREG0B18S0_MASK GENMASK_32(15, 0) +/* CSR_SEQUENCEREG0B18S1 */ +#define CSR_SEQUENCEREG0B18S1_LSB 0 +#define CSR_SEQUENCEREG0B18S1_MASK GENMASK_32(15, 0) +/* CSR_SEQUENCEREG0B18S2 */ +#define CSR_SEQUENCEREG0B18S2_LSB 0 +#define CSR_SEQUENCEREG0B18S2_MASK GENMASK_32(8, 0) +/* CSR_SEQUENCEREG0B19S0 */ +#define CSR_SEQUENCEREG0B19S0_LSB 0 +#define CSR_SEQUENCEREG0B19S0_MASK GENMASK_32(15, 0) +/* CSR_SEQUENCEREG0B19S1 */ +#define CSR_SEQUENCEREG0B19S1_LSB 0 +#define CSR_SEQUENCEREG0B19S1_MASK GENMASK_32(15, 0) +/* CSR_SEQUENCEREG0B19S2 */ +#define CSR_SEQUENCEREG0B19S2_LSB 0 +#define CSR_SEQUENCEREG0B19S2_MASK GENMASK_32(8, 0) +/* CSR_SEQUENCEREG0B20S0 */ +#define CSR_SEQUENCEREG0B20S0_LSB 0 +#define CSR_SEQUENCEREG0B20S0_MASK GENMASK_32(15, 0) +/* CSR_SEQUENCEREG0B20S1 */ +#define CSR_SEQUENCEREG0B20S1_LSB 0 +#define CSR_SEQUENCEREG0B20S1_MASK GENMASK_32(15, 0) +/* CSR_SEQUENCEREG0B20S2 */ +#define CSR_SEQUENCEREG0B20S2_LSB 0 +#define CSR_SEQUENCEREG0B20S2_MASK GENMASK_32(8, 0) +/* CSR_SEQUENCEREG0B21S0 */ +#define CSR_SEQUENCEREG0B21S0_LSB 0 +#define CSR_SEQUENCEREG0B21S0_MASK GENMASK_32(15, 0) +/* CSR_SEQUENCEREG0B21S1 */ +#define CSR_SEQUENCEREG0B21S1_LSB 0 +#define CSR_SEQUENCEREG0B21S1_MASK GENMASK_32(15, 0) +/* CSR_SEQUENCEREG0B21S2 */ +#define CSR_SEQUENCEREG0B21S2_LSB 0 +#define CSR_SEQUENCEREG0B21S2_MASK GENMASK_32(8, 0) +/* CSR_SEQUENCEREG0B22S0 */ +#define CSR_SEQUENCEREG0B22S0_LSB 0 +#define CSR_SEQUENCEREG0B22S0_MASK GENMASK_32(15, 0) +/* CSR_SEQUENCEREG0B22S1 */ +#define CSR_SEQUENCEREG0B22S1_LSB 0 +#define CSR_SEQUENCEREG0B22S1_MASK GENMASK_32(15, 0) +/* CSR_SEQUENCEREG0B22S2 */ +#define CSR_SEQUENCEREG0B22S2_LSB 0 +#define CSR_SEQUENCEREG0B22S2_MASK GENMASK_32(8, 0) +/* CSR_SEQUENCEREG0B23S0 */ +#define CSR_SEQUENCEREG0B23S0_LSB 0 +#define CSR_SEQUENCEREG0B23S0_MASK GENMASK_32(15, 0) +/* CSR_SEQUENCEREG0B23S1 */ +#define CSR_SEQUENCEREG0B23S1_LSB 0 +#define CSR_SEQUENCEREG0B23S1_MASK GENMASK_32(15, 0) +/* CSR_SEQUENCEREG0B23S2 */ +#define CSR_SEQUENCEREG0B23S2_LSB 0 +#define CSR_SEQUENCEREG0B23S2_MASK GENMASK_32(8, 0) +/* CSR_SEQUENCEREG0B24S0 */ +#define CSR_SEQUENCEREG0B24S0_LSB 0 +#define CSR_SEQUENCEREG0B24S0_MASK GENMASK_32(15, 0) +/* CSR_SEQUENCEREG0B24S1 */ +#define CSR_SEQUENCEREG0B24S1_LSB 0 +#define CSR_SEQUENCEREG0B24S1_MASK GENMASK_32(15, 0) +/* CSR_SEQUENCEREG0B24S2 */ +#define CSR_SEQUENCEREG0B24S2_LSB 0 +#define CSR_SEQUENCEREG0B24S2_MASK GENMASK_32(8, 0) +/* CSR_SEQUENCEREG0B25S0 */ +#define CSR_SEQUENCEREG0B25S0_LSB 0 +#define CSR_SEQUENCEREG0B25S0_MASK GENMASK_32(15, 0) +/* CSR_SEQUENCEREG0B25S1 */ +#define CSR_SEQUENCEREG0B25S1_LSB 0 +#define CSR_SEQUENCEREG0B25S1_MASK GENMASK_32(15, 0) +/* CSR_SEQUENCEREG0B25S2 */ +#define CSR_SEQUENCEREG0B25S2_LSB 0 +#define CSR_SEQUENCEREG0B25S2_MASK GENMASK_32(8, 0) +/* CSR_SEQUENCEREG0B26S0 */ +#define CSR_SEQUENCEREG0B26S0_LSB 0 +#define CSR_SEQUENCEREG0B26S0_MASK GENMASK_32(15, 0) +/* CSR_SEQUENCEREG0B26S1 */ +#define CSR_SEQUENCEREG0B26S1_LSB 0 +#define CSR_SEQUENCEREG0B26S1_MASK GENMASK_32(15, 0) +/* CSR_SEQUENCEREG0B26S2 */ +#define CSR_SEQUENCEREG0B26S2_LSB 0 +#define CSR_SEQUENCEREG0B26S2_MASK GENMASK_32(8, 0) +/* CSR_SEQUENCEREG0B27S0 */ +#define CSR_SEQUENCEREG0B27S0_LSB 0 +#define CSR_SEQUENCEREG0B27S0_MASK GENMASK_32(15, 0) +/* CSR_SEQUENCEREG0B27S1 */ +#define CSR_SEQUENCEREG0B27S1_LSB 0 +#define CSR_SEQUENCEREG0B27S1_MASK GENMASK_32(15, 0) +/* CSR_SEQUENCEREG0B27S2 */ +#define CSR_SEQUENCEREG0B27S2_LSB 0 +#define CSR_SEQUENCEREG0B27S2_MASK GENMASK_32(8, 0) +/* CSR_SEQUENCEREG0B28S0 */ +#define CSR_SEQUENCEREG0B28S0_LSB 0 +#define CSR_SEQUENCEREG0B28S0_MASK GENMASK_32(15, 0) +/* CSR_SEQUENCEREG0B28S1 */ +#define CSR_SEQUENCEREG0B28S1_LSB 0 +#define CSR_SEQUENCEREG0B28S1_MASK GENMASK_32(15, 0) +/* CSR_SEQUENCEREG0B28S2 */ +#define CSR_SEQUENCEREG0B28S2_LSB 0 +#define CSR_SEQUENCEREG0B28S2_MASK GENMASK_32(8, 0) +/* CSR_SEQUENCEREG0B29S0 */ +#define CSR_SEQUENCEREG0B29S0_LSB 0 +#define CSR_SEQUENCEREG0B29S0_MASK GENMASK_32(15, 0) +/* CSR_SEQUENCEREG0B29S1 */ +#define CSR_SEQUENCEREG0B29S1_LSB 0 +#define CSR_SEQUENCEREG0B29S1_MASK GENMASK_32(15, 0) +/* CSR_SEQUENCEREG0B29S2 */ +#define CSR_SEQUENCEREG0B29S2_LSB 0 +#define CSR_SEQUENCEREG0B29S2_MASK GENMASK_32(8, 0) +/* CSR_SEQUENCEREG0B30S0 */ +#define CSR_SEQUENCEREG0B30S0_LSB 0 +#define CSR_SEQUENCEREG0B30S0_MASK GENMASK_32(15, 0) +/* CSR_SEQUENCEREG0B30S1 */ +#define CSR_SEQUENCEREG0B30S1_LSB 0 +#define CSR_SEQUENCEREG0B30S1_MASK GENMASK_32(15, 0) +/* CSR_SEQUENCEREG0B30S2 */ +#define CSR_SEQUENCEREG0B30S2_LSB 0 +#define CSR_SEQUENCEREG0B30S2_MASK GENMASK_32(8, 0) +/* CSR_SEQUENCEREG0B31S0 */ +#define CSR_SEQUENCEREG0B31S0_LSB 0 +#define CSR_SEQUENCEREG0B31S0_MASK GENMASK_32(15, 0) +/* CSR_SEQUENCEREG0B31S1 */ +#define CSR_SEQUENCEREG0B31S1_LSB 0 +#define CSR_SEQUENCEREG0B31S1_MASK GENMASK_32(15, 0) +/* CSR_SEQUENCEREG0B31S2 */ +#define CSR_SEQUENCEREG0B31S2_LSB 0 +#define CSR_SEQUENCEREG0B31S2_MASK GENMASK_32(8, 0) +/* CSR_SEQUENCEREG0B32S0 */ +#define CSR_SEQUENCEREG0B32S0_LSB 0 +#define CSR_SEQUENCEREG0B32S0_MASK GENMASK_32(15, 0) +/* CSR_SEQUENCEREG0B32S1 */ +#define CSR_SEQUENCEREG0B32S1_LSB 0 +#define CSR_SEQUENCEREG0B32S1_MASK GENMASK_32(15, 0) +/* CSR_SEQUENCEREG0B32S2 */ +#define CSR_SEQUENCEREG0B32S2_LSB 0 +#define CSR_SEQUENCEREG0B32S2_MASK GENMASK_32(8, 0) +/* CSR_SEQUENCEREG0B33S0 */ +#define CSR_SEQUENCEREG0B33S0_LSB 0 +#define CSR_SEQUENCEREG0B33S0_MASK GENMASK_32(15, 0) +/* CSR_SEQUENCEREG0B33S1 */ +#define CSR_SEQUENCEREG0B33S1_LSB 0 +#define CSR_SEQUENCEREG0B33S1_MASK GENMASK_32(15, 0) +/* CSR_SEQUENCEREG0B33S2 */ +#define CSR_SEQUENCEREG0B33S2_LSB 0 +#define CSR_SEQUENCEREG0B33S2_MASK GENMASK_32(8, 0) +/* CSR_SEQUENCEREG0B34S0 */ +#define CSR_SEQUENCEREG0B34S0_LSB 0 +#define CSR_SEQUENCEREG0B34S0_MASK GENMASK_32(15, 0) +/* CSR_SEQUENCEREG0B34S1 */ +#define CSR_SEQUENCEREG0B34S1_LSB 0 +#define CSR_SEQUENCEREG0B34S1_MASK GENMASK_32(15, 0) +/* CSR_SEQUENCEREG0B34S2 */ +#define CSR_SEQUENCEREG0B34S2_LSB 0 +#define CSR_SEQUENCEREG0B34S2_MASK GENMASK_32(8, 0) +/* CSR_SEQUENCEREG0B35S0 */ +#define CSR_SEQUENCEREG0B35S0_LSB 0 +#define CSR_SEQUENCEREG0B35S0_MASK GENMASK_32(15, 0) +/* CSR_SEQUENCEREG0B35S1 */ +#define CSR_SEQUENCEREG0B35S1_LSB 0 +#define CSR_SEQUENCEREG0B35S1_MASK GENMASK_32(15, 0) +/* CSR_SEQUENCEREG0B35S2 */ +#define CSR_SEQUENCEREG0B35S2_LSB 0 +#define CSR_SEQUENCEREG0B35S2_MASK GENMASK_32(8, 0) +/* CSR_SEQUENCEREG0B36S0 */ +#define CSR_SEQUENCEREG0B36S0_LSB 0 +#define CSR_SEQUENCEREG0B36S0_MASK GENMASK_32(15, 0) +/* CSR_SEQUENCEREG0B36S1 */ +#define CSR_SEQUENCEREG0B36S1_LSB 0 +#define CSR_SEQUENCEREG0B36S1_MASK GENMASK_32(15, 0) +/* CSR_SEQUENCEREG0B36S2 */ +#define CSR_SEQUENCEREG0B36S2_LSB 0 +#define CSR_SEQUENCEREG0B36S2_MASK GENMASK_32(8, 0) +/* CSR_SEQUENCEREG0B37S0 */ +#define CSR_SEQUENCEREG0B37S0_LSB 0 +#define CSR_SEQUENCEREG0B37S0_MASK GENMASK_32(15, 0) +/* CSR_SEQUENCEREG0B37S1 */ +#define CSR_SEQUENCEREG0B37S1_LSB 0 +#define CSR_SEQUENCEREG0B37S1_MASK GENMASK_32(15, 0) +/* CSR_SEQUENCEREG0B37S2 */ +#define CSR_SEQUENCEREG0B37S2_LSB 0 +#define CSR_SEQUENCEREG0B37S2_MASK GENMASK_32(8, 0) +/* CSR_SEQUENCEREG0B38S0 */ +#define CSR_SEQUENCEREG0B38S0_LSB 0 +#define CSR_SEQUENCEREG0B38S0_MASK GENMASK_32(15, 0) +/* CSR_SEQUENCEREG0B38S1 */ +#define CSR_SEQUENCEREG0B38S1_LSB 0 +#define CSR_SEQUENCEREG0B38S1_MASK GENMASK_32(15, 0) +/* CSR_SEQUENCEREG0B38S2 */ +#define CSR_SEQUENCEREG0B38S2_LSB 0 +#define CSR_SEQUENCEREG0B38S2_MASK GENMASK_32(8, 0) +/* CSR_SEQUENCEREG0B39S0 */ +#define CSR_SEQUENCEREG0B39S0_LSB 0 +#define CSR_SEQUENCEREG0B39S0_MASK GENMASK_32(15, 0) +/* CSR_SEQUENCEREG0B39S1 */ +#define CSR_SEQUENCEREG0B39S1_LSB 0 +#define CSR_SEQUENCEREG0B39S1_MASK GENMASK_32(15, 0) +/* CSR_SEQUENCEREG0B39S2 */ +#define CSR_SEQUENCEREG0B39S2_LSB 0 +#define CSR_SEQUENCEREG0B39S2_MASK GENMASK_32(8, 0) +/* CSR_SEQUENCEREG0B40S0 */ +#define CSR_SEQUENCEREG0B40S0_LSB 0 +#define CSR_SEQUENCEREG0B40S0_MASK GENMASK_32(15, 0) +/* CSR_SEQUENCEREG0B40S1 */ +#define CSR_SEQUENCEREG0B40S1_LSB 0 +#define CSR_SEQUENCEREG0B40S1_MASK GENMASK_32(15, 0) +/* CSR_SEQUENCEREG0B40S2 */ +#define CSR_SEQUENCEREG0B40S2_LSB 0 +#define CSR_SEQUENCEREG0B40S2_MASK GENMASK_32(8, 0) +/* CSR_SEQUENCEREG0B41S0 */ +#define CSR_SEQUENCEREG0B41S0_LSB 0 +#define CSR_SEQUENCEREG0B41S0_MASK GENMASK_32(15, 0) +/* CSR_SEQUENCEREG0B41S1 */ +#define CSR_SEQUENCEREG0B41S1_LSB 0 +#define CSR_SEQUENCEREG0B41S1_MASK GENMASK_32(15, 0) +/* CSR_SEQUENCEREG0B41S2 */ +#define CSR_SEQUENCEREG0B41S2_LSB 0 +#define CSR_SEQUENCEREG0B41S2_MASK GENMASK_32(8, 0) +/* CSR_SEQUENCEREG0B42S0 */ +#define CSR_SEQUENCEREG0B42S0_LSB 0 +#define CSR_SEQUENCEREG0B42S0_MASK GENMASK_32(15, 0) +/* CSR_SEQUENCEREG0B42S1 */ +#define CSR_SEQUENCEREG0B42S1_LSB 0 +#define CSR_SEQUENCEREG0B42S1_MASK GENMASK_32(15, 0) +/* CSR_SEQUENCEREG0B42S2 */ +#define CSR_SEQUENCEREG0B42S2_LSB 0 +#define CSR_SEQUENCEREG0B42S2_MASK GENMASK_32(8, 0) +/* CSR_SEQUENCEREG0B43S0 */ +#define CSR_SEQUENCEREG0B43S0_LSB 0 +#define CSR_SEQUENCEREG0B43S0_MASK GENMASK_32(15, 0) +/* CSR_SEQUENCEREG0B43S1 */ +#define CSR_SEQUENCEREG0B43S1_LSB 0 +#define CSR_SEQUENCEREG0B43S1_MASK GENMASK_32(15, 0) +/* CSR_SEQUENCEREG0B43S2 */ +#define CSR_SEQUENCEREG0B43S2_LSB 0 +#define CSR_SEQUENCEREG0B43S2_MASK GENMASK_32(8, 0) +/* CSR_SEQUENCEREG0B44S0 */ +#define CSR_SEQUENCEREG0B44S0_LSB 0 +#define CSR_SEQUENCEREG0B44S0_MASK GENMASK_32(15, 0) +/* CSR_SEQUENCEREG0B44S1 */ +#define CSR_SEQUENCEREG0B44S1_LSB 0 +#define CSR_SEQUENCEREG0B44S1_MASK GENMASK_32(15, 0) +/* CSR_SEQUENCEREG0B44S2 */ +#define CSR_SEQUENCEREG0B44S2_LSB 0 +#define CSR_SEQUENCEREG0B44S2_MASK GENMASK_32(8, 0) +/* CSR_SEQUENCEREG0B45S0 */ +#define CSR_SEQUENCEREG0B45S0_LSB 0 +#define CSR_SEQUENCEREG0B45S0_MASK GENMASK_32(15, 0) +/* CSR_SEQUENCEREG0B45S1 */ +#define CSR_SEQUENCEREG0B45S1_LSB 0 +#define CSR_SEQUENCEREG0B45S1_MASK GENMASK_32(15, 0) +/* CSR_SEQUENCEREG0B45S2 */ +#define CSR_SEQUENCEREG0B45S2_LSB 0 +#define CSR_SEQUENCEREG0B45S2_MASK GENMASK_32(8, 0) +/* CSR_SEQUENCEREG0B46S0 */ +#define CSR_SEQUENCEREG0B46S0_LSB 0 +#define CSR_SEQUENCEREG0B46S0_MASK GENMASK_32(15, 0) +/* CSR_SEQUENCEREG0B46S1 */ +#define CSR_SEQUENCEREG0B46S1_LSB 0 +#define CSR_SEQUENCEREG0B46S1_MASK GENMASK_32(15, 0) +/* CSR_SEQUENCEREG0B46S2 */ +#define CSR_SEQUENCEREG0B46S2_LSB 0 +#define CSR_SEQUENCEREG0B46S2_MASK GENMASK_32(8, 0) +/* CSR_SEQUENCEREG0B47S0 */ +#define CSR_SEQUENCEREG0B47S0_LSB 0 +#define CSR_SEQUENCEREG0B47S0_MASK GENMASK_32(15, 0) +/* CSR_SEQUENCEREG0B47S1 */ +#define CSR_SEQUENCEREG0B47S1_LSB 0 +#define CSR_SEQUENCEREG0B47S1_MASK GENMASK_32(15, 0) +/* CSR_SEQUENCEREG0B47S2 */ +#define CSR_SEQUENCEREG0B47S2_LSB 0 +#define CSR_SEQUENCEREG0B47S2_MASK GENMASK_32(8, 0) +/* CSR_SEQUENCEREG0B48S0 */ +#define CSR_SEQUENCEREG0B48S0_LSB 0 +#define CSR_SEQUENCEREG0B48S0_MASK GENMASK_32(15, 0) +/* CSR_SEQUENCEREG0B48S1 */ +#define CSR_SEQUENCEREG0B48S1_LSB 0 +#define CSR_SEQUENCEREG0B48S1_MASK GENMASK_32(15, 0) +/* CSR_SEQUENCEREG0B48S2 */ +#define CSR_SEQUENCEREG0B48S2_LSB 0 +#define CSR_SEQUENCEREG0B48S2_MASK GENMASK_32(8, 0) +/* CSR_SEQUENCEREG0B49S0 */ +#define CSR_SEQUENCEREG0B49S0_LSB 0 +#define CSR_SEQUENCEREG0B49S0_MASK GENMASK_32(15, 0) +/* CSR_SEQUENCEREG0B49S1 */ +#define CSR_SEQUENCEREG0B49S1_LSB 0 +#define CSR_SEQUENCEREG0B49S1_MASK GENMASK_32(15, 0) +/* CSR_SEQUENCEREG0B49S2 */ +#define CSR_SEQUENCEREG0B49S2_LSB 0 +#define CSR_SEQUENCEREG0B49S2_MASK GENMASK_32(8, 0) +/* CSR_SEQUENCEREG0B50S0 */ +#define CSR_SEQUENCEREG0B50S0_LSB 0 +#define CSR_SEQUENCEREG0B50S0_MASK GENMASK_32(15, 0) +/* CSR_SEQUENCEREG0B50S1 */ +#define CSR_SEQUENCEREG0B50S1_LSB 0 +#define CSR_SEQUENCEREG0B50S1_MASK GENMASK_32(15, 0) +/* CSR_SEQUENCEREG0B50S2 */ +#define CSR_SEQUENCEREG0B50S2_LSB 0 +#define CSR_SEQUENCEREG0B50S2_MASK GENMASK_32(8, 0) +/* CSR_SEQUENCEREG0B51S0 */ +#define CSR_SEQUENCEREG0B51S0_LSB 0 +#define CSR_SEQUENCEREG0B51S0_MASK GENMASK_32(15, 0) +/* CSR_SEQUENCEREG0B51S1 */ +#define CSR_SEQUENCEREG0B51S1_LSB 0 +#define CSR_SEQUENCEREG0B51S1_MASK GENMASK_32(15, 0) +/* CSR_SEQUENCEREG0B51S2 */ +#define CSR_SEQUENCEREG0B51S2_LSB 0 +#define CSR_SEQUENCEREG0B51S2_MASK GENMASK_32(8, 0) +/* CSR_SEQUENCEREG0B52S0 */ +#define CSR_SEQUENCEREG0B52S0_LSB 0 +#define CSR_SEQUENCEREG0B52S0_MASK GENMASK_32(15, 0) +/* CSR_SEQUENCEREG0B52S1 */ +#define CSR_SEQUENCEREG0B52S1_LSB 0 +#define CSR_SEQUENCEREG0B52S1_MASK GENMASK_32(15, 0) +/* CSR_SEQUENCEREG0B52S2 */ +#define CSR_SEQUENCEREG0B52S2_LSB 0 +#define CSR_SEQUENCEREG0B52S2_MASK GENMASK_32(8, 0) +/* CSR_SEQUENCEREG0B53S0 */ +#define CSR_SEQUENCEREG0B53S0_LSB 0 +#define CSR_SEQUENCEREG0B53S0_MASK GENMASK_32(15, 0) +/* CSR_SEQUENCEREG0B53S1 */ +#define CSR_SEQUENCEREG0B53S1_LSB 0 +#define CSR_SEQUENCEREG0B53S1_MASK GENMASK_32(15, 0) +/* CSR_SEQUENCEREG0B53S2 */ +#define CSR_SEQUENCEREG0B53S2_LSB 0 +#define CSR_SEQUENCEREG0B53S2_MASK GENMASK_32(8, 0) +/* CSR_SEQUENCEREG0B54S0 */ +#define CSR_SEQUENCEREG0B54S0_LSB 0 +#define CSR_SEQUENCEREG0B54S0_MASK GENMASK_32(15, 0) +/* CSR_SEQUENCEREG0B54S1 */ +#define CSR_SEQUENCEREG0B54S1_LSB 0 +#define CSR_SEQUENCEREG0B54S1_MASK GENMASK_32(15, 0) +/* CSR_SEQUENCEREG0B54S2 */ +#define CSR_SEQUENCEREG0B54S2_LSB 0 +#define CSR_SEQUENCEREG0B54S2_MASK GENMASK_32(8, 0) +/* CSR_SEQUENCEREG0B55S0 */ +#define CSR_SEQUENCEREG0B55S0_LSB 0 +#define CSR_SEQUENCEREG0B55S0_MASK GENMASK_32(15, 0) +/* CSR_SEQUENCEREG0B55S1 */ +#define CSR_SEQUENCEREG0B55S1_LSB 0 +#define CSR_SEQUENCEREG0B55S1_MASK GENMASK_32(15, 0) +/* CSR_SEQUENCEREG0B55S2 */ +#define CSR_SEQUENCEREG0B55S2_LSB 0 +#define CSR_SEQUENCEREG0B55S2_MASK GENMASK_32(8, 0) +/* CSR_SEQUENCEREG0B56S0 */ +#define CSR_SEQUENCEREG0B56S0_LSB 0 +#define CSR_SEQUENCEREG0B56S0_MASK GENMASK_32(15, 0) +/* CSR_SEQUENCEREG0B56S1 */ +#define CSR_SEQUENCEREG0B56S1_LSB 0 +#define CSR_SEQUENCEREG0B56S1_MASK GENMASK_32(15, 0) +/* CSR_SEQUENCEREG0B56S2 */ +#define CSR_SEQUENCEREG0B56S2_LSB 0 +#define CSR_SEQUENCEREG0B56S2_MASK GENMASK_32(8, 0) +/* CSR_SEQUENCEREG0B57S0 */ +#define CSR_SEQUENCEREG0B57S0_LSB 0 +#define CSR_SEQUENCEREG0B57S0_MASK GENMASK_32(15, 0) +/* CSR_SEQUENCEREG0B57S1 */ +#define CSR_SEQUENCEREG0B57S1_LSB 0 +#define CSR_SEQUENCEREG0B57S1_MASK GENMASK_32(15, 0) +/* CSR_SEQUENCEREG0B57S2 */ +#define CSR_SEQUENCEREG0B57S2_LSB 0 +#define CSR_SEQUENCEREG0B57S2_MASK GENMASK_32(8, 0) +/* CSR_SEQUENCEREG0B58S0 */ +#define CSR_SEQUENCEREG0B58S0_LSB 0 +#define CSR_SEQUENCEREG0B58S0_MASK GENMASK_32(15, 0) +/* CSR_SEQUENCEREG0B58S1 */ +#define CSR_SEQUENCEREG0B58S1_LSB 0 +#define CSR_SEQUENCEREG0B58S1_MASK GENMASK_32(15, 0) +/* CSR_SEQUENCEREG0B58S2 */ +#define CSR_SEQUENCEREG0B58S2_LSB 0 +#define CSR_SEQUENCEREG0B58S2_MASK GENMASK_32(8, 0) +/* CSR_SEQUENCEREG0B59S0 */ +#define CSR_SEQUENCEREG0B59S0_LSB 0 +#define CSR_SEQUENCEREG0B59S0_MASK GENMASK_32(15, 0) +/* CSR_SEQUENCEREG0B59S1 */ +#define CSR_SEQUENCEREG0B59S1_LSB 0 +#define CSR_SEQUENCEREG0B59S1_MASK GENMASK_32(15, 0) +/* CSR_SEQUENCEREG0B59S2 */ +#define CSR_SEQUENCEREG0B59S2_LSB 0 +#define CSR_SEQUENCEREG0B59S2_MASK GENMASK_32(8, 0) +/* CSR_SEQUENCEREG0B60S0 */ +#define CSR_SEQUENCEREG0B60S0_LSB 0 +#define CSR_SEQUENCEREG0B60S0_MASK GENMASK_32(15, 0) +/* CSR_SEQUENCEREG0B60S1 */ +#define CSR_SEQUENCEREG0B60S1_LSB 0 +#define CSR_SEQUENCEREG0B60S1_MASK GENMASK_32(15, 0) +/* CSR_SEQUENCEREG0B60S2 */ +#define CSR_SEQUENCEREG0B60S2_LSB 0 +#define CSR_SEQUENCEREG0B60S2_MASK GENMASK_32(8, 0) +/* CSR_SEQUENCEREG0B61S0 */ +#define CSR_SEQUENCEREG0B61S0_LSB 0 +#define CSR_SEQUENCEREG0B61S0_MASK GENMASK_32(15, 0) +/* CSR_SEQUENCEREG0B61S1 */ +#define CSR_SEQUENCEREG0B61S1_LSB 0 +#define CSR_SEQUENCEREG0B61S1_MASK GENMASK_32(15, 0) +/* CSR_SEQUENCEREG0B61S2 */ +#define CSR_SEQUENCEREG0B61S2_LSB 0 +#define CSR_SEQUENCEREG0B61S2_MASK GENMASK_32(8, 0) +/* CSR_SEQUENCEREG0B62S0 */ +#define CSR_SEQUENCEREG0B62S0_LSB 0 +#define CSR_SEQUENCEREG0B62S0_MASK GENMASK_32(15, 0) +/* CSR_SEQUENCEREG0B62S1 */ +#define CSR_SEQUENCEREG0B62S1_LSB 0 +#define CSR_SEQUENCEREG0B62S1_MASK GENMASK_32(15, 0) +/* CSR_SEQUENCEREG0B62S2 */ +#define CSR_SEQUENCEREG0B62S2_LSB 0 +#define CSR_SEQUENCEREG0B62S2_MASK GENMASK_32(8, 0) +/* CSR_SEQUENCEREG0B63S0 */ +#define CSR_SEQUENCEREG0B63S0_LSB 0 +#define CSR_SEQUENCEREG0B63S0_MASK GENMASK_32(15, 0) +/* CSR_SEQUENCEREG0B63S1 */ +#define CSR_SEQUENCEREG0B63S1_LSB 0 +#define CSR_SEQUENCEREG0B63S1_MASK GENMASK_32(15, 0) +/* CSR_SEQUENCEREG0B63S2 */ +#define CSR_SEQUENCEREG0B63S2_LSB 0 +#define CSR_SEQUENCEREG0B63S2_MASK GENMASK_32(8, 0) +/* CSR_SEQUENCEREG0B64S0 */ +#define CSR_SEQUENCEREG0B64S0_LSB 0 +#define CSR_SEQUENCEREG0B64S0_MASK GENMASK_32(15, 0) +/* CSR_SEQUENCEREG0B64S1 */ +#define CSR_SEQUENCEREG0B64S1_LSB 0 +#define CSR_SEQUENCEREG0B64S1_MASK GENMASK_32(15, 0) +/* CSR_SEQUENCEREG0B64S2 */ +#define CSR_SEQUENCEREG0B64S2_LSB 0 +#define CSR_SEQUENCEREG0B64S2_MASK GENMASK_32(8, 0) +/* CSR_SEQUENCEREG0B65S0 */ +#define CSR_SEQUENCEREG0B65S0_LSB 0 +#define CSR_SEQUENCEREG0B65S0_MASK GENMASK_32(15, 0) +/* CSR_SEQUENCEREG0B65S1 */ +#define CSR_SEQUENCEREG0B65S1_LSB 0 +#define CSR_SEQUENCEREG0B65S1_MASK GENMASK_32(15, 0) +/* CSR_SEQUENCEREG0B65S2 */ +#define CSR_SEQUENCEREG0B65S2_LSB 0 +#define CSR_SEQUENCEREG0B65S2_MASK GENMASK_32(8, 0) +/* CSR_SEQUENCEREG0B66S0 */ +#define CSR_SEQUENCEREG0B66S0_LSB 0 +#define CSR_SEQUENCEREG0B66S0_MASK GENMASK_32(15, 0) +/* CSR_SEQUENCEREG0B66S1 */ +#define CSR_SEQUENCEREG0B66S1_LSB 0 +#define CSR_SEQUENCEREG0B66S1_MASK GENMASK_32(15, 0) +/* CSR_SEQUENCEREG0B66S2 */ +#define CSR_SEQUENCEREG0B66S2_LSB 0 +#define CSR_SEQUENCEREG0B66S2_MASK GENMASK_32(8, 0) +/* CSR_SEQUENCEREG0B67S0 */ +#define CSR_SEQUENCEREG0B67S0_LSB 0 +#define CSR_SEQUENCEREG0B67S0_MASK GENMASK_32(15, 0) +/* CSR_SEQUENCEREG0B67S1 */ +#define CSR_SEQUENCEREG0B67S1_LSB 0 +#define CSR_SEQUENCEREG0B67S1_MASK GENMASK_32(15, 0) +/* CSR_SEQUENCEREG0B67S2 */ +#define CSR_SEQUENCEREG0B67S2_LSB 0 +#define CSR_SEQUENCEREG0B67S2_MASK GENMASK_32(8, 0) +/* CSR_SEQUENCEREG0B68S0 */ +#define CSR_SEQUENCEREG0B68S0_LSB 0 +#define CSR_SEQUENCEREG0B68S0_MASK GENMASK_32(15, 0) +/* CSR_SEQUENCEREG0B68S1 */ +#define CSR_SEQUENCEREG0B68S1_LSB 0 +#define CSR_SEQUENCEREG0B68S1_MASK GENMASK_32(15, 0) +/* CSR_SEQUENCEREG0B68S2 */ +#define CSR_SEQUENCEREG0B68S2_LSB 0 +#define CSR_SEQUENCEREG0B68S2_MASK GENMASK_32(8, 0) +/* CSR_SEQUENCEREG0B69S0 */ +#define CSR_SEQUENCEREG0B69S0_LSB 0 +#define CSR_SEQUENCEREG0B69S0_MASK GENMASK_32(15, 0) +/* CSR_SEQUENCEREG0B69S1 */ +#define CSR_SEQUENCEREG0B69S1_LSB 0 +#define CSR_SEQUENCEREG0B69S1_MASK GENMASK_32(15, 0) +/* CSR_SEQUENCEREG0B69S2 */ +#define CSR_SEQUENCEREG0B69S2_LSB 0 +#define CSR_SEQUENCEREG0B69S2_MASK GENMASK_32(8, 0) +/* CSR_SEQUENCEREG0B70S0 */ +#define CSR_SEQUENCEREG0B70S0_LSB 0 +#define CSR_SEQUENCEREG0B70S0_MASK GENMASK_32(15, 0) +/* CSR_SEQUENCEREG0B70S1 */ +#define CSR_SEQUENCEREG0B70S1_LSB 0 +#define CSR_SEQUENCEREG0B70S1_MASK GENMASK_32(15, 0) +/* CSR_SEQUENCEREG0B70S2 */ +#define CSR_SEQUENCEREG0B70S2_LSB 0 +#define CSR_SEQUENCEREG0B70S2_MASK GENMASK_32(8, 0) +/* CSR_SEQUENCEREG0B71S0 */ +#define CSR_SEQUENCEREG0B71S0_LSB 0 +#define CSR_SEQUENCEREG0B71S0_MASK GENMASK_32(15, 0) +/* CSR_SEQUENCEREG0B71S1 */ +#define CSR_SEQUENCEREG0B71S1_LSB 0 +#define CSR_SEQUENCEREG0B71S1_MASK GENMASK_32(15, 0) +/* CSR_SEQUENCEREG0B71S2 */ +#define CSR_SEQUENCEREG0B71S2_LSB 0 +#define CSR_SEQUENCEREG0B71S2_MASK GENMASK_32(8, 0) +/* CSR_SEQUENCEREG0B72S0 */ +#define CSR_SEQUENCEREG0B72S0_LSB 0 +#define CSR_SEQUENCEREG0B72S0_MASK GENMASK_32(15, 0) +/* CSR_SEQUENCEREG0B72S1 */ +#define CSR_SEQUENCEREG0B72S1_LSB 0 +#define CSR_SEQUENCEREG0B72S1_MASK GENMASK_32(15, 0) +/* CSR_SEQUENCEREG0B72S2 */ +#define CSR_SEQUENCEREG0B72S2_LSB 0 +#define CSR_SEQUENCEREG0B72S2_MASK GENMASK_32(8, 0) +/* CSR_SEQUENCEREG0B73S0 */ +#define CSR_SEQUENCEREG0B73S0_LSB 0 +#define CSR_SEQUENCEREG0B73S0_MASK GENMASK_32(15, 0) +/* CSR_SEQUENCEREG0B73S1 */ +#define CSR_SEQUENCEREG0B73S1_LSB 0 +#define CSR_SEQUENCEREG0B73S1_MASK GENMASK_32(15, 0) +/* CSR_SEQUENCEREG0B73S2 */ +#define CSR_SEQUENCEREG0B73S2_LSB 0 +#define CSR_SEQUENCEREG0B73S2_MASK GENMASK_32(8, 0) +/* CSR_SEQUENCEREG0B74S0 */ +#define CSR_SEQUENCEREG0B74S0_LSB 0 +#define CSR_SEQUENCEREG0B74S0_MASK GENMASK_32(15, 0) +/* CSR_SEQUENCEREG0B74S1 */ +#define CSR_SEQUENCEREG0B74S1_LSB 0 +#define CSR_SEQUENCEREG0B74S1_MASK GENMASK_32(15, 0) +/* CSR_SEQUENCEREG0B74S2 */ +#define CSR_SEQUENCEREG0B74S2_LSB 0 +#define CSR_SEQUENCEREG0B74S2_MASK GENMASK_32(8, 0) +/* CSR_SEQUENCEREG0B75S0 */ +#define CSR_SEQUENCEREG0B75S0_LSB 0 +#define CSR_SEQUENCEREG0B75S0_MASK GENMASK_32(15, 0) +/* CSR_SEQUENCEREG0B75S1 */ +#define CSR_SEQUENCEREG0B75S1_LSB 0 +#define CSR_SEQUENCEREG0B75S1_MASK GENMASK_32(15, 0) +/* CSR_SEQUENCEREG0B75S2 */ +#define CSR_SEQUENCEREG0B75S2_LSB 0 +#define CSR_SEQUENCEREG0B75S2_MASK GENMASK_32(8, 0) +/* CSR_SEQUENCEREG0B76S0 */ +#define CSR_SEQUENCEREG0B76S0_LSB 0 +#define CSR_SEQUENCEREG0B76S0_MASK GENMASK_32(15, 0) +/* CSR_SEQUENCEREG0B76S1 */ +#define CSR_SEQUENCEREG0B76S1_LSB 0 +#define CSR_SEQUENCEREG0B76S1_MASK GENMASK_32(15, 0) +/* CSR_SEQUENCEREG0B76S2 */ +#define CSR_SEQUENCEREG0B76S2_LSB 0 +#define CSR_SEQUENCEREG0B76S2_MASK GENMASK_32(8, 0) +/* CSR_SEQUENCEREG0B77S0 */ +#define CSR_SEQUENCEREG0B77S0_LSB 0 +#define CSR_SEQUENCEREG0B77S0_MASK GENMASK_32(15, 0) +/* CSR_SEQUENCEREG0B77S1 */ +#define CSR_SEQUENCEREG0B77S1_LSB 0 +#define CSR_SEQUENCEREG0B77S1_MASK GENMASK_32(15, 0) +/* CSR_SEQUENCEREG0B77S2 */ +#define CSR_SEQUENCEREG0B77S2_LSB 0 +#define CSR_SEQUENCEREG0B77S2_MASK GENMASK_32(8, 0) +/* CSR_SEQUENCEREG0B78S0 */ +#define CSR_SEQUENCEREG0B78S0_LSB 0 +#define CSR_SEQUENCEREG0B78S0_MASK GENMASK_32(15, 0) +/* CSR_SEQUENCEREG0B78S1 */ +#define CSR_SEQUENCEREG0B78S1_LSB 0 +#define CSR_SEQUENCEREG0B78S1_MASK GENMASK_32(15, 0) +/* CSR_SEQUENCEREG0B78S2 */ +#define CSR_SEQUENCEREG0B78S2_LSB 0 +#define CSR_SEQUENCEREG0B78S2_MASK GENMASK_32(8, 0) +/* CSR_SEQUENCEREG0B79S0 */ +#define CSR_SEQUENCEREG0B79S0_LSB 0 +#define CSR_SEQUENCEREG0B79S0_MASK GENMASK_32(15, 0) +/* CSR_SEQUENCEREG0B79S1 */ +#define CSR_SEQUENCEREG0B79S1_LSB 0 +#define CSR_SEQUENCEREG0B79S1_MASK GENMASK_32(15, 0) +/* CSR_SEQUENCEREG0B79S2 */ +#define CSR_SEQUENCEREG0B79S2_LSB 0 +#define CSR_SEQUENCEREG0B79S2_MASK GENMASK_32(8, 0) +/* CSR_SEQUENCEREG0B80S0 */ +#define CSR_SEQUENCEREG0B80S0_LSB 0 +#define CSR_SEQUENCEREG0B80S0_MASK GENMASK_32(15, 0) +/* CSR_SEQUENCEREG0B80S1 */ +#define CSR_SEQUENCEREG0B80S1_LSB 0 +#define CSR_SEQUENCEREG0B80S1_MASK GENMASK_32(15, 0) +/* CSR_SEQUENCEREG0B80S2 */ +#define CSR_SEQUENCEREG0B80S2_LSB 0 +#define CSR_SEQUENCEREG0B80S2_MASK GENMASK_32(8, 0) +/* CSR_SEQUENCEREG0B81S0 */ +#define CSR_SEQUENCEREG0B81S0_LSB 0 +#define CSR_SEQUENCEREG0B81S0_MASK GENMASK_32(15, 0) +/* CSR_SEQUENCEREG0B81S1 */ +#define CSR_SEQUENCEREG0B81S1_LSB 0 +#define CSR_SEQUENCEREG0B81S1_MASK GENMASK_32(15, 0) +/* CSR_SEQUENCEREG0B81S2 */ +#define CSR_SEQUENCEREG0B81S2_LSB 0 +#define CSR_SEQUENCEREG0B81S2_MASK GENMASK_32(8, 0) +/* CSR_SEQUENCEREG0B82S0 */ +#define CSR_SEQUENCEREG0B82S0_LSB 0 +#define CSR_SEQUENCEREG0B82S0_MASK GENMASK_32(15, 0) +/* CSR_SEQUENCEREG0B82S1 */ +#define CSR_SEQUENCEREG0B82S1_LSB 0 +#define CSR_SEQUENCEREG0B82S1_MASK GENMASK_32(15, 0) +/* CSR_SEQUENCEREG0B82S2 */ +#define CSR_SEQUENCEREG0B82S2_LSB 0 +#define CSR_SEQUENCEREG0B82S2_MASK GENMASK_32(8, 0) +/* CSR_SEQUENCEREG0B83S0 */ +#define CSR_SEQUENCEREG0B83S0_LSB 0 +#define CSR_SEQUENCEREG0B83S0_MASK GENMASK_32(15, 0) +/* CSR_SEQUENCEREG0B83S1 */ +#define CSR_SEQUENCEREG0B83S1_LSB 0 +#define CSR_SEQUENCEREG0B83S1_MASK GENMASK_32(15, 0) +/* CSR_SEQUENCEREG0B83S2 */ +#define CSR_SEQUENCEREG0B83S2_LSB 0 +#define CSR_SEQUENCEREG0B83S2_MASK GENMASK_32(8, 0) +/* CSR_SEQUENCEREG0B84S0 */ +#define CSR_SEQUENCEREG0B84S0_LSB 0 +#define CSR_SEQUENCEREG0B84S0_MASK GENMASK_32(15, 0) +/* CSR_SEQUENCEREG0B84S1 */ +#define CSR_SEQUENCEREG0B84S1_LSB 0 +#define CSR_SEQUENCEREG0B84S1_MASK GENMASK_32(15, 0) +/* CSR_SEQUENCEREG0B84S2 */ +#define CSR_SEQUENCEREG0B84S2_LSB 0 +#define CSR_SEQUENCEREG0B84S2_MASK GENMASK_32(8, 0) +/* CSR_SEQUENCEREG0B85S0 */ +#define CSR_SEQUENCEREG0B85S0_LSB 0 +#define CSR_SEQUENCEREG0B85S0_MASK GENMASK_32(15, 0) +/* CSR_SEQUENCEREG0B85S1 */ +#define CSR_SEQUENCEREG0B85S1_LSB 0 +#define CSR_SEQUENCEREG0B85S1_MASK GENMASK_32(15, 0) +/* CSR_SEQUENCEREG0B85S2 */ +#define CSR_SEQUENCEREG0B85S2_LSB 0 +#define CSR_SEQUENCEREG0B85S2_MASK GENMASK_32(8, 0) +/* CSR_SEQUENCEREG0B86S0 */ +#define CSR_SEQUENCEREG0B86S0_LSB 0 +#define CSR_SEQUENCEREG0B86S0_MASK GENMASK_32(15, 0) +/* CSR_SEQUENCEREG0B86S1 */ +#define CSR_SEQUENCEREG0B86S1_LSB 0 +#define CSR_SEQUENCEREG0B86S1_MASK GENMASK_32(15, 0) +/* CSR_SEQUENCEREG0B86S2 */ +#define CSR_SEQUENCEREG0B86S2_LSB 0 +#define CSR_SEQUENCEREG0B86S2_MASK GENMASK_32(8, 0) +/* CSR_SEQUENCEREG0B87S0 */ +#define CSR_SEQUENCEREG0B87S0_LSB 0 +#define CSR_SEQUENCEREG0B87S0_MASK GENMASK_32(15, 0) +/* CSR_SEQUENCEREG0B87S1 */ +#define CSR_SEQUENCEREG0B87S1_LSB 0 +#define CSR_SEQUENCEREG0B87S1_MASK GENMASK_32(15, 0) +/* CSR_SEQUENCEREG0B87S2 */ +#define CSR_SEQUENCEREG0B87S2_LSB 0 +#define CSR_SEQUENCEREG0B87S2_MASK GENMASK_32(8, 0) +/* CSR_SEQUENCEREG0B88S0 */ +#define CSR_SEQUENCEREG0B88S0_LSB 0 +#define CSR_SEQUENCEREG0B88S0_MASK GENMASK_32(15, 0) +/* CSR_SEQUENCEREG0B88S1 */ +#define CSR_SEQUENCEREG0B88S1_LSB 0 +#define CSR_SEQUENCEREG0B88S1_MASK GENMASK_32(15, 0) +/* CSR_SEQUENCEREG0B88S2 */ +#define CSR_SEQUENCEREG0B88S2_LSB 0 +#define CSR_SEQUENCEREG0B88S2_MASK GENMASK_32(8, 0) +/* CSR_SEQUENCEREG0B89S0 */ +#define CSR_SEQUENCEREG0B89S0_LSB 0 +#define CSR_SEQUENCEREG0B89S0_MASK GENMASK_32(15, 0) +/* CSR_SEQUENCEREG0B89S1 */ +#define CSR_SEQUENCEREG0B89S1_LSB 0 +#define CSR_SEQUENCEREG0B89S1_MASK GENMASK_32(15, 0) +/* CSR_SEQUENCEREG0B89S2 */ +#define CSR_SEQUENCEREG0B89S2_LSB 0 +#define CSR_SEQUENCEREG0B89S2_MASK GENMASK_32(8, 0) +/* CSR_SEQUENCEREG0B90S0 */ +#define CSR_SEQUENCEREG0B90S0_LSB 0 +#define CSR_SEQUENCEREG0B90S0_MASK GENMASK_32(15, 0) +/* CSR_SEQUENCEREG0B90S1 */ +#define CSR_SEQUENCEREG0B90S1_LSB 0 +#define CSR_SEQUENCEREG0B90S1_MASK GENMASK_32(15, 0) +/* CSR_SEQUENCEREG0B90S2 */ +#define CSR_SEQUENCEREG0B90S2_LSB 0 +#define CSR_SEQUENCEREG0B90S2_MASK GENMASK_32(8, 0) +/* CSR_SEQUENCEREG0B91S0 */ +#define CSR_SEQUENCEREG0B91S0_LSB 0 +#define CSR_SEQUENCEREG0B91S0_MASK GENMASK_32(15, 0) +/* CSR_SEQUENCEREG0B91S1 */ +#define CSR_SEQUENCEREG0B91S1_LSB 0 +#define CSR_SEQUENCEREG0B91S1_MASK GENMASK_32(15, 0) +/* CSR_SEQUENCEREG0B91S2 */ +#define CSR_SEQUENCEREG0B91S2_LSB 0 +#define CSR_SEQUENCEREG0B91S2_MASK GENMASK_32(8, 0) +/* CSR_SEQUENCEREG0B92S0 */ +#define CSR_SEQUENCEREG0B92S0_LSB 0 +#define CSR_SEQUENCEREG0B92S0_MASK GENMASK_32(15, 0) +/* CSR_SEQUENCEREG0B92S1 */ +#define CSR_SEQUENCEREG0B92S1_LSB 0 +#define CSR_SEQUENCEREG0B92S1_MASK GENMASK_32(15, 0) +/* CSR_SEQUENCEREG0B92S2 */ +#define CSR_SEQUENCEREG0B92S2_LSB 0 +#define CSR_SEQUENCEREG0B92S2_MASK GENMASK_32(8, 0) +/* CSR_SEQUENCEREG0B93S0 */ +#define CSR_SEQUENCEREG0B93S0_LSB 0 +#define CSR_SEQUENCEREG0B93S0_MASK GENMASK_32(15, 0) +/* CSR_SEQUENCEREG0B93S1 */ +#define CSR_SEQUENCEREG0B93S1_LSB 0 +#define CSR_SEQUENCEREG0B93S1_MASK GENMASK_32(15, 0) +/* CSR_SEQUENCEREG0B93S2 */ +#define CSR_SEQUENCEREG0B93S2_LSB 0 +#define CSR_SEQUENCEREG0B93S2_MASK GENMASK_32(8, 0) +/* CSR_SEQUENCEREG0B94S0 */ +#define CSR_SEQUENCEREG0B94S0_LSB 0 +#define CSR_SEQUENCEREG0B94S0_MASK GENMASK_32(15, 0) +/* CSR_SEQUENCEREG0B94S1 */ +#define CSR_SEQUENCEREG0B94S1_LSB 0 +#define CSR_SEQUENCEREG0B94S1_MASK GENMASK_32(15, 0) +/* CSR_SEQUENCEREG0B94S2 */ +#define CSR_SEQUENCEREG0B94S2_LSB 0 +#define CSR_SEQUENCEREG0B94S2_MASK GENMASK_32(8, 0) +/* CSR_SEQUENCEREG0B95S0 */ +#define CSR_SEQUENCEREG0B95S0_LSB 0 +#define CSR_SEQUENCEREG0B95S0_MASK GENMASK_32(15, 0) +/* CSR_SEQUENCEREG0B95S1 */ +#define CSR_SEQUENCEREG0B95S1_LSB 0 +#define CSR_SEQUENCEREG0B95S1_MASK GENMASK_32(15, 0) +/* CSR_SEQUENCEREG0B95S2 */ +#define CSR_SEQUENCEREG0B95S2_LSB 0 +#define CSR_SEQUENCEREG0B95S2_MASK GENMASK_32(8, 0) +/* CSR_SEQUENCEREG0B96S0 */ +#define CSR_SEQUENCEREG0B96S0_LSB 0 +#define CSR_SEQUENCEREG0B96S0_MASK GENMASK_32(15, 0) +/* CSR_SEQUENCEREG0B96S1 */ +#define CSR_SEQUENCEREG0B96S1_LSB 0 +#define CSR_SEQUENCEREG0B96S1_MASK GENMASK_32(15, 0) +/* CSR_SEQUENCEREG0B96S2 */ +#define CSR_SEQUENCEREG0B96S2_LSB 0 +#define CSR_SEQUENCEREG0B96S2_MASK GENMASK_32(8, 0) +/* CSR_SEQUENCEREG0B97S0 */ +#define CSR_SEQUENCEREG0B97S0_LSB 0 +#define CSR_SEQUENCEREG0B97S0_MASK GENMASK_32(15, 0) +/* CSR_SEQUENCEREG0B97S1 */ +#define CSR_SEQUENCEREG0B97S1_LSB 0 +#define CSR_SEQUENCEREG0B97S1_MASK GENMASK_32(15, 0) +/* CSR_SEQUENCEREG0B97S2 */ +#define CSR_SEQUENCEREG0B97S2_LSB 0 +#define CSR_SEQUENCEREG0B97S2_MASK GENMASK_32(8, 0) +/* CSR_SEQUENCEREG0B98S0 */ +#define CSR_SEQUENCEREG0B98S0_LSB 0 +#define CSR_SEQUENCEREG0B98S0_MASK GENMASK_32(15, 0) +/* CSR_SEQUENCEREG0B98S1 */ +#define CSR_SEQUENCEREG0B98S1_LSB 0 +#define CSR_SEQUENCEREG0B98S1_MASK GENMASK_32(15, 0) +/* CSR_SEQUENCEREG0B98S2 */ +#define CSR_SEQUENCEREG0B98S2_LSB 0 +#define CSR_SEQUENCEREG0B98S2_MASK GENMASK_32(8, 0) +/* CSR_SEQUENCEREG0B99S0 */ +#define CSR_SEQUENCEREG0B99S0_LSB 0 +#define CSR_SEQUENCEREG0B99S0_MASK GENMASK_32(15, 0) +/* CSR_SEQUENCEREG0B99S1 */ +#define CSR_SEQUENCEREG0B99S1_LSB 0 +#define CSR_SEQUENCEREG0B99S1_MASK GENMASK_32(15, 0) +/* CSR_SEQUENCEREG0B99S2 */ +#define CSR_SEQUENCEREG0B99S2_LSB 0 +#define CSR_SEQUENCEREG0B99S2_MASK GENMASK_32(8, 0) +/* CSR_SEQUENCEREG0B100S0 */ +#define CSR_SEQUENCEREG0B100S0_LSB 0 +#define CSR_SEQUENCEREG0B100S0_MASK GENMASK_32(15, 0) +/* CSR_SEQUENCEREG0B100S1 */ +#define CSR_SEQUENCEREG0B100S1_LSB 0 +#define CSR_SEQUENCEREG0B100S1_MASK GENMASK_32(15, 0) +/* CSR_SEQUENCEREG0B100S2 */ +#define CSR_SEQUENCEREG0B100S2_LSB 0 +#define CSR_SEQUENCEREG0B100S2_MASK GENMASK_32(8, 0) +/* CSR_SEQUENCEREG0B101S0 */ +#define CSR_SEQUENCEREG0B101S0_LSB 0 +#define CSR_SEQUENCEREG0B101S0_MASK GENMASK_32(15, 0) +/* CSR_SEQUENCEREG0B101S1 */ +#define CSR_SEQUENCEREG0B101S1_LSB 0 +#define CSR_SEQUENCEREG0B101S1_MASK GENMASK_32(15, 0) +/* CSR_SEQUENCEREG0B101S2 */ +#define CSR_SEQUENCEREG0B101S2_LSB 0 +#define CSR_SEQUENCEREG0B101S2_MASK GENMASK_32(8, 0) +/* CSR_SEQUENCEREG0B102S0 */ +#define CSR_SEQUENCEREG0B102S0_LSB 0 +#define CSR_SEQUENCEREG0B102S0_MASK GENMASK_32(15, 0) +/* CSR_SEQUENCEREG0B102S1 */ +#define CSR_SEQUENCEREG0B102S1_LSB 0 +#define CSR_SEQUENCEREG0B102S1_MASK GENMASK_32(15, 0) +/* CSR_SEQUENCEREG0B102S2 */ +#define CSR_SEQUENCEREG0B102S2_LSB 0 +#define CSR_SEQUENCEREG0B102S2_MASK GENMASK_32(8, 0) +/* CSR_SEQUENCEREG0B103S0 */ +#define CSR_SEQUENCEREG0B103S0_LSB 0 +#define CSR_SEQUENCEREG0B103S0_MASK GENMASK_32(15, 0) +/* CSR_SEQUENCEREG0B103S1 */ +#define CSR_SEQUENCEREG0B103S1_LSB 0 +#define CSR_SEQUENCEREG0B103S1_MASK GENMASK_32(15, 0) +/* CSR_SEQUENCEREG0B103S2 */ +#define CSR_SEQUENCEREG0B103S2_LSB 0 +#define CSR_SEQUENCEREG0B103S2_MASK GENMASK_32(8, 0) +/* CSR_SEQUENCEREG0B104S0 */ +#define CSR_SEQUENCEREG0B104S0_LSB 0 +#define CSR_SEQUENCEREG0B104S0_MASK GENMASK_32(15, 0) +/* CSR_SEQUENCEREG0B104S1 */ +#define CSR_SEQUENCEREG0B104S1_LSB 0 +#define CSR_SEQUENCEREG0B104S1_MASK GENMASK_32(15, 0) +/* CSR_SEQUENCEREG0B104S2 */ +#define CSR_SEQUENCEREG0B104S2_LSB 0 +#define CSR_SEQUENCEREG0B104S2_MASK GENMASK_32(8, 0) +/* CSR_SEQUENCEREG0B105S0 */ +#define CSR_SEQUENCEREG0B105S0_LSB 0 +#define CSR_SEQUENCEREG0B105S0_MASK GENMASK_32(15, 0) +/* CSR_SEQUENCEREG0B105S1 */ +#define CSR_SEQUENCEREG0B105S1_LSB 0 +#define CSR_SEQUENCEREG0B105S1_MASK GENMASK_32(15, 0) +/* CSR_SEQUENCEREG0B105S2 */ +#define CSR_SEQUENCEREG0B105S2_LSB 0 +#define CSR_SEQUENCEREG0B105S2_MASK GENMASK_32(8, 0) +/* CSR_SEQUENCEREG0B106S0 */ +#define CSR_SEQUENCEREG0B106S0_LSB 0 +#define CSR_SEQUENCEREG0B106S0_MASK GENMASK_32(15, 0) +/* CSR_SEQUENCEREG0B106S1 */ +#define CSR_SEQUENCEREG0B106S1_LSB 0 +#define CSR_SEQUENCEREG0B106S1_MASK GENMASK_32(15, 0) +/* CSR_SEQUENCEREG0B106S2 */ +#define CSR_SEQUENCEREG0B106S2_LSB 0 +#define CSR_SEQUENCEREG0B106S2_MASK GENMASK_32(8, 0) +/* CSR_SEQUENCEREG0B107S0 */ +#define CSR_SEQUENCEREG0B107S0_LSB 0 +#define CSR_SEQUENCEREG0B107S0_MASK GENMASK_32(15, 0) +/* CSR_SEQUENCEREG0B107S1 */ +#define CSR_SEQUENCEREG0B107S1_LSB 0 +#define CSR_SEQUENCEREG0B107S1_MASK GENMASK_32(15, 0) +/* CSR_SEQUENCEREG0B107S2 */ +#define CSR_SEQUENCEREG0B107S2_LSB 0 +#define CSR_SEQUENCEREG0B107S2_MASK GENMASK_32(8, 0) +/* CSR_SEQUENCEREG0B108S0 */ +#define CSR_SEQUENCEREG0B108S0_LSB 0 +#define CSR_SEQUENCEREG0B108S0_MASK GENMASK_32(15, 0) +/* CSR_SEQUENCEREG0B108S1 */ +#define CSR_SEQUENCEREG0B108S1_LSB 0 +#define CSR_SEQUENCEREG0B108S1_MASK GENMASK_32(15, 0) +/* CSR_SEQUENCEREG0B108S2 */ +#define CSR_SEQUENCEREG0B108S2_LSB 0 +#define CSR_SEQUENCEREG0B108S2_MASK GENMASK_32(8, 0) +/* CSR_SEQUENCEREG0B109S0 */ +#define CSR_SEQUENCEREG0B109S0_LSB 0 +#define CSR_SEQUENCEREG0B109S0_MASK GENMASK_32(15, 0) +/* CSR_SEQUENCEREG0B109S1 */ +#define CSR_SEQUENCEREG0B109S1_LSB 0 +#define CSR_SEQUENCEREG0B109S1_MASK GENMASK_32(15, 0) +/* CSR_SEQUENCEREG0B109S2 */ +#define CSR_SEQUENCEREG0B109S2_LSB 0 +#define CSR_SEQUENCEREG0B109S2_MASK GENMASK_32(8, 0) +/* CSR_SEQUENCEREG0B110S0 */ +#define CSR_SEQUENCEREG0B110S0_LSB 0 +#define CSR_SEQUENCEREG0B110S0_MASK GENMASK_32(15, 0) +/* CSR_SEQUENCEREG0B110S1 */ +#define CSR_SEQUENCEREG0B110S1_LSB 0 +#define CSR_SEQUENCEREG0B110S1_MASK GENMASK_32(15, 0) +/* CSR_SEQUENCEREG0B110S2 */ +#define CSR_SEQUENCEREG0B110S2_LSB 0 +#define CSR_SEQUENCEREG0B110S2_MASK GENMASK_32(8, 0) +/* CSR_SEQUENCEREG0B111S0 */ +#define CSR_SEQUENCEREG0B111S0_LSB 0 +#define CSR_SEQUENCEREG0B111S0_MASK GENMASK_32(15, 0) +/* CSR_SEQUENCEREG0B111S1 */ +#define CSR_SEQUENCEREG0B111S1_LSB 0 +#define CSR_SEQUENCEREG0B111S1_MASK GENMASK_32(15, 0) +/* CSR_SEQUENCEREG0B111S2 */ +#define CSR_SEQUENCEREG0B111S2_LSB 0 +#define CSR_SEQUENCEREG0B111S2_MASK GENMASK_32(8, 0) +/* CSR_SEQUENCEREG0B112S0 */ +#define CSR_SEQUENCEREG0B112S0_LSB 0 +#define CSR_SEQUENCEREG0B112S0_MASK GENMASK_32(15, 0) +/* CSR_SEQUENCEREG0B112S1 */ +#define CSR_SEQUENCEREG0B112S1_LSB 0 +#define CSR_SEQUENCEREG0B112S1_MASK GENMASK_32(15, 0) +/* CSR_SEQUENCEREG0B112S2 */ +#define CSR_SEQUENCEREG0B112S2_LSB 0 +#define CSR_SEQUENCEREG0B112S2_MASK GENMASK_32(8, 0) +/* CSR_SEQUENCEREG0B113S0 */ +#define CSR_SEQUENCEREG0B113S0_LSB 0 +#define CSR_SEQUENCEREG0B113S0_MASK GENMASK_32(15, 0) +/* CSR_SEQUENCEREG0B113S1 */ +#define CSR_SEQUENCEREG0B113S1_LSB 0 +#define CSR_SEQUENCEREG0B113S1_MASK GENMASK_32(15, 0) +/* CSR_SEQUENCEREG0B113S2 */ +#define CSR_SEQUENCEREG0B113S2_LSB 0 +#define CSR_SEQUENCEREG0B113S2_MASK GENMASK_32(8, 0) +/* CSR_SEQUENCEREG0B114S0 */ +#define CSR_SEQUENCEREG0B114S0_LSB 0 +#define CSR_SEQUENCEREG0B114S0_MASK GENMASK_32(15, 0) +/* CSR_SEQUENCEREG0B114S1 */ +#define CSR_SEQUENCEREG0B114S1_LSB 0 +#define CSR_SEQUENCEREG0B114S1_MASK GENMASK_32(15, 0) +/* CSR_SEQUENCEREG0B114S2 */ +#define CSR_SEQUENCEREG0B114S2_LSB 0 +#define CSR_SEQUENCEREG0B114S2_MASK GENMASK_32(8, 0) +/* CSR_SEQUENCEREG0B115S0 */ +#define CSR_SEQUENCEREG0B115S0_LSB 0 +#define CSR_SEQUENCEREG0B115S0_MASK GENMASK_32(15, 0) +/* CSR_SEQUENCEREG0B115S1 */ +#define CSR_SEQUENCEREG0B115S1_LSB 0 +#define CSR_SEQUENCEREG0B115S1_MASK GENMASK_32(15, 0) +/* CSR_SEQUENCEREG0B115S2 */ +#define CSR_SEQUENCEREG0B115S2_LSB 0 +#define CSR_SEQUENCEREG0B115S2_MASK GENMASK_32(8, 0) +/* CSR_SEQUENCEREG0B116S0 */ +#define CSR_SEQUENCEREG0B116S0_LSB 0 +#define CSR_SEQUENCEREG0B116S0_MASK GENMASK_32(15, 0) +/* CSR_SEQUENCEREG0B116S1 */ +#define CSR_SEQUENCEREG0B116S1_LSB 0 +#define CSR_SEQUENCEREG0B116S1_MASK GENMASK_32(15, 0) +/* CSR_SEQUENCEREG0B116S2 */ +#define CSR_SEQUENCEREG0B116S2_LSB 0 +#define CSR_SEQUENCEREG0B116S2_MASK GENMASK_32(8, 0) +/* CSR_SEQUENCEREG0B117S0 */ +#define CSR_SEQUENCEREG0B117S0_LSB 0 +#define CSR_SEQUENCEREG0B117S0_MASK GENMASK_32(15, 0) +/* CSR_SEQUENCEREG0B117S1 */ +#define CSR_SEQUENCEREG0B117S1_LSB 0 +#define CSR_SEQUENCEREG0B117S1_MASK GENMASK_32(15, 0) +/* CSR_SEQUENCEREG0B117S2 */ +#define CSR_SEQUENCEREG0B117S2_LSB 0 +#define CSR_SEQUENCEREG0B117S2_MASK GENMASK_32(8, 0) +/* CSR_SEQUENCEREG0B118S0 */ +#define CSR_SEQUENCEREG0B118S0_LSB 0 +#define CSR_SEQUENCEREG0B118S0_MASK GENMASK_32(15, 0) +/* CSR_SEQUENCEREG0B118S1 */ +#define CSR_SEQUENCEREG0B118S1_LSB 0 +#define CSR_SEQUENCEREG0B118S1_MASK GENMASK_32(15, 0) +/* CSR_SEQUENCEREG0B118S2 */ +#define CSR_SEQUENCEREG0B118S2_LSB 0 +#define CSR_SEQUENCEREG0B118S2_MASK GENMASK_32(8, 0) +/* CSR_SEQUENCEREG0B119S0 */ +#define CSR_SEQUENCEREG0B119S0_LSB 0 +#define CSR_SEQUENCEREG0B119S0_MASK GENMASK_32(15, 0) +/* CSR_SEQUENCEREG0B119S1 */ +#define CSR_SEQUENCEREG0B119S1_LSB 0 +#define CSR_SEQUENCEREG0B119S1_MASK GENMASK_32(15, 0) +/* CSR_SEQUENCEREG0B119S2 */ +#define CSR_SEQUENCEREG0B119S2_LSB 0 +#define CSR_SEQUENCEREG0B119S2_MASK GENMASK_32(8, 0) +/* CSR_SEQUENCEREG0B120S0 */ +#define CSR_SEQUENCEREG0B120S0_LSB 0 +#define CSR_SEQUENCEREG0B120S0_MASK GENMASK_32(15, 0) +/* CSR_SEQUENCEREG0B120S1 */ +#define CSR_SEQUENCEREG0B120S1_LSB 0 +#define CSR_SEQUENCEREG0B120S1_MASK GENMASK_32(15, 0) +/* CSR_SEQUENCEREG0B120S2 */ +#define CSR_SEQUENCEREG0B120S2_LSB 0 +#define CSR_SEQUENCEREG0B120S2_MASK GENMASK_32(8, 0) +/* CSR_SEQUENCEREG0B121S0 */ +#define CSR_SEQUENCEREG0B121S0_LSB 0 +#define CSR_SEQUENCEREG0B121S0_MASK GENMASK_32(15, 0) +/* CSR_SEQUENCEREG0B121S1 */ +#define CSR_SEQUENCEREG0B121S1_LSB 0 +#define CSR_SEQUENCEREG0B121S1_MASK GENMASK_32(15, 0) +/* CSR_SEQUENCEREG0B121S2 */ +#define CSR_SEQUENCEREG0B121S2_LSB 0 +#define CSR_SEQUENCEREG0B121S2_MASK GENMASK_32(8, 0) +/* CSR_SEQ0BGPR1 */ +#define CSR_SEQ0BGPR1_LSB 0 +#define CSR_SEQ0BGPR1_MASK GENMASK_32(15, 0) +/* CSR_SEQ0BGPR2 */ +#define CSR_SEQ0BGPR2_LSB 0 +#define CSR_SEQ0BGPR2_MASK GENMASK_32(15, 0) +/* CSR_SEQ0BGPR3 */ +#define CSR_SEQ0BGPR3_LSB 0 +#define CSR_SEQ0BGPR3_MASK GENMASK_32(15, 0) +/* CSR_SEQ0BGPR4 */ +#define CSR_SEQ0BGPR4_LSB 0 +#define CSR_SEQ0BGPR4_MASK GENMASK_32(15, 0) +/* CSR_SEQ0BGPR5 */ +#define CSR_SEQ0BGPR5_LSB 0 +#define CSR_SEQ0BGPR5_MASK GENMASK_32(15, 0) +/* CSR_SEQ0BGPR6 */ +#define CSR_SEQ0BGPR6_LSB 0 +#define CSR_SEQ0BGPR6_MASK GENMASK_32(15, 0) +/* CSR_SEQ0BGPR7 */ +#define CSR_SEQ0BGPR7_LSB 0 +#define CSR_SEQ0BGPR7_MASK GENMASK_32(15, 0) +/* CSR_SEQ0BGPR8 */ +#define CSR_SEQ0BGPR8_LSB 0 +#define CSR_SEQ0BGPR8_MASK GENMASK_32(15, 0) +/* CSR_SEQ0BFIXEDADDRBITS */ +#define CSR_SEQ0BFIXEDADDRBITS_LSB 0 +#define CSR_SEQ0BFIXEDADDRBITS_MASK GENMASK_32(6, 0) +#define CSR_SEQ0BCHIPLETBITS_LSB 0 +#define CSR_SEQ0BCHIPLETBITS_MASK GENMASK_32(3, 0) +#define CSR_SEQ0BPSTATEBITS_LSB 4 +#define CSR_SEQ0BPSTATEBITS_MASK GENMASK_32(6, 4) + +/* DRTUB0 register offsets */ +/* CSR_DCTSHADOWREGS */ +#define CSR_DCTSHADOWREGS_LSB 0 +#define CSR_DCTSHADOWREGS_MASK BIT(0) +#define CSR_DCTWRITEPROTSHADOW_LSB 0 +#define CSR_DCTWRITEPROTSHADOW_MASK BIT(0) +/* CSR_DCTWRITEONLYSHADOW */ +#define CSR_DCTWRITEONLYSHADOW_LSB 0 +#define CSR_DCTWRITEONLYSHADOW_MASK GENMASK_32(15, 0) +/* CSR_UCTWRITEONLY */ +#define CSR_UCTWRITEONLY_LSB 0 +#define CSR_UCTWRITEONLY_MASK GENMASK_32(15, 0) +/* CSR_UCTWRITEPROT */ +#define CSR_UCTWRITEPROT_LSB 0 +#define CSR_UCTWRITEPROT_MASK BIT(0) +/* CSR_UCTDATWRITEONLY */ +#define CSR_UCTDATWRITEONLY_LSB 0 +#define CSR_UCTDATWRITEONLY_MASK GENMASK_32(15, 0) +/* CSR_UCTDATWRITEPROT */ +#define CSR_UCTDATWRITEPROT_LSB 0 +#define CSR_UCTDATWRITEPROT_MASK BIT(0) +/* CSR_UCTLERR */ +#define CSR_UCTLERR_LSB 0 +#define CSR_UCTLERR_MASK BIT(0) +/* CSR_UCCLKHCLKENABLES */ +#define CSR_UCCLKHCLKENABLES_LSB 0 +#define CSR_UCCLKHCLKENABLES_MASK GENMASK_32(1, 0) +#define CSR_UCCLKEN_LSB 0 +#define CSR_UCCLKEN_MASK BIT(0) +#define CSR_HCLKEN_LSB 1 +#define CSR_HCLKEN_MASK BIT(1) +/* CSR_CURPSTATE0B */ +#define CSR_CURPSTATE0B_LSB 0 +#define CSR_CURPSTATE0B_MASK GENMASK_32(3, 0) +/* CSR_CLRWAKEUPSTICKY */ +#define CSR_CLRWAKEUPSTICKY_LSB 0 +#define CSR_CLRWAKEUPSTICKY_MASK GENMASK_32(3, 0) +/* CSR_WAKEUPMASK */ +#define CSR_WAKEUPMASK_LSB 0 +#define CSR_WAKEUPMASK_MASK GENMASK_32(3, 0) +/* CSR_CUSTPUBREV */ +#define CSR_CUSTPUBREV_LSB 0 +#define CSR_CUSTPUBREV_MASK GENMASK_32(5, 0) +/* CSR_PUBREV */ +#define CSR_PUBREV_LSB 0 +#define CSR_PUBREV_MASK GENMASK_32(15, 0) +#define CSR_RESERVEDPUBREV_LSB 0 +#define CSR_RESERVEDPUBREV_MASK GENMASK_32(3, 0) +#define CSR_PUBMNR_LSB 4 +#define CSR_PUBMNR_MASK GENMASK_32(7, 4) +#define CSR_PUBMDR_LSB 8 +#define CSR_PUBMDR_MASK GENMASK_32(11, 8) +#define CSR_PUBMJR_LSB 12 +#define CSR_PUBMJR_MASK GENMASK_32(15, 12) + +/* APBONLY0 register offsets */ +/* CSR_MICROCONTMUXSEL */ +#define CSR_MICROCONTMUXSEL_LSB 0 +#define CSR_MICROCONTMUXSEL_MASK BIT(0) +/* CSR_UCTSHADOWREGS */ +#define CSR_UCTSHADOWREGS_LSB 0 +#define CSR_UCTSHADOWREGS_MASK GENMASK_32(1, 0) +#define CSR_UCTWRITEPROTSHADOW_LSB 0 +#define CSR_UCTWRITEPROTSHADOW_MASK BIT(0) +#define CSR_UCTDATWRITEPROTSHADOW_LSB 1 +#define CSR_UCTDATWRITEPROTSHADOW_MASK BIT(1) +/* CSR_DCTWRITEONLY */ +#define CSR_DCTWRITEONLY_LSB 0 +#define CSR_DCTWRITEONLY_MASK GENMASK_32(15, 0) +/* CSR_DCTWRITEPROT */ +#define CSR_DCTWRITEPROT_LSB 0 +#define CSR_DCTWRITEPROT_MASK BIT(0) +/* CSR_UCTWRITEONLYSHADOW */ +#define CSR_UCTWRITEONLYSHADOW_LSB 0 +#define CSR_UCTWRITEONLYSHADOW_MASK GENMASK_32(15, 0) +/* CSR_UCTDATWRITEONLYSHADOW */ +#define CSR_UCTDATWRITEONLYSHADOW_LSB 0 +#define CSR_UCTDATWRITEONLYSHADOW_MASK GENMASK_32(15, 0) +/* CSR_NEVERGATECSRCLOCK */ +#define CSR_NEVERGATECSRCLOCK_LSB 0 +#define CSR_NEVERGATECSRCLOCK_MASK BIT(0) +/* CSR_DFICFGRDDATAVALIDTICKS */ +#define CSR_DFICFGRDDATAVALIDTICKS_LSB 0 +#define CSR_DFICFGRDDATAVALIDTICKS_MASK GENMASK_32(5, 0) +/* CSR_MICRORESET */ +#define CSR_MICRORESET_LSB 0 +#define CSR_MICRORESET_MASK GENMASK_32(3, 0) +#define CSR_STALLTOMICRO_LSB 0 +#define CSR_STALLTOMICRO_MASK BIT(0) +#define CSR_TESTWAKEUP_LSB 1 +#define CSR_TESTWAKEUP_MASK BIT(1) +#define CSR_RSVDMICRO_LSB 2 +#define CSR_RSVDMICRO_MASK BIT(2) +#define CSR_RESETTOMICRO_LSB 3 +#define CSR_RESETTOMICRO_MASK BIT(3) +/* CSR_SEQUENCEROVERRIDE */ +#define CSR_SEQUENCEROVERRIDE_LSB 0 +#define CSR_SEQUENCEROVERRIDE_MASK GENMASK_32(10, 0) +#define CSR_FORCESEQ0BDFIFREQ_LSB 0 +#define CSR_FORCESEQ0BDFIFREQ_MASK GENMASK_32(4, 0) +#define CSR_FORCESEQ0BSTART_LSB 5 +#define CSR_FORCESEQ0BSTART_MASK BIT(5) +#define CSR_FORCESEQ0BSTOP_LSB 6 +#define CSR_FORCESEQ0BSTOP_MASK BIT(6) +#define CSR_BLOCKSEQ0BREQUESTS_LSB 7 +#define CSR_BLOCKSEQ0BREQUESTS_MASK BIT(7) +#define CSR_BLOCKSEQ0BACK_LSB 8 +#define CSR_BLOCKSEQ0BACK_MASK BIT(8) +#define CSR_DISABLETERMINATEFLAG_LSB 9 +#define CSR_DISABLETERMINATEFLAG_MASK BIT(9) +#define CSR_SELECTDFIFREQTOGPRMUX_LSB 10 +#define CSR_SELECTDFIFREQTOGPRMUX_MASK BIT(10) +/* CSR_DFIINITCOMPLETESHADOW */ +#define CSR_DFIINITCOMPLETESHADOW_LSB 0 +#define CSR_DFIINITCOMPLETESHADOW_MASK BIT(0) + +/* Fields brought to you by the letter B */ +#define B_MIN 0U +#define B_MAX 1U +#define B0 0x0U +#define B1 0x100U +#define BBRD 0xF00U +#define BB_MIN 0U +#define BB_MAX 15U +#define BB0 0x0U +#define BB1 0x1000U +#define BB2 0x2000U +#define BB3 0x3000U +#define BB4 0x4000U +#define BB5 0x5000U +#define BB6 0x6000U +#define BB7 0x7000U +#define BB8 0x8000U +#define BB9 0x9000U +#define BB10 0xA000U +#define BB11 0xB000U +#define BB12 0xC000U +#define BB13 0xD000U +#define BB14 0xE000U +#define BB15 0xF000U +#define BBBRD 0xF000U +/* Fields brought to you by the letter C */ +#define C_MIN 0U +#define C_MAX 15U +#define C0 0x0U +#define C1 0x1000U +#define C2 0x2000U +#define C3 0x3000U +#define C4 0x4000U +#define C5 0x5000U +#define C6 0x6000U +#define C7 0x7000U +#define C8 0x8000U +#define C9 0x9000U +#define C10 0xA000U +#define C11 0xB000U +#define C12 0xC000U +#define C13 0xD000U +#define C14 0xE000U +#define C15 0xF000U +#define CBRD 0xF000U +/* Fields brought to you by the letter D */ +#define D_MIN 0U +#define D_MAX 3U +#define D0 0x0U +#define D1 0x100U +#define D2 0x200U +#define D3 0x300U +#define DBRD 0xF00U +/* Fields brought to you by the letter I */ +#define I_MIN 0U +#define I_MAX 8U +#define I0 0x0U +#define I1 0x100U +#define I2 0x200U +#define I3 0x300U +#define I4 0x400U +#define I5 0x500U +#define I6 0x600U +#define I7 0x700U +#define I8 0x800U +#define IBRD 0xF00U +/* Fields brought to you by the letter J */ +#define J_MIN 0U +#define J_MAX 0U +#define J0 0x0U +#define JBRD 0xF00U +/* Fields brought to you by the letter L */ +#define L_MIN 0U +#define L_MAX 13U +#define L0 0x0U +#define L1 0x100U +#define L2 0x200U +#define L3 0x300U +#define L4 0x400U +#define L5 0x500U +#define L6 0x600U +#define L7 0x700U +#define L8 0x800U +#define L9 0x900U +#define L10 0xA00U +#define L11 0xB00U +#define L12 0xC00U +#define L13 0xD00U +#define LBRD 0xF00U +/* Fields brought to you by the letter M */ +#define M_MIN 0U +#define M_MAX 8U +#define M0 0x0U +#define M1 0x100U +#define M2 0x200U +#define M3 0x300U +#define M4 0x400U +#define M5 0x500U +#define M6 0x600U +#define M7 0x700U +#define M8 0x800U +#define MBRD 0xF00U +/* Fields brought to you by the letter N */ +#define N_MIN 0U +#define N_MAX 15U +#define N0 0x0U +#define N1 0x100U +#define N2 0x200U +#define N3 0x300U +#define N4 0x400U +#define N5 0x500U +#define N6 0x600U +#define N7 0x700U +#define N8 0x800U +#define N9 0x900U +#define N10 0xA00U +#define N11 0xB00U +#define N12 0xC00U +#define N13 0xD00U +#define N14 0xE00U +#define N15 0xF00U +#define NBRD 0xF00U +/* Fields brought to you by the letter P */ +#define P_MIN 0U +#define P_MAX 3U +#define P0 0x0U +#define P1 0x100000U +#define P2 0x200000U +#define P3 0x300000U +#define PBRD 0x700000U +#define PP_MIN 0U +#define PP_MAX 3U +#define PP0 0x0U +#define PP1 0x100000U +#define PP2 0x200000U +#define PP3 0x300000U +#define PPBRD 0x700000U +/* Fields brought to you by the letter Q */ +#define Q_MIN 0U +#define Q_MAX 3U +#define Q0 0x0U +#define Q1 0x100000U +#define Q2 0x200000U +#define Q3 0x300000U +#define QBRD 0x700000U +/* Fields brought to you by the letter R */ +#define R_MIN 0U +#define R_MAX 8U +#define R0 0x0U +#define R1 0x100U +#define R2 0x200U +#define R3 0x300U +#define R4 0x400U +#define R5 0x500U +#define R6 0x600U +#define R7 0x700U +#define R8 0x800U +#define RBRD 0xF00U +/* Fields brought to you by the letter T */ +#define T_MIN 0U +#define T_MAX 15U +#define T0 0x0U +#define T1 0x10000U +#define T2 0x20000U +#define T3 0x30000U +#define T4 0x40000U +#define T5 0x50000U +#define T6 0x60000U +#define T7 0x70000U +#define T8 0x80000U +#define T9 0x90000U +#define T10 0xA0000U +#define T11 0xB0000U +#define T12 0xC0000U +#define T13 0xD0000U +#define T14 0xE0000U +#define T15 0xF0000U +#define TBRD 0xF0000U +/* Fields brought to you by the letter U */ +#define U_MIN 0U +#define U_MAX 1U +#define U0 0x0U +#define U1 0x100U +#define UBRD 0xF00U +/* Fields brought to you by the letter Y */ +#define Y_MIN 0U +#define Y_MAX 0U +#define Y0 0x0U +#define YBRD 0xF000000U + +#define TACSM 0x40000U +#define TACSMBRD 0x4F000U +#define TALL 0xF0000U +#define TALLBRD 0xFF000U +#define TANIB 0x0U +#define TANIBBRD 0xF000U +#define TAPBONLY 0xD0000U +#define TAPBONLYBRD 0xDF000U +#define TDBYTE 0x10000U +#define TDBYTEBRD 0x1F000U +#define TDRTUB 0xC0000U +#define TDRTUBBRD 0xCF000U +#define TINITENG 0x90000U +#define TINITENGBRD 0x9F000U +#define TMASTER 0x20000U +#define TMASTERBRD 0x2F000U +#define TPPGC 0x70000U +#define TPPGCBRD 0x7F000U +#define TUCTL_MEM 0x50000U +#define TUCTL_MEMBRD 0x5F000U + +#define DBYTE_NUM 9U +#define ANIB_NUM 12U + +#endif /* DDRPHY_PHYINIT_CSR_ALL_DEFINES_H */ diff --git a/drivers/st/ddr/phy/phyinit/include/ddrphy_phyinit.h b/drivers/st/ddr/phy/phyinit/include/ddrphy_phyinit.h new file mode 100644 index 000000000..acd7072a4 --- /dev/null +++ b/drivers/st/ddr/phy/phyinit/include/ddrphy_phyinit.h @@ -0,0 +1,37 @@ +/* + * Copyright (C) 2021-2024, STMicroelectronics - All Rights Reserved + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef DDRPHY_PHYINIT_H +#define DDRPHY_PHYINIT_H + +#include + +#include + +enum message_block_field { + MB_FIELD_PSTATE, + MB_FIELD_PLLBYPASSEN, + MB_FIELD_DRAMFREQ, + MB_FIELD_DFIFREQRATIO, + MB_FIELD_BPZNRESVAL, + MB_FIELD_PHYODTIMPEDANCE, + MB_FIELD_PHYDRVIMPEDANCE, + MB_FIELD_DRAMTYPE, + MB_FIELD_DISABLEDDBYTE, + MB_FIELD_ENABLEDDQS, + MB_FIELD_PHYCFG, + MB_FIELD_X16PRESENT, + MB_FIELD_ENABLEDDQSCHA, + MB_FIELD_CSPRESENTCHA, + MB_FIELD_ENABLEDDQSCHB, + MB_FIELD_CSPRESENTCHB, +}; + +/* Function definitions */ +int ddrphy_phyinit_softsetmb(struct pmu_smb_ddr_1d *mb_ddr_1d, enum message_block_field field, + uint32_t value); +void ddrphy_phyinit_initstruct(struct stm32mp_ddr_config *config, struct pmu_smb_ddr_1d *mb_ddr_1d); +#endif /* DDRPHY_PHYINIT_H */ diff --git a/drivers/st/ddr/phy/phyinit/include/ddrphy_phyinit_struct.h b/drivers/st/ddr/phy/phyinit/include/ddrphy_phyinit_struct.h new file mode 100644 index 000000000..ae34c0c87 --- /dev/null +++ b/drivers/st/ddr/phy/phyinit/include/ddrphy_phyinit_struct.h @@ -0,0 +1,786 @@ +/* + * Copyright (C) 2021-2024, STMicroelectronics - All Rights Reserved + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef DDRPHY_PHYINIT_STRUCT_H +#define DDRPHY_PHYINIT_STRUCT_H + +/* This file defines the internal data structures used in PhyInit to store user configuration */ + +/* DIMM Type definitions */ +#define DDR_DIMMTYPE_NODIMM 4U /* No DIMM (Soldered-on) */ + +/* + * Structure for basic user inputs + * + * The following basic data structure must be set and completed correctly so + * that the PhyInit software package can accurate program PHY registers. + */ +struct user_input_basic { + uint32_t dramtype; /* + * DRAM module type. + * + * Value | Description + * ----- | ------ + * 0x0 | DDR4 + * 0x1 | DDR3 + * 0x2 | LPDDR4 + */ + + uint32_t dimmtype; /* + * DIMM type. + * + * Value | Description + * ----- | ------ + * 0x4 | No DIMM (Soldered-on) (DDR_DIMMTYPE_NODIMM) + */ + + uint32_t lp4xmode; /* + * LPDDR4X mode support. + * Only used for LPDDR4, but not valid here. + * + * Value | Description + * ----- | ------ + * 0x0 | LPDDR4 mode, when dramtype is LPDDR4 + */ + + uint32_t numdbyte; /* Number of dbytes physically instantiated */ + + uint32_t numactivedbytedfi0; /* Number of active dbytes to be controlled by dfi0 */ + + uint32_t numactivedbytedfi1; /* + * Number of active dbytes to be controlled by dfi1. + * Only used for LPDDR4. + */ + + uint32_t numanib; /* Number of ANIBs physically instantiated */ + + uint32_t numrank_dfi0; /* Number of ranks in DFI0 channel */ + + uint32_t numrank_dfi1; /* Number of ranks in DFI1 channel (if DFI1 exists) */ + + uint32_t dramdatawidth; /* + * Width of the DRAM device. + * + * Enter 4,8,16 or 32 depending on protocol and dram type + * according below table. + * + * Protocol | Valid Options | Default + * -------- | ------------- | --- + * DDR3 | 4,8,16 | 8 + * DDR4 | 4,8,16 | 8 + * LPDDR4 | 8,16 | 16 + * + * For mixed x8 and x16 width devices, set variable to x8. + */ + + uint32_t numpstates; /* Number of p-states used. Must be set to 1 */ + + uint32_t frequency; /* + * Memclk frequency for each PState. + * Memclk frequency in MHz round up to next highest integer. + * Enter 334 for 333.333, etc. + */ + + uint32_t pllbypass; /* + * Indicates if PLL should be in Bypass mode. + * If DDR datarate < 333, PLL must be in Bypass Mode. + * + * Value | Description + * ----- | ------ + * 0x1 | Enabled + * 0x0 | Disabled + */ + + uint32_t dfifreqratio; /* + * Selected Dfi Frequency ratio. + * Used to program the dfifreqratio register. This register + * controls how dfi_freq_ratio input pin should be driven + * inaccordance with DFI Spec. + * + * Binary Value | Description + * ----- | ------ + * 2'b01 | 1:2 DFI Frequency Ratio (default) + */ + + uint32_t dfi1exists; /* Indicates if the PHY configuration has Dfi1 channel */ + + uint32_t train2d; /* Obsolete. Not used. */ + + uint32_t hardmacrover; /* + * Hard Macro Family version in use. + * + * Value | Description + * ----- | ------ + * 3 | hardmacro family D + */ + + uint32_t readdbienable; /* Obsolete. Not Used. */ + + uint32_t dfimode; /* Obsolete. Not Used. */ +}; + +/* + * Structure for advanced user inputs + */ +struct user_input_advanced { + uint32_t lp4rxpreamblemode; /* + * Selects between DRAM read static vs toggle preamble. + * Determine desired DRAM Read Preamble Mode based on SI + * Analysis and DRAM Part in use. + * The PHY training firmware will program DRAM mr1-OP[3] + * after training based on setting. + * + * Value | Description + * ----- | ------ + * 0x1 | toggling preamble + * 0x0 | static preamble + */ + + uint32_t lp4postambleext; /* + * Extend write postamble in LPDDR4. + * Only used for LPDDR4. + * This variable is used to calculate LPDDR4 mr3-OP[1] set + * in the messageBlock. + * The training firmware will set DRAM MR according to MR + * value in the messageBlock at the end of training. + * Set value according to your SI analysis and DRAM + * requirement. + * + * Value | Description + * ----- | ------ + * 0x0 | half Memclk postamble + * 0x1 | 1.5 Memclk postabmle (default) + */ + + uint32_t d4rxpreamblelength; /* + * Length of read preamble in DDR4 mode. + * Only used for DDR4. + * This variable is used to calculate DDR4 mr4-OP[11] set + * in the messageBlock. + * The training firmware will set DRAM MR according to MR + * value in the messageBlock at the end of training. + * Set value according to your SI analysis and DRAM + * requirement. + * + * Value | Description + * ----- | ------ + * 0x0 | 1 Tck + * 0x1 | 2 Tck (default) + */ + + uint32_t d4txpreamblelength; /* + * Length of write preamble in DDR4 mode. + * Only used for DDR4. + * This variable is used to calculate DDR4 mr4-OP[12] set + * in the messageBlock. + * The training firmware will set DRAM MR according to MR + * value in the messageBlock at the end of training. + * Set value according to your SI analysis and DRAM + * requirement. + * + * Value | Description + * ----- | ------ + * 0x0 | 1 Tck (default) + * 0x1 | 2 Tck + */ + + uint32_t extcalresval; /* + * External Impedance calibration pull-down resistor value + * select. + * Indicates value of impedance calibration pull-down + * resistor connected to BP_ZN pin of the PHY. + * Value | Description + * ----- | ------ + * 0x0 | 240 ohm (default) + */ + + uint32_t is2ttiming; /* + * Set to 1 to use 2T timing for address/command, otherwise + * 1T timing will be used. + * Determine 1T or 2T Timing operation mode based on SI + * Analysis and DRAM Timing. + * - In 1T mode, CK, CS, CA all have the same nominal + * timing, ie. ATxDly[6:0] will have same value for all + * ANIBs. + * - In 2T mode, CK, CS,have the same nominal timing + * (e.g. AtxDly[6:0]=0x00), while CA is delayed by 1UI + * (e.g. ATxDly[6:0]=0x40) + * Used to program phycfg setting in messageBlock. + * + * Value | Description + * ----- | ------ + * 0x0 | 1T Timing (default) + * 0x1 | 2T Timing + */ + + uint32_t odtimpedance; /* + * ODT impedance in ohm. + * Used for programming TxOdtDrvStren registers. + * Enter 0 for open/high-impedance. + * Default value: 60 + */ + + uint32_t tximpedance; /* + * Tx Drive Impedance for DQ/DQS in ohm. + * Used for programming TxImpedanceCtrl1 registers. + * Enter 0 for open/high-impedance. + * Default value: 60 + */ + + uint32_t atximpedance; /* + * Tx Drive Impedance for AC in ohm. + * Used for programming ATxImpedance register. + * Enter 0 for open/high-impedance + * Default value: 20 (HMA,HMB,HMC,HMD), 40 (HME) + */ + + uint32_t memalerten; /* + * Enables BP_ALERT programming of PHY registers. + * Only used for DDR3 and DDR4. + * Used for programming MemAlertControl and MemAlertControl2 + * registers. + * Program if you require using BP_ALERT pin (to receive or + * terminate signal) of the PHY otherwise leave at default + * value to save power. + * + * Value | Description + * ----- | ------ + * 0x0 | Disable BP_ALERT (default) + */ + + uint32_t memalertpuimp; /* + * Specify MemAlert Pull-up Termination Impedance. + * Programs the pull-up termination on BP_ALERT. + * Not valid here (fixed 0 value). + */ + + uint32_t memalertvreflevel; /* + * Specify the Vref level for BP_ALERT(MemAlert) Receiver. + * Not valid here (fixed 0 value). + */ + + uint32_t memalertsyncbypass; /* + * When set, this bit bypasses the DfiClk synchronizer on + * dfi_alert_n. + * Not valid here (fixed 0 value). + */ + + uint32_t disdynadrtri; /* + * Disable Dynamic Per-MEMCLK Address Tristate feature. + * Program this variable if you require to disable this + * feature. + * - In DDR3/2T and DDR4/2T/2N modes, the dynamic tristate + * feature should be disabled if the controller cannot + * follow the 2T PHY tristate protocol. + * - In LPDDR4 mode, the dynamic tristate feature should + * be disabled. + * + * Value | Description + * ----- | ------ + * 0x1 | Disable Dynamic Tristate + */ + + uint32_t phymstrtraininterval; /* + * Specifies the how frequent dfi_phymstr_req is issued by + * PHY. + * Only required in LPDDR4. + * Based on SI analysis determine how frequent DRAM drift + * compensation and re-training is required. + * Determine if Memory controller supports DFI PHY Master + * Interface. + * Program based on desired setting for + * PPTTrainSetup.PhyMstrTrainInterval register. + * Default value: 0xa + * + * Example: + * Value | Description + * ----- | ------ + * 0xa | PPT Train Interval = 268435456 MEMCLKs (default) + */ + + uint32_t phymstrmaxreqtoack; /* + * Max time from dfi_phymstr_req asserted to dfi_phymstr_ack + * asserted. + * Only required in LPDDR4. + * Based on your Memory controller's(MC) specification + * determine how long the PHY should wait for the assertion + * of dfi_phymstr_ack once dfi_phymstr_req has been issued + * by the PHY. If the MC does not ack the PHY's request, PHY + * may issue dfi_error. + * This value will be used to program + * PPTTrainSetup.PhyMstrMaxReqToAck register. + * Default value: 0x5 + * + * Example: + * Value | Description + * ----- | ------ + * 0x5 | PPT Max. Req to Ack. = 8192 MEMCLKs (default) + */ + + uint32_t wdqsext; /* + * Enable Write DQS Extension feature of PHY. + * + * Value | Description + * ----- | ------ + * 0x0 | Disable Write DQS Extension feature. (default) + * 0x1 | Enable Write DQS Extension feature. + */ + + uint32_t calinterval; /* + * Specifies the interval between successive calibrations, + * in mS. + * Program variable based on desired setting for + * CalRate.CalInterval register. + * - Fixed 0x9 value (20mS interval) + */ + + uint32_t calonce; /* + * This setting changes the behaviour of CalRun register. + * If you desire to manually trigger impedance calibration + * in mission mode set this variable to 1, and toggle CalRun + * in mission mode. + * + * Value | Description + * ----- | ------ + * 0x0 | Calibration will proceed at the rate determined + * | by CalInterval. This field should only be changed + * | while the calibrator is idle. ie before csr + * | CalRun is set. + */ + + uint32_t lp4rl; /* + * LPDDR4 Dram Read Latency. + * Applicable only if dramtype == LPDDR4. + * This variable is used to calculate LPDDR4 mr2-OP[2:0] + * set in the messageBlock. + * The training firmware will set DRAM MR according to MR + * value in the messageBlock at the end of training. + * Please refer to JEDEC JESD209-4A (LPDDR4) Spec for + * definition of MR. + * Determine values based on your DRAM part's supported + * speed and latency bin. + * Default: calculated based on user_input_basic.frequency + * and "JEDEC JESD209-4A (LPDDR4)" Table 28 "Read and Write + * Latencies". + * Lowest latency selected when more than one latency can be + * used. For example given configuration for LPDDR4, x16, + * NoDbi and DDR533, RL=10 is selected rather than 14. + */ + + uint32_t lp4wl; /* + * LPDDR4 Dram Write Latency. + * Applicable only if dramtype == LPDDR4. + * This variable is used to calculate LPDDR4 mr2-OP[5:3] + * set in the messageBlock. + * The training firmware will set DRAM MR according to MR + * value in the messageBlock at the end of training. + * Please refer to JEDEC JESD209-4A (LPDDR4) Spec for + * definition of MR. + * Determine values based on your DRAM part's supported + * speed and latency bin. + * Default: calculated based on user_input_basic.frequency + * and "JEDEC JESD209-4A (LPDDR4)" Table 28 "Read and Write + * Latencies". + * Lowest latency selected when more than one latency can be + * used. + */ + + uint32_t lp4wls; /* + * LPDDR4 Dram WL Set. + * Applicable only if dramtype == LPDDR4. + * This variable is used to calculate LPDDR4 mr2-OP[6] set + * in the messageBlock. + * The training firmware will set DRAM MR according to MR + * value in the messageBlock at the end of training. + * Please refer to JEDEC JESD209-4A (LPDDR4) Spec for + * definition of MR. + * Determine value based on Memory controllers requirement + * of DRAM State after PHY training. + * + * Value | Description + * --- | --- + * 0x0 | WL Set "A" (default) + */ + + uint32_t lp4dbird; /* + * LPDDR4 Dram DBI-Read Enable. + * Applicable only if dramtype == LPDDR4. + * Determine if you require to using DBI for the given + * PState. + * If Read DBI is not used PHY receivers are turned off to + * save power. + * This variable is used to calculate LPDDR4 mr3-OP[6] set + * in the messageBlock. + * The training firmware will set DRAM MR according to MR + * value in the messageBlock at the end of training. + * PHY register DMIPinPresent is programmed based on this + * parameter. + * Please refer to JEDEC JESD209-4A (LPDDR4) Spec for + * definition of MR. + * + * Value | Description + * --- | --- + * 0x0 | Disabled (default) + * 0x1 | Enabled + */ + + uint32_t lp4dbiwr; /* + * LPDDR4 Dram DBI-Write Enable. + * Applicable only if dramtype == LPDDR4. + * This variable is used to calculate LPDDR4 mr3-OP[7] set + * in the messageBlock. + * The training firmware will set DRAM MR according to MR + * value in the messageBlock at the end of training. + * Please refer to JEDEC JESD209-4A (LPDDR4) Spec for + * definition of MR. + * + * Value | Description + * --- | --- + * 0x0 | Disabled (default) + * 0x1 | Enabled + */ + + uint32_t lp4nwr; /* + * LPDDR4 Write-Recovery for Auto- Pre-charge commands. + * Applicable only if dramtype == LPDDR4. + * This variable is used to calculate LPDDR4 mr1-OP[6:4] set + * in the messageBlock. + * The training firmware will set DRAM MR according to MR + * value in the messageBlock at the end of training. + * Please refer to JEDEC JESD209-4A (LPDDR4) Spec for + * definition of MR. + * Determine values based on your DRAM part's supported + * speed and latency bin. + * Default: calculated based on user_input_basic.frequency + * and "JEDEC JESD209-4A (LPDDR4)" Table 28 "Read and Write + * Latencies". + * Lowest latency selected when more than one latency can be + * used. + * + * Binary Value | Description + * --- | --- + * 000 | nWR = 6 (default) + * 001 | nWR = 10 + * 010 | nWR = 16 + * 011 | nWR = 20 + * 100 | nWR = 24 + * 101 | nWR = 30 + * 110 | nWR = 34 + * 111 | nWR = 40 + */ + + uint32_t lp4lowpowerdrv; /* + * Configure output Driver in Low power mode. + * Feature only supported for Hard Macro Family E (HME). + * Use NMOS Pull-up for Low-Power IO. + * Not valid here + */ + + uint32_t drambyteswap; /* + * DRAM Oscillator count source mapping for skip_training. + * The PHY supports swapping of DRAM oscillator count values + * between paired DBytes for the purpose of tDQSDQ DRAM + * Drift Compensation(DDC). + * Each DByte has a register bit to control the source of + * the oscillator count value used to perform tDQSDQ Drift + * compensation. + * On silicon the training firmware will determine the DByte + * swap and program PptCtlStatic register to select + * oscillator count source. When skip_train is used, + * training firmware is skipped thus manual programming may + * be required depending on configuration. + * The default hardware configuration is for odd Dbyte + * instance n to use oscillator count values from its paired + * Dbyte instance n-1. So Dbyte1 will use the oscillator + * count values from Dbyte0, Dbyte3 will use Dbyte2 and so + * on. This is required for DRAM Data width =16. + * Each bit of this field corresponds to a DBYTE: + * - bit-0 = setting for DBYTE0 + * - bit-1 = setting for DBYTE1 + * - bit-2 = setting for DBYTE2 + * - . . . + * - bit-n = setting for DBYTEn + * By setting the associated bit for each DByte to 1, PHY + * will use non-default source for count value. + * - for even Dbytes, non-default source is to use the odd + * pair count value. + * - for odd Dbytes, no-default source to use data + * received directly from the DRAM. + * Byte swapping must be the same across different ranks. + * Default value: 0x0 + * If Byte mode devices are indicated via the x8mode + * messageBlock parameter, this variable is ignored as PHY + * only supports a limited configuration set based on Byte + * mode configuration. + * + * Example: + * DramByteSwap = 0x03 - Dbyte0: use count values from + * Dbyte1, Dbyte1 uses count values received directly + * received from DRAM. + * Rest of Dbytes have default source for DRAM oscilator + * count. + */ + + uint32_t rxenbackoff; /* + * Determines the Placement of PHY Read Gate signal. + * Only used in LPDDR4 when lp4rxpreamblemode==0 (static + * preamble) for skip_train==true. + * For other dramtypes or LPDDR4-toggling-preamble no + * options are available and PhyInit will set position as + * required. See source code in + * ddrphy_phyinit_c_initphyconfig() to see how the + * RxEnBackOff register is set. + * For skip_train==false, FW will set the position based on + * Preamble. + * We recommend keeping this setting at default value. + * SI analysis is required to determine if default value + * needs to be changed. + * + * Value | Description + * ----- | --- + * 0x1 | Position read gate 1UI from the first valid edge + * | of DQS_t (LPDDR4 Static preamble only) (default) + */ + + uint32_t trainsequencectrl; /* + * Firmware Training Sequence Control. + * This input is used to program sequencectrl in + * messageBlock. + * It controls the training stages executed by firmware. + * For production silicon we recommend to use default value + * programmed by PhyInit. + */ + + uint32_t snpsumctlopt; /* + * Enable Fast Frequency Change (FFC) Optimizations + * specific to UMCTL2 (DDRCTRL). + * Not valid for dimmtype=NODIMM. + * Consult DDRCTRL documentation in Reference Manual to + * ensure when optimizations can be enabled. + * + * Value | Description + * ----- | --- + * 0 | Disable FFC MRW optimization (default) + */ + + uint32_t snpsumctlf0rc5x; /* + * F0RX5x RCD Control Word when using Fast Frequency + * Change(FFC) optimizations specific to UMCTL2 + * Not valid for dimmtype=NODIMM. + * Only valid for when SnpsUmctlOpt=1. + * When UMCTL2 optimizations are enabled PHY will perform + * RCD MRW during fast frequency change request. + * The correct RCD control word value for each PState must + * be programmed in this field. + * Consult the RCD spec and UMCTL documentation to + * determine the correct value based on DRAM configuration + * and operating speed. + */ + + uint32_t txslewrisedq; /* + * Pull-up slew rate control for DBYTE Tx. + * Value specified here will be written to register + * TxSlewRate.TxPreP by PhyInit. + * See register description for more information. + */ + + uint32_t txslewfalldq; /* + * Pull-down slew rate control for DBYTE Tx. + * Value specified here will be written to + * TxSlewRate.TxPreN by PhyInit. + * See register description for more information. + */ + + uint32_t txslewriseac; /* + * Pull-up slew rate control for ANIB Tx. + * Value specified here will be written to + * ATxSlewRate.ATxPreP. + * See register description for more information. + */ + + uint32_t txslewfallac; /* + * Pull-down slew rate control for ANIB Tx. + * Value specified here will be written to + * ATxSlewRate.ATxPreN. + * See register description for more information. + */ + + uint32_t disableretraining; /* + * Disable PHY DRAM Drift compensation re-training. + * Only applied to LPDDR4. No retraining is required in + * DDR4/3. + * Disable PHY re-training during DFI frequency change + * requests in LPDDR4. + * The purpose of retraining is to compensate for drift in + * the DRAM. + * Determine based on SI analysis and DRAM datasheet if + * retraining can be disabled. + * + * Value | Description + * ----- | --- + * 0x1 | Disable retraining + * 0x0 | Enable retraining + */ + + uint32_t disablephyupdate; /* + * Disable DFI PHY Update feature. + * Only effects LPDDR4. + * Disable DFI PHY Update feature. When set PHY will not + * assert dfi0/1_phyupd_req. + * + * Value | Description + * ----- | --- + * 0x1 | Disable DFI PHY Update + * 0x0 | Enable DFI PHY Update + */ + + uint32_t enablehighclkskewfix; /* + * Enable alternative PIE program. + * If enabled the PIE reinitializes the FIFO pointers a + * second time due for designs with large skew between + * chiplet DfiClk branches. If enabled PIE latencies in all + * protocols are increased by 60 DfiClks. + * + * Value | Description + * ----- | --- + * 0x0 | Disable (default) + */ + + uint32_t disableunusedaddrlns; /* + * Turn off or tristate Address Lanes when possible. + * + * When enabled, PHY will tristate unused address lanes to + * save power when possible by using Acx4AnibDis and + * AForceTriCont registers. + * This feature is only implemented for the default PHY + * Address bump mapping and Ranks must be populated in + * order. ie Rank1 cannot be used if Rank0 is unpopulated. + * For alternative bump mapping follow the following + * guideline to achieve maximum power savings: + * - For each unused BP_A bump program AForceTriCont[4:0] + * bits based on register description. + * - if all lanes of an Anib are unused _AND_ ANIB is not + * the first or last instance set bit associated with + * the instance in Acs4AnibDis registers. see register + * description for details. + * + * Value | Description + * ----- | --- + * 0x1 | Enable + */ + + uint32_t phyinitsequencenum; /* + * Switches between supported phyinit training sequences. + * + * Value | Description + * ----- | --- + * 0x0 | Minimizes number of Imem/Dmem loads (default) + */ + + uint32_t enabledficspolarityfix;/* + * Enable alternative PIE program. + * Set to 1 if PUB_VERSION <2.43a, otherwise set to 0. If + * enabled the PIE programs Dfi{Rd,Wr}DataCsDestMap CSR's + * to default values 0x00E4 before running PPT. + * Before exiting PPT, PIE will restore + * Dfi{Rd,Wr}DataCsDestMap CSR's to 0x00E1. + * + * Value | Description + * ----- | --- + * 0x0 | Disable (default) + */ + + uint32_t phyvref; /* + * Must be programmed with the Vref level to be used by the + * PHY during reads. + * The units of this field are a percentage of VDDQ + * according to the following equation: + * Receiver Vref = VDDQ*phyvref[6:0]/128 + * For example to set Vref at 0.75*VDDQ, set this field to + * 0x60. + * For digital simulation, any legal value can be used. For + * silicon, the users must calculate the analytical Vref by + * using the impedances, terminations, and series resistance + * present in the system. + */ + + uint32_t sequencectrl; /* + * Controls the training steps to be run. Each bit + * corresponds to a training step. + * If the bit is set to 1, the training step will run. + * If the bit is set to 0, the training step will be + * skipped. + * Training step to bit mapping: + * sequencectrl[0] = Run DevInit - Device/phy + * initialization. Should always be set. + * sequencectrl[1] = Run WrLvl - Write leveling + * sequencectrl[2] = Run RxEn - Read gate training + * sequencectrl[3] = Run RdDQS1D - 1d read dqs training + * sequencectrl[4] = Run WrDQ1D - 1d write dq training + * sequencectrl[5] = RFU, must be zero + * sequencectrl[6] = RFU, must be zero + * sequencectrl[7] = RFU, must be zero + * sequencectrl[8] = Run RdDeskew - Per lane read dq deskew + * training + * sequencectrl[9] = Run MxRdLat - Max read latency training + * sequencectrl[10] = RFU, must be zero + * sequencectrl[11] = RFU, must be zero + * sequencectrl[12] = RFU, must be zero + * sequencectrl[13] = RFU, must be zero + * sequencectrl[15-14] = RFU, must be zero + */ +}; + +/* + * Structure for mode register user inputs + * + * The following data structure must be set and completed correctly so that the PhyInit software + * package can accurate fill message block structure. + * Only some mrx are used per DDR type, on related width: + * - DDR3: mr0..2 are used (16-bits values) + * - DDR4: mr0..6 are used (16-bits values) + * - LPDDR4: mr1..4 and mr11..22 are used (8-bits values) + */ +struct user_input_mode_register { + uint32_t mr0; + uint32_t mr1; + uint32_t mr2; + uint32_t mr3; + uint32_t mr4; + uint32_t mr5; + uint32_t mr6; + uint32_t mr11; + uint32_t mr12; + uint32_t mr13; + uint32_t mr14; + uint32_t mr22; +}; + +/* + * Structure for swizzle user inputs + * + * The following data structure must be set and completed correctly sothat the PhyInit software + * package can accurate set swizzle (IO muxing) config. + * Only some swizzles are used per DDR type: + * - DDR3/DDR4: swizzle 0..32 are used + * - 26 for hwtswizzle + * - 7 for acswizzle + * - LPDDR4: swizzle 0..43 are used + * - 8 per byte for dqlnsel (total 32) + * - 6 for mapcaatodfi + * - 6 for mapcabtodfi + */ +#define NB_HWT_SWIZZLE 26U +#define NB_AC_SWIZZLE 7U +#define NB_DQLNSEL_SWIZZLE_PER_BYTE 8U +#define NB_MAPCAATODFI_SWIZZLE 6U +#define NB_MAPCABTODFI_SWIZZLE 6U +#define NB_SWIZZLE 44 +struct user_input_swizzle { + uint32_t swizzle[NB_SWIZZLE]; +}; + +#endif /* DDRPHY_PHYINIT_STRUCT_H */ diff --git a/drivers/st/ddr/phy/phyinit/include/ddrphy_phyinit_usercustom.h b/drivers/st/ddr/phy/phyinit/include/ddrphy_phyinit_usercustom.h new file mode 100644 index 000000000..b248f592e --- /dev/null +++ b/drivers/st/ddr/phy/phyinit/include/ddrphy_phyinit_usercustom.h @@ -0,0 +1,118 @@ +/* + * Copyright (C) 2021-2024, STMicroelectronics - All Rights Reserved + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef DDRPHY_PHYINIT_USERCUSTOM_H +#define DDRPHY_PHYINIT_USERCUSTOM_H + +#include +#include + +#include + +#include + +/* Message Block Structure Definitions */ +#if STM32MP_DDR3_TYPE +#include +#elif STM32MP_DDR4_TYPE +#include +#else /* STM32MP_LPDDR4_TYPE */ +#include +#endif /* STM32MP_DDR3_TYPE */ + +/* + * ------------------------------------------------------------- + * Defines for Firmware Images + * - indicate IMEM/DMEM address, size (bytes) and offsets. + * ------------------------------------------------------------- + * + * IMEM_SIZE max size of instruction memory. + * DMEM_SIZE max size of data memory. + * + * IMEM_ST_ADDR start of IMEM address in memory. + * DMEM_ST_ADDR start of DMEM address in memory. + * DMEM_BIN_OFFSET start offset in DMEM memory (message block). + */ +#if STM32MP_DDR3_TYPE +#define IMEM_SIZE 0x4C28U +#define DMEM_SIZE 0x6C8U +#elif STM32MP_DDR4_TYPE +#define IMEM_SIZE 0x6D24U +#define DMEM_SIZE 0x6CCU +#else /* STM32MP_LPDDR4_TYPE */ +#define IMEM_SIZE 0x7E50U +#define DMEM_SIZE 0x67CU +#endif /* STM32MP_DDR3_TYPE */ +#define IMEM_ST_ADDR 0x50000U +#define DMEM_ST_ADDR 0x54000U +#define DMEM_BIN_OFFSET 0x200U + +/* + * ------------------ + * Type definitions + * ------------------ + */ + +/* A structure used to SRAM memory address space */ +enum return_offset_lastaddr { + RETURN_OFFSET, + RETURN_LASTADDR +}; + +/* Enumeration of instructions for PhyInit Register Interface */ +enum reginstr { + STARTTRACK, /* Start register tracking */ + STOPTRACK, /* Stop register tracking */ + SAVEREGS, /* Save(read) tracked register values */ + RESTOREREGS, /* Restore (write) saved register values */ +}; + +/* Data structure to store register address/value pairs */ +struct reg_addr_val { + uint32_t address; /* Register address */ + uint16_t value; /* Register value */ +}; + +/* Target CSR for the impedance value for ddrphy_phyinit_mapdrvstren() */ +enum drvtype { + DRVSTRENFSDQP, + DRVSTRENFSDQN, + ODTSTRENP, + ODTSTRENN, + ADRVSTRENP, + ADRVSTRENN +}; + +/* + * ------------------------------------------------------------- + * Fixed Function prototypes + * ------------------------------------------------------------- + */ +int ddrphy_phyinit_sequence(struct stm32mp_ddr_config *config, bool skip_training, bool reten); +int ddrphy_phyinit_restore_sequence(void); +int ddrphy_phyinit_c_initphyconfig(struct stm32mp_ddr_config *config, + struct pmu_smb_ddr_1d *mb_ddr_1d, uint32_t *ardptrinitval); +void ddrphy_phyinit_d_loadimem(void); +void ddrphy_phyinit_progcsrskiptrain(struct stm32mp_ddr_config *config, + struct pmu_smb_ddr_1d *mb_ddr_1d, uint32_t ardptrinitval); +int ddrphy_phyinit_f_loaddmem(struct stm32mp_ddr_config *config, struct pmu_smb_ddr_1d *mb_ddr_1d); +int ddrphy_phyinit_g_execfw(void); +void ddrphy_phyinit_i_loadpieimage(struct stm32mp_ddr_config *config, bool skip_training); +void ddrphy_phyinit_loadpieprodcode(void); +int ddrphy_phyinit_mapdrvstren(uint32_t drvstren_ohm, enum drvtype targetcsr); +int ddrphy_phyinit_calcmb(struct stm32mp_ddr_config *config, struct pmu_smb_ddr_1d *mb_ddr_1d); +void ddrphy_phyinit_writeoutmem(uint32_t *mem, uint32_t mem_offset, uint32_t mem_size); +void ddrphy_phyinit_writeoutmsgblk(uint16_t *mem, uint32_t mem_offset, uint32_t mem_size); +int ddrphy_phyinit_isdbytedisabled(struct stm32mp_ddr_config *config, + struct pmu_smb_ddr_1d *mb_ddr_1d, uint32_t dbytenumber); +int ddrphy_phyinit_trackreg(uint32_t adr); +int ddrphy_phyinit_reginterface(enum reginstr myreginstr, uint32_t adr, uint16_t dat); + +void ddrphy_phyinit_usercustom_custompretrain(struct stm32mp_ddr_config *config); +int ddrphy_phyinit_usercustom_g_waitfwdone(void); +int ddrphy_phyinit_usercustom_saveretregs(struct stm32mp_ddr_config *config); + +#endif /* DDRPHY_PHYINIT_USERCUSTOM_H */ diff --git a/drivers/st/ddr/phy/phyinit/include/ddrphy_wrapper.h b/drivers/st/ddr/phy/phyinit/include/ddrphy_wrapper.h new file mode 100644 index 000000000..ed4be1c06 --- /dev/null +++ b/drivers/st/ddr/phy/phyinit/include/ddrphy_wrapper.h @@ -0,0 +1,20 @@ +/* + * Copyright (C) 2021-2024, STMicroelectronics - All Rights Reserved + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef DDRPHY_WRAPPER_H +#define DDRPHY_WRAPPER_H + +static inline long long fmodll(long long x, long long y) +{ + return x - ((x / y) * y); +} + +static inline int fmodi(int x, int y) +{ + return (int)fmodll((long long)x, (long long)y); +} + +#endif /* DDRPHY_WRAPPER_H */ diff --git a/drivers/st/ddr/phy/phyinit/src/ddrphy_phyinit_c_initphyconfig.c b/drivers/st/ddr/phy/phyinit/src/ddrphy_phyinit_c_initphyconfig.c new file mode 100644 index 000000000..38b8a0706 --- /dev/null +++ b/drivers/st/ddr/phy/phyinit/src/ddrphy_phyinit_c_initphyconfig.c @@ -0,0 +1,1139 @@ +/* + * Copyright (C) 2021-2024, STMicroelectronics - All Rights Reserved + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include + +#include + +#include +#include + +#include +#include + +#include + +/* + * Program txslewrate: + * - txslewrate::txpredrvmode is dependent on dramtype. + * - txslewrate::txprep and txslewrate::txpren are technology-specific. + */ +static void txslewrate_program(struct stm32mp_ddr_config *config) +{ + uint32_t txpredrvmode; + uint32_t byte; + uint32_t txpren; /* Default to 0xf (max). Optimal setting is technology specific */ + uint32_t txprep; /* Default to 0xf (max). Optimal setting is technology specific */ + uint16_t txslewrate; + +#if STM32MP_DDR3_TYPE + txpredrvmode = 0x3U; +#elif STM32MP_DDR4_TYPE + txpredrvmode = 0x2U; +#else /* STM32MP_LPDDR4_TYPE */ + txpredrvmode = 0x1U; +#endif /* STM32MP_DDR3_TYPE */ + + txprep = config->uia.txslewrisedq; + txpren = config->uia.txslewfalldq; + + txslewrate = (uint16_t)((txpredrvmode << CSR_TXPREDRVMODE_LSB) | + (txpren << CSR_TXPREN_LSB) | + (txprep << CSR_TXPREP_LSB)); + + for (byte = 0U; byte < config->uib.numdbyte; byte++) { + uint32_t c_addr; + uint32_t lane; + + c_addr = byte << 12; + for (lane = 0U; lane <= B_MAX; lane++) { + uint32_t b_addr; + + b_addr = lane << 8; + mmio_write_16((uintptr_t)(DDRPHYC_BASE + (4U * (TDBYTE | c_addr | b_addr | + CSR_TXSLEWRATE_ADDR))), + txslewrate); + } + } +} + +/* + * Program atxslewrate: + * - atxslewrate::atxpredrvmode is dependent on dramtype and whether + * the ACX4 instance is used for AC or CK. + * - atxslewrate::atxprep and atxslewrate::atxpren are technology-specific. + */ +static void atxslewrate_program(struct stm32mp_ddr_config *config) +{ + uint32_t anib; + uint32_t atxpren; /* Default to 0xf (max). Optimal setting is technology specific */ + uint32_t atxprep; /* Default to 0xf (max). Optimal setting is technology specific */ + uint32_t ck_anib_inst[2]; + + atxprep = config->uia.txslewriseac; + atxpren = config->uia.txslewfallac; + + /* + * # of ANIBs CK ANIB Instance + * ACX8 ANIB 1 + */ + if (config->uib.numanib == 8U) { + ck_anib_inst[0] = 1U; + ck_anib_inst[1] = 1U; + } + + for (anib = 0U; anib < config->uib.numanib; anib++) { + uint32_t atxpredrvmode; + uint32_t c_addr; + uint16_t atxslewrate; + + c_addr = anib << 12; + + if ((anib == ck_anib_inst[0]) || (anib == ck_anib_inst[1])) { + /* CK ANIB instance */ +#if STM32MP_DDR3_TYPE || STM32MP_DDR4_TYPE + atxpredrvmode = 0x0U; +#else /* STM32MP_LPDDR4_TYPE */ + atxpredrvmode = 0x1U; +#endif /* STM32MP_DDR3_TYPE || STM32MP_DDR4_TYPE */ + } else { + /* non-CK ANIB instance */ +#if STM32MP_DDR3_TYPE || STM32MP_DDR4_TYPE + atxpredrvmode = 0x3U; +#else /* STM32MP_LPDDR4_TYPE */ + atxpredrvmode = 0x1U; +#endif /* STM32MP_DDR3_TYPE || STM32MP_DDR4_TYPE */ + } + + atxslewrate = (uint16_t)((atxpredrvmode << CSR_ATXPREDRVMODE_LSB) | + (atxpren << CSR_ATXPREN_LSB) | + (atxprep << CSR_ATXPREP_LSB)); + + mmio_write_16((uintptr_t)(DDRPHYC_BASE + (4U * (TANIB | c_addr | + CSR_ATXSLEWRATE_ADDR))), + atxslewrate); + } +} + +#if STM32MP_DDR3_TYPE || STM32MP_DDR4_TYPE +/* + * Program dfirddatacsdestmap and dfiwrdatacsdestmap: + * - Dependencies: mb_ddr_1d->msgmisc[6] Determine Partial Rank Support. + */ +static void dfidatacsdestmap_program(struct pmu_smb_ddr_1d *mb_ddr_1d) +{ + if ((mb_ddr_1d->msgmisc & 0x40U) != 0U) { + uint16_t dfirddatacsdestmap = 0xA0U; + uint16_t dfiwrdatacsdestmap = 0xA0U; + + mmio_write_16((uintptr_t)(DDRPHYC_BASE + (4U * (TMASTER | + CSR_DFIRDDATACSDESTMAP_ADDR))), + dfirddatacsdestmap); + mmio_write_16((uintptr_t)(DDRPHYC_BASE + (4U * (TMASTER | + CSR_DFIWRDATACSDESTMAP_ADDR))), + dfiwrdatacsdestmap); + } +} +#endif /* STM32MP_DDR3_TYPE || STM32MP_DDR4_TYPE */ + +/* + * Program pllctrl2: + * - Calculate PLL controls from frequency. + */ +static void pllctrl2_program(struct stm32mp_ddr_config *config) +{ + uint16_t pllctrl2; + uint32_t halffreq = config->uib.frequency / 2U; + + if (halffreq < 235U) { + pllctrl2 = 0x7U; + } else if (halffreq < 313U) { + pllctrl2 = 0x6U; + } else if (halffreq < 469U) { + pllctrl2 = 0xBU; + } else if (halffreq < 625U) { + pllctrl2 = 0xAU; + } else if (halffreq < 938U) { + pllctrl2 = 0x19U; + } else if (halffreq < 1067U) { + pllctrl2 = 0x18U; + } else { + pllctrl2 = 0x19U; + } + + mmio_write_16((uintptr_t)(DDRPHYC_BASE + (4U * (TMASTER | CSR_PLLCTRL2_ADDR))), pllctrl2); +} + +/* + * Program ardptrinitval: + * - The values programmed here assume ideal properties of DfiClk and Pclk including: + * - DfiClk skew + * - DfiClk jitter + * - DfiClk PVT variations + * - Pclk skew + * - Pclk jitter + * + * ardptrinitval Programmed differently based on PLL Bypass mode and frequency: + * - PLL Bypassed mode: + * - For MemClk frequency > 933MHz, the valid range of ardptrinitval[3:0] is: 2-5 + * - For MemClk frequency < 933MHz, the valid range of ardptrinitval[3:0] is: 1-5 + * - PLL Enabled mode: + * - For MemClk frequency > 933MHz, the valid range of ardptrinitval[3:0] is: 1-5 + * - For MemClk frequency < 933MHz, the valid range of ardptrinitval[3:0] is: 0-5 + */ +static void ardptrinitval_program(struct stm32mp_ddr_config *config, uint32_t *ardptrinitval) +{ + uint16_t regdata; + + if (config->uib.frequency >= 933U) { + regdata = 0x2U; + } else { + regdata = 0x1U; + } + + /* Add one UI for synchronizer on SyncBus when PLL is bypassed */ + if (config->uib.pllbypass == 1U) { + regdata++; + } + + mmio_write_16((uintptr_t)(DDRPHYC_BASE + (4U * (TMASTER | CSR_ARDPTRINITVAL_ADDR))), + regdata); + + *ardptrinitval = (uint32_t)regdata; +} + +#if STM32MP_LPDDR4_TYPE +/* + * Program ProcOdtCtl: + * - Sets procodtalwayson/procodtalwaysoff for LPDDR4 using the PIE register seq0bgpr4. + */ +static void procodtctl_program(void) +{ + mmio_write_16((uintptr_t)(DDRPHYC_BASE + (4U * (TINITENG | C0 | CSR_SEQ0BGPR4_ADDR))), 0U); +} +#endif /* STM32MP_LPDDR4_TYPE */ + +/* + * Program dbytedllmodecntrl: + * - dllrxpreamblemode + * Program dqspreamblecontrol: + * - Fields: + * - twotckrxdqspre + * - twotcktxdqspre + * - positiondfeinit + * - lp4tgltwotcktxdqspre + * - lp4postambleext + * - lp4sttcprebridgerxen + * - Dependencies: + * - user_input_advanced.lp4rxpreamblemode (LPDDR4) + * - user_input_advanced.lp4postambleext (LPDDR4) + * - user_input_advanced.wdqsext (LPDDR4) + * - user_input_advanced.d4rxpreamblelength (DDR4) + * - user_input_advanced.d4txpreamblelength (DDR4) + */ +static void dbytedllmodecntrl_program(struct stm32mp_ddr_config *config, uint32_t *twotckrxdqspre) +{ + uint32_t disdllgainivseed = 1U; + uint32_t disdllseedsel = 0U; + uint32_t dllgainiv = 0x1U; + uint32_t dllgaintv = 0x6U; + uint32_t dllrxpreamblemode = 0U; + uint32_t lcdlseed0 = 0x21U; + uint32_t lp4postambleext = 0U; + uint32_t lp4sttcprebridgerxen = 0U; + uint32_t lp4tgltwotcktxdqspre = 0U; + uint32_t positiondfeinit; + uint32_t twotcktxdqspre = 0U; + uint32_t wdqsextension = 0U; + uint16_t dbytedllmodecntrl; + uint16_t dllgainctl; + uint16_t dlllockparam; + uint16_t dqspreamblecontrol; + +#if STM32MP_DDR3_TYPE + /* Same as default */ + *twotckrxdqspre = 0x0U; + lp4sttcprebridgerxen = 0x0U; + dllrxpreamblemode = 0x0U; + twotcktxdqspre = 0x0U; + lp4tgltwotcktxdqspre = 0x0U; + positiondfeinit = 0x0U; + lp4postambleext = 0x0U; +#elif STM32MP_DDR4_TYPE + *twotckrxdqspre = config->uia.d4rxpreamblelength; + lp4sttcprebridgerxen = 0x0U; + dllrxpreamblemode = 0x1U; + twotcktxdqspre = config->uia.d4txpreamblelength; + lp4tgltwotcktxdqspre = 0x0U; + positiondfeinit = 0x2U; + lp4postambleext = 0x0U; +#else /* STM32MP_LPDDR4_TYPE */ + /* Set to 1 if static Rx preamble */ + *twotckrxdqspre = (config->uia.lp4rxpreamblemode == 0U) ? 1U : 0U; + /* Set to 1 if static Rx preamble */ + lp4sttcprebridgerxen = (config->uia.lp4rxpreamblemode == 0U) ? 1U : 0U; + dllrxpreamblemode = 0x1U; + /* Must be 2*Tck Tx preamble according to JEDEC (mr1.OP[2] = 1) */ + twotcktxdqspre = 0x1U; + /* Must be toggling Tx preamble */ + lp4tgltwotcktxdqspre = 0x1U; + positiondfeinit = 0x0U; + lp4postambleext = config->uia.lp4postambleext; + wdqsextension = config->uia.wdqsext; +#endif /* STM32MP_DDR3_TYPE */ + + dqspreamblecontrol = (uint16_t)((wdqsextension << CSR_WDQSEXTENSION_LSB) | + (lp4sttcprebridgerxen << CSR_LP4STTCPREBRIDGERXEN_LSB) | + (lp4postambleext << CSR_LP4POSTAMBLEEXT_LSB) | + (lp4tgltwotcktxdqspre << CSR_LP4TGLTWOTCKTXDQSPRE_LSB) | + (positiondfeinit << CSR_POSITIONDFEINIT_LSB) | + (twotcktxdqspre << CSR_TWOTCKTXDQSPRE_LSB) | + (*twotckrxdqspre << CSR_TWOTCKRXDQSPRE_LSB)); + + mmio_write_16((uintptr_t)(DDRPHYC_BASE + (4U * (TMASTER | CSR_DQSPREAMBLECONTROL_ADDR))), + dqspreamblecontrol); + + dbytedllmodecntrl = (uint16_t)(dllrxpreamblemode << CSR_DLLRXPREAMBLEMODE_LSB); + mmio_write_16((uintptr_t)(DDRPHYC_BASE + (4U * (TMASTER | CSR_DBYTEDLLMODECNTRL_ADDR))), + dbytedllmodecntrl); + + dllgainctl = (uint16_t)(dllgainiv | (dllgaintv << CSR_DLLGAINTV_LSB)); + dlllockparam = (uint16_t)(disdllseedsel | (disdllgainivseed << CSR_DISDLLGAINIVSEED_LSB) | + (lcdlseed0 << CSR_LCDLSEED0_LSB)); + + mmio_write_16((uintptr_t)(DDRPHYC_BASE + (4U * (TMASTER | CSR_DLLLOCKPARAM_ADDR))), + dlllockparam); + + mmio_write_16((uintptr_t)(DDRPHYC_BASE + (4U * (TMASTER | CSR_DLLGAINCTL_ADDR))), + dllgainctl); +} + +/* + * Program procodttimectl: + * - Fields: + * - POdtStartDelay[3:2] + * - POdtTailWidth[1:0] + * - Dependencies: + * - user_input_basic.frequency + * - user_input_advanced.wdqsext + */ +static void procodttimectl_program(struct stm32mp_ddr_config *config, uint32_t twotckrxdqspre) +{ + uint16_t procodttimectl; + + if (config->uia.wdqsext != 0U) { + /* POdtStartDelay = 0x0 and POdtTailWidth = 0x3 */ + procodttimectl = 0x3U; + } else if (config->uib.frequency <= 933U) { + /* Memclk Freq <= 933MHz: POdtStartDelay = 0x2 and POdtTailWidth = 0x2 */ + procodttimectl = 0xAU; + } else if (config->uib.frequency <= 1200U) { + /* 933MHz < Memclk Freq <= 1200MHz */ + if (twotckrxdqspre == 1U) { + /* POdtStartDelay = 0x0 and POdtTailWidth = 0x2 */ + procodttimectl = 0x2U; + } else { + /* POdtStartDelay = 0x1 and POdtTailWidth = 0x2 */ + procodttimectl = 0x6U; + } + } else { + /* Memclk Freq > 1200MHz */ + if (twotckrxdqspre == 1U) { + /* POdtStartDelay = 0x0 and POdtTailWidth = 0x3 */ + procodttimectl = 0x3U; + } else { + /* POdtStartDelay = 0x1 and POdtTailWidth = 0x3 */ + procodttimectl = 0x7U; + } + } + + mmio_write_16((uintptr_t)(DDRPHYC_BASE + (4U * (TMASTER | CSR_PROCODTTIMECTL_ADDR))), + procodttimectl); +} + +/* + * Program txodtdrvstren: + * - Fields: + * - ODTStrenP_px[5:0] + * - ODTStrenN_px[11:6] + * - Dependencies: + * - user_input_basic.numdbyte + * - user_input_advanced.odtimpedance + * \return 0 on success. + */ +static int txodtdrvstren_program(struct stm32mp_ddr_config *config) +{ + uint32_t byte; + int odtstrenn_state; + int odtstrenp_state; + uint16_t txodtdrvstren; + + odtstrenp_state = ddrphy_phyinit_mapdrvstren(config->uia.odtimpedance, ODTSTRENP); + if (odtstrenp_state < 0) { + return odtstrenp_state; + } + + odtstrenn_state = ddrphy_phyinit_mapdrvstren(config->uia.odtimpedance, ODTSTRENN); + if (odtstrenn_state < 0) { + return odtstrenn_state; + } + + txodtdrvstren = (uint16_t)((odtstrenn_state << CSR_ODTSTRENN_LSB) | odtstrenp_state); + + for (byte = 0U; byte < config->uib.numdbyte; byte++) { + uint32_t c_addr; + uint32_t lane; + + c_addr = byte << 12; + for (lane = 0U; lane <= B_MAX; lane++) { + uint32_t b_addr; + + b_addr = lane << 8; + mmio_write_16((uintptr_t)(DDRPHYC_BASE + (4U * (TDBYTE | c_addr | b_addr | + CSR_TXODTDRVSTREN_ADDR))), + txodtdrvstren); + } + } + + return 0; +} + +/* + * Program tximpedancectrl1: + * - Fields: + * - DrvStrenFSDqP[5:0] + * - DrvStrenFSDqN[11:6] + * - Dependencies: + * - user_input_basic.numdbyte + * - user_input_advanced.tximpedance + * \return 0 on success. + */ +static int tximpedancectrl1_program(struct stm32mp_ddr_config *config) +{ + uint32_t byte; + int drvstrenfsdqn_state; + int drvstrenfsdqp_state; + uint16_t tximpedancectrl1; + + drvstrenfsdqp_state = ddrphy_phyinit_mapdrvstren(config->uia.tximpedance, + DRVSTRENFSDQP); + if (drvstrenfsdqp_state < 0) { + return drvstrenfsdqp_state; + } + + drvstrenfsdqn_state = ddrphy_phyinit_mapdrvstren(config->uia.tximpedance, + DRVSTRENFSDQN); + if (drvstrenfsdqn_state < 0) { + return drvstrenfsdqn_state; + } + + tximpedancectrl1 = (uint16_t)((drvstrenfsdqn_state << CSR_DRVSTRENFSDQN_LSB) | + (drvstrenfsdqp_state << CSR_DRVSTRENFSDQP_LSB)); + + for (byte = 0U; byte < config->uib.numdbyte; byte++) { + uint32_t c_addr; + uint32_t lane; + + c_addr = byte << 12; + for (lane = 0U; lane <= B_MAX; lane++) { + uint32_t b_addr; + + b_addr = lane << 8; + mmio_write_16((uintptr_t)(DDRPHYC_BASE + (4U * + (TDBYTE | c_addr | b_addr | + CSR_TXIMPEDANCECTRL1_ADDR))), + tximpedancectrl1); + } + } + + return 0; +} + +/* + * Program atximpedance: + * - Fields: + * - ADrvStrenP[4:0] + * - ADrvStrenN[9:5] + * - Dependencies: + * - user_input_basic.numanib + * - user_input_advanced.atximpedance + * \return 0 on success. + */ +static int atximpedance_program(struct stm32mp_ddr_config *config) +{ + int adrvstrenn_state; + int adrvstrenp_state; + uint32_t anib; + uint16_t atximpedance; + + adrvstrenp_state = ddrphy_phyinit_mapdrvstren(config->uia.atximpedance, + ADRVSTRENP); + if (adrvstrenp_state < 0) { + return adrvstrenp_state; + } + + adrvstrenn_state = ddrphy_phyinit_mapdrvstren(config->uia.atximpedance, + ADRVSTRENN); + if (adrvstrenn_state < 0) { + return adrvstrenn_state; + } + + atximpedance = (uint16_t)((adrvstrenn_state << CSR_ADRVSTRENN_LSB) | + (adrvstrenp_state << CSR_ADRVSTRENP_LSB)); + + for (anib = 0U; anib < config->uib.numanib; anib++) { + uint32_t c_addr; + + c_addr = anib << 12; + mmio_write_16((uintptr_t)(DDRPHYC_BASE + (4U * (TANIB | c_addr | + CSR_ATXIMPEDANCE_ADDR))), + atximpedance); + } + + return 0; +} + +/* + * Program dfimode: + * - Dependencies: + * - user_input_basic.dfi1exists + */ +static void dfimode_program(struct stm32mp_ddr_config *config) +{ + uint16_t dfimode = 0x5U; + +#if STM32MP_DDR3_TYPE || STM32MP_DDR4_TYPE + if (config->uib.dfi1exists == 0U) { + dfimode = 0x1U; /* DFI1 does not physically exists */ + } +#endif /* STM32MP_DDR3_TYPE || STM32MP_DDR4_TYPE */ + + mmio_write_16((uintptr_t)(DDRPHYC_BASE + (4U * (TMASTER | CSR_DFIMODE_ADDR))), dfimode); +} + +/* + * Program dficamode: + * - Fields: + * - DfiLp3CAMode + * - DfiD4CAMode + * - DfiLp4CAMode + * - DfiD4AltCAMode + */ +static void dficamode_program(void) +{ + uint16_t dficamode; + +#if STM32MP_DDR3_TYPE + dficamode = 0U; +#elif STM32MP_DDR4_TYPE + dficamode = 2U; +#else /* STM32MP_LPDDR4_TYPE */ + dficamode = 4U; +#endif /* STM32MP_DDR3_TYPE */ + + mmio_write_16((uintptr_t)(DDRPHYC_BASE + (4U * (TMASTER | CSR_DFICAMODE_ADDR))), dficamode); +} + +/* + * Program caldrvstr0: + * - Fields: + * - caldrvstrpd50[3:0] + * - caldrvstrpu50[7:4] + * - Dependencies: + * - user_input_advanced.extcalresval + */ +static void caldrvstr0_program(struct stm32mp_ddr_config *config) +{ + uint16_t caldrvstr0; + uint16_t caldrvstrp50 = (uint16_t)config->uia.extcalresval; + + caldrvstr0 = (caldrvstrp50 << CSR_CALDRVSTRPU50_LSB) | caldrvstrp50; + + mmio_write_16((uintptr_t)(DDRPHYC_BASE + (4U * (TMASTER | CSR_CALDRVSTR0_ADDR))), + caldrvstr0); +} + +/* + * Program CalUclkInfo: + * - Impedance calibration CLK Counter. + * - Fields: + * - caluclkticksper1us + * - Dependencies: + * - user_input_basic.frequency + */ +static void caluclkinfo_program(struct stm32mp_ddr_config *config) +{ + uint32_t caluclkticksper1us_x10; + uint16_t caluclkticksper1us; + + /* Number of DfiClk cycles per 1us */ + caluclkticksper1us_x10 = (10U * config->uib.frequency) / 2U; + caluclkticksper1us = (uint16_t)(caluclkticksper1us_x10 / 10U); + + if ((config->uib.frequency % 2U) != 0U) { + caluclkticksper1us++; + } + + if (caluclkticksper1us < 24U) { + /* Minimum value of caluclkticksper1us = 24 */ + caluclkticksper1us = 24U; + } + + mmio_write_16((uintptr_t)(DDRPHYC_BASE + (4U * (TMASTER | CSR_CALUCLKINFO_ADDR))), + caluclkticksper1us); +} + +/* + * Program Calibration CSRs based on user input + * - Fields: + * - calinterval + * - calonce + * - Dependencies: + * - user_input_advanced.calinterval + * - user_input_advanced.calonce + */ +static void calibration_program(struct stm32mp_ddr_config *config) +{ + uint32_t calinterval; + uint32_t calonce; + uint16_t calrate; + + calinterval = config->uia.calinterval; + calonce = config->uia.calonce; + + calrate = (uint16_t)((calonce << CSR_CALONCE_LSB) | (calinterval << CSR_CALINTERVAL_LSB)); + + mmio_write_16((uintptr_t)(DDRPHYC_BASE + (4U * (TMASTER | CSR_CALRATE_ADDR))), calrate); +} + +/* + * Program vrefinglobal: + * - dqdqsrcvcntrl and csrvrefinglobal to select Global VREF + * from Master to be used in each DQ. + * - Fields: + * - globalvrefinsel: Select Range of GlobalVref DAC. Default: set to 1. + * - globalvrefindac: Vref level is set based on mb_ddr_1d->phyvref value. + * The following formula is used to convert the phyvref into the register setting. + * \f{eqnarray*}{ + * PhyVrefPrcnt &=& \frac{mb_ddr_1d->phyvref}{128} \\ + * if globalvrefinsel = 1 : + * globalvrefindac &=& 1+\frac{PhyVrefPrcnt}{0.005} \\ + * if globalvrefinsel = 0 : + * globalvrefindac &=& \frac{(PhyVrefPrcnt-0.345)}{0.005} \\ + * RxVref &=& (globalvrefindac == 0) ? Hi-Z : (PhyVrefPrcnt \times VDDQ) + * \f} + * + * Program dqdqsrcvcntrl: + * - dqdqsrcvcntrl and csrvrefinglobal to select Global VREF + * from Master to be used in each DQ + * - Fields: + * - selanalogvref + * - majormodedbyte + * - ExtVrefRange + * - DfeCtrl + * - GainCurrAdj + * - Dependencies: + * - user_input_basic.numdbyte + */ +static void vrefinglobal_program(struct stm32mp_ddr_config *config, + struct pmu_smb_ddr_1d *mb_ddr_1d) +{ + uint32_t majormodedbyte; + int32_t vref_percentvddq = (int32_t)mb_ddr_1d->phyvref * 1000 * 100 / 128; + uint8_t globalvrefindac = 0x0U; + uint8_t globalvrefinsel = 0x4U; + uint32_t byte; + uint32_t dfectrl_defval = 0U; + uint32_t extvrefrange_defval = 0U; + uint32_t gaincurradj_defval = 0xBU; + uint32_t selanalogvref = 1U; /* Use Global VREF from Master */ + uint16_t dqdqsrcvcntrl; + uint16_t vrefinglobal; + +#if STM32MP_DDR3_TYPE + majormodedbyte = 0U; +#elif STM32MP_DDR4_TYPE + majormodedbyte = 3U; +#else /* STM32MP_LPDDR4_TYPE */ + majormodedbyte = 2U; +#endif /* STM32MP_DDR3_TYPE */ + + /* Check range1 first. Only use range0 if customer input maxes out range1. */ + globalvrefindac = (uint8_t)((vref_percentvddq / 500) + 1); + if (globalvrefindac > 127U) { + /* Min value is 1 */ + globalvrefindac = (uint8_t)(MAX((vref_percentvddq - 34500), 500) / 500); + globalvrefinsel = 0x0U; + } + globalvrefindac = MIN(globalvrefindac, (uint8_t)127); + + vrefinglobal = (uint16_t)((globalvrefindac << CSR_GLOBALVREFINDAC_LSB) | globalvrefinsel); + mmio_write_16((uintptr_t)(DDRPHYC_BASE + (4U * (TMASTER | CSR_VREFINGLOBAL_ADDR))), + vrefinglobal); + + dqdqsrcvcntrl = (uint16_t)((gaincurradj_defval << CSR_GAINCURRADJ_LSB) | + (majormodedbyte << CSR_MAJORMODEDBYTE_LSB) | + (dfectrl_defval << CSR_DFECTRL_LSB) | + (extvrefrange_defval << CSR_EXTVREFRANGE_LSB) | + (selanalogvref << CSR_SELANALOGVREF_LSB)); + + for (byte = 0U; byte < config->uib.numdbyte; byte++) { + uint32_t c_addr; + uint32_t lane; + + c_addr = byte << 12; + for (lane = 0U; lane <= B_MAX; lane++) { + uint32_t b_addr; + + b_addr = lane << 8; + mmio_write_16((uintptr_t)(DDRPHYC_BASE + (4U * (TDBYTE | c_addr | b_addr | + CSR_DQDQSRCVCNTRL_ADDR))), + dqdqsrcvcntrl); + } + } +} + +/* + * Program dfifreqratio : + * - Dependencies: + * - user_input_basic.dfifreqratio + */ +static void dfifreqratio_program(struct stm32mp_ddr_config *config) +{ + uint16_t dfifreqratio; + + dfifreqratio = (uint16_t)config->uib.dfifreqratio; + + mmio_write_16((uintptr_t)(DDRPHYC_BASE + (4U * (TMASTER | CSR_DFIFREQRATIO_ADDR))), + dfifreqratio); +} + +/* + * Program tristatemodeca based on dramtype and 2T Timing + * - Fields: + * - CkDisVal + * - disdynadrtri + * - ddr2tmode + * - Dependencies: + * - user_input_advanced.is2ttiming + * - user_input_advanced.disdynadrtri + */ +static void tristatemodeca_program(struct stm32mp_ddr_config *config) +{ + uint32_t ckdisval_def; + uint32_t ddr2tmode; + uint32_t disdynadrtri; + uint16_t tristatemodeca; + + /* CkDisVal depends on dramtype */ +#if STM32MP_DDR3_TYPE || STM32MP_DDR4_TYPE + ckdisval_def = 1U; /* {CLK_t,CLK_c} = 2'b00; */ +#else /* STM32MP_LPDDR4_TYPE */ + ckdisval_def = 0U; /* {CLK_t,CLK_c} = 2'b01; */ +#endif /* STM32MP_DDR3_TYPE || STM32MP_DDR4_TYPE */ + +#if STM32MP_DDR3_TYPE || STM32MP_DDR4_TYPE + disdynadrtri = config->uia.disdynadrtri; +#else /* STM32MP_LPDDR4_TYPE */ + disdynadrtri = 1U; +#endif /* STM32MP_DDR3_TYPE || STM32MP_DDR4_TYPE */ + + ddr2tmode = config->uia.is2ttiming; + + tristatemodeca = (uint16_t)((ckdisval_def << CSR_CKDISVAL_LSB) | + (ddr2tmode << CSR_DDR2TMODE_LSB) | + (disdynadrtri << CSR_DISDYNADRTRI_LSB)); + + mmio_write_16((uintptr_t)(DDRPHYC_BASE + (4U * (TMASTER | CSR_TRISTATEMODECA_ADDR))), + tristatemodeca); +} + +/* + * Program DfiXlat based on Pll Bypass Input + * - Dependencies: + * - user_input_basic.frequency + * - user_input_basic.pllbypass + */ +static void dfixlat_program(struct stm32mp_ddr_config *config) +{ + uint16_t loopvector; + uint16_t pllbypass_dat = 0U; + uint16_t skipddc_dat = 0U; /* + * Set to vector offset based on frequency to disable dram + * drift compensation. + */ + + pllbypass_dat |= (uint16_t)config->uib.pllbypass; + + if (config->uib.frequency < 333U) { + skipddc_dat |= 0x5U; + } + + for (loopvector = 0U; loopvector < 8U; loopvector++) { + uint16_t dfifreqxlat_dat; + uintptr_t reg = (uintptr_t)(DDRPHYC_BASE + (4U * (C0 | TMASTER | + (CSR_DFIFREQXLAT0_ADDR + + loopvector)))); + +#if STM32MP_DDR3_TYPE || STM32MP_DDR4_TYPE + if (loopvector == 0U) { + /* + * Relock DfiFreq = 00,01,02,03) Use StartVec 5 (pll_enabled) or + * StartVec 6 (pll_bypassed). + */ + dfifreqxlat_dat = pllbypass_dat + 0x5555U; + + mmio_write_16(reg, dfifreqxlat_dat); + } else if (loopvector == 7U) { + /* LP3-entry DfiFreq = 1F */ + mmio_write_16(reg, 0xF000U); + } else { + /* + * Everything else = skip retrain (could also map to 0000 since retrain + * code is excluded, but this is cleaner). + */ + mmio_write_16(reg, 0x5555U); + } +#else /* STM32MP_LPDDR4_TYPE */ + if (loopvector == 0U) { + /* + * Retrain & Relock DfiFreq = 00,01,02,03) Use StartVec 0 (pll_enabled) or + * StartVec 1 (pll_bypassed). + */ + dfifreqxlat_dat = pllbypass_dat + skipddc_dat; + mmio_write_16(reg, dfifreqxlat_dat); + } else if (loopvector == 2U) { + /* + * Retrain only DfiFreq = 08,09,0A,0B) Use StartVec 4 (1, and maybe 2,3, + * used by verif). + */ + mmio_write_16(reg, 0x4444U); + } else if (loopvector == 3U) { + /* Phymstr type state change, StartVec 8 */ + mmio_write_16(reg, 0x8888U); + } else if (loopvector == 4U) { + /* + * Relock only DfiFreq = 10,11,12,13 Use StartVec 5 (pll_enabled) or + * StartVec 6 (pll_bypassed). + */ + dfifreqxlat_dat = pllbypass_dat + 0x5555U; + mmio_write_16(reg, dfifreqxlat_dat); + } else if (loopvector == 7U) { + /* LP3-entry DfiFreq = 1F */ + mmio_write_16(reg, 0xF000U); + } else { + /* Everything else */ + mmio_write_16(reg, 0x0000U); + } +#endif /* STM32MP_DDR3_TYPE || STM32MP_DDR4_TYPE */ + } +} + +/* + * Program dqdqsrcvcntrl1 (Receiver Powerdown) and DbyteMiscMode + * - see function ddrphy_phyinit_isdbytedisabled() to determine + * which DBytes are turned off completely based on PHY configuration. + * - Fields: + * - DByteDisable + * - PowerDownRcvr + * - PowerDownRcvrDqs + * - RxPadStandbyEn + * - Dependencies: + * - user_input_basic.numdbyte + * - user_input_basic.dramdatawidth (DDR3/DDR4) + * - mb_ddr_1d->mr5 (DDR4) + * - user_input_advanced.lp4dbird (LPDDR4) + */ +static void dqdqsrcvcntrl1_program(struct stm32mp_ddr_config *config, + struct pmu_smb_ddr_1d *mb_ddr_1d) +{ + uint32_t d; + uint16_t mr5 __maybe_unused; + uint16_t regdata; + uint16_t regdata1; + uint16_t regdata2; /* Turn off Rx of DBI lane */ + + regdata = 0x1U << CSR_DBYTEDISABLE_LSB; + + regdata1 = (0x1FFU << CSR_POWERDOWNRCVR_LSB) | + (0x1U << CSR_POWERDOWNRCVRDQS_LSB) | + (0x1U << CSR_RXPADSTANDBYEN_LSB); + + regdata2 = (0x100U << CSR_POWERDOWNRCVR_LSB) | CSR_RXPADSTANDBYEN_MASK; + +#if STM32MP_DDR4_TYPE + /* OR all mr4 masked values, to help check in next loop */ + mr5 = (mb_ddr_1d->mr5 >> 12) & 0x1U; +#endif /* STM32MP_DDR4_TYPE */ + + for (d = 0U; d < config->uib.numdbyte; d++) { + uint32_t c_addr; + + c_addr = d * C1; + if (ddrphy_phyinit_isdbytedisabled(config, mb_ddr_1d, d) != 0) { + mmio_write_16((uintptr_t)(DDRPHYC_BASE + (4U * (c_addr | TDBYTE | + CSR_DBYTEMISCMODE_ADDR))), + regdata); + mmio_write_16((uintptr_t)(DDRPHYC_BASE + (4U * (c_addr | TDBYTE | + CSR_DQDQSRCVCNTRL1_ADDR))), + regdata1); + } else { + /* Disable RDBI lane if not used. */ +#if STM32MP_DDR3_TYPE + if (config->uib.dramdatawidth != 4U) { +#elif STM32MP_DDR4_TYPE + if ((config->uib.dramdatawidth != 4U) && (mr5 == 0U)) { +#else /* STM32MP_LPDDR4_TYPE */ + if (config->uia.lp4dbird == 0U) { +#endif /* STM32MP_DDR3_TYPE */ + mmio_write_16((uintptr_t) + (DDRPHYC_BASE + (4U * (c_addr | TDBYTE | + CSR_DQDQSRCVCNTRL1_ADDR))), + regdata2); + } + } + } +} + +/* + * Program masterx4config + * - Fields: + * - x4tg + * - masterx4config + * - Dependencies: + * - user_input_basic.dramdatawidth + * + * \note PHY does not support mixed dram device data width + */ +static void masterx4config_program(struct stm32mp_ddr_config *config) +{ + uint32_t x4tg = 0U; + uint16_t masterx4config; + + if (config->uib.dramdatawidth == 4U) { + x4tg = 0xFU; + } + + masterx4config = (uint16_t)(x4tg << CSR_X4TG_LSB); + + mmio_write_16((uintptr_t)(DDRPHYC_BASE + (4U * (TMASTER | CSR_MASTERX4CONFIG_ADDR))), + masterx4config); +} + +#if !STM32MP_DDR3_TYPE +/* + * Program dmipinpresent based on dramtype and Read-DBI enable + * - Fields: + * - RdDbiEnabled + * - Dependencies: + * - mb_ddr_1d->mr5 (DDR4) + * - user_input_advanced.lp4dbird (LPDDR4) + */ +static void dmipinpresent_program(struct stm32mp_ddr_config *config, + struct pmu_smb_ddr_1d *mb_ddr_1d) +{ + uint16_t dmipinpresent; + +#if STM32MP_DDR4_TYPE + /* For DDR4, Read DBI is enabled in mr5-A12 */ + dmipinpresent = (mb_ddr_1d->mr5 >> 12) & 0x1U; +#else /* STM32MP_LPDDR4_TYPE */ + dmipinpresent = (uint16_t)config->uia.lp4dbird; +#endif /* STM32MP_DDR4_TYPE */ + + mmio_write_16((uintptr_t)(DDRPHYC_BASE + (4U * (TMASTER | CSR_DMIPINPRESENT_ADDR))), + dmipinpresent); +} +#endif /* !STM32MP_DDR3_TYPE */ + +/* + * Program aforcetricont and acx4anibdis + * - Fields: + * - aforcetricont + * - acx4anibdis + * - Dependencies: + * - user_input_basic.numrank_dfi0 + * - user_input_basic.numrank_dfi1 + * - user_input_basic.numanib + * - user_input_advanced.disableunusedaddrlns + */ +static void aforcetricont_acx4anibdis_program(struct stm32mp_ddr_config *config) +{ + uint32_t anib; + uint16_t acx4anibdis = 0x0U; + + for (anib = 0U; (anib < config->uib.numanib) && (config->uia.disableunusedaddrlns != 0U); + anib++) { + uint32_t c_addr; +#if STM32MP_DDR3_TYPE || STM32MP_DDR4_TYPE + uint32_t numrank = config->uib.numrank_dfi0 + config->uib.numrank_dfi1; +#else /* STM32MP_LPDDR4_TYPE */ + uint32_t numrank0 = config->uib.numrank_dfi0; + uint32_t numrank1 = config->uib.numrank_dfi1; +#endif /* STM32MP_DDR3_TYPE || STM32MP_DDR4_TYPE */ + uint16_t aforcetricont = 0x0U; + + c_addr = anib << 12; + +#if STM32MP_DDR3_TYPE || STM32MP_DDR4_TYPE + if ((anib == 0U) && (numrank == 1U)) { + aforcetricont = 0x2U; + } else if ((anib == 1U) && (numrank == 1U)) { + aforcetricont = 0xCU; + } else if (anib == 6U) { + aforcetricont = 0x1U; + } +#else /* STM32MP_LPDDR4_TYPE */ + if ((anib == 0U) && (numrank0 == 0U)) { + aforcetricont = 0xFU; + } else if ((anib == 0U) && (numrank0 == 1U)) { + aforcetricont = 0x2U; + } else if ((anib == 1U) && (numrank0 == 0U)) { + aforcetricont = 0xFU; + } else if ((anib == 1U) && (numrank0 == 1U)) { + aforcetricont = 0x8U; + } else if ((anib == 2U) && (numrank0 == 0U)) { + aforcetricont = 0xFU; + } else if ((anib == 3U) && (numrank1 == 0U)) { + aforcetricont = 0xFU; + } else if ((anib == 3U) && (numrank1 == 1U)) { + aforcetricont = 0x2U; + } else if ((anib == 4U) && (numrank1 == 0U)) { + aforcetricont = 0xFU; + } else if ((anib == 4U) && (numrank1 == 1U)) { + aforcetricont = 0x8U; + } else if ((anib == 5U) && (numrank1 == 0U)) { + aforcetricont = 0xFU; + } else if (anib == 6U) { + aforcetricont = 0xFU; + } else if (anib == 7U) { + aforcetricont = 0xFU; + } +#endif /* STM32MP_DDR3_TYPE || STM32MP_DDR4_TYPE */ + + /* + * If all the lanes can be disabled, and Anib is not the first or last disable + * entire chiplet + */ + if ((aforcetricont == 0xFU) && (anib != 0U) && + (anib != (config->uib.numanib - 1U))) { + acx4anibdis = acx4anibdis | (0x1U << anib); + } + mmio_write_16((uintptr_t)(DDRPHYC_BASE + (4U * (TANIB | c_addr | + CSR_AFORCETRICONT_ADDR))), + aforcetricont); + } + + mmio_write_16((uintptr_t)(DDRPHYC_BASE + (4U * (TMASTER | CSR_ACX4ANIBDIS_ADDR))), + acx4anibdis); +} + +/* + * Implements Step C of initialization sequence + * + * This function programs majority of PHY configuration registers based + * on data input into PhyInit data structures. + * + * This function programs PHY configuration registers based on information + * provided in the PhyInit data structures (config->uib, config->uia). + * The user can overwrite the programming of this function by modifying + * ddrphy_phyinit_usercustom_custompretrain(). Please see + * ddrphy_phyinit_struct.h for PhyInit data structure definition. + * + * \return 0 on success. + */ +int ddrphy_phyinit_c_initphyconfig(struct stm32mp_ddr_config *config, + struct pmu_smb_ddr_1d *mb_ddr_1d, uint32_t *ardptrinitval) +{ + uint32_t twotckrxdqspre; + int ret; + + /* + * Step (C) Initialize PHY Configuration + * Load the required PHY configuration registers for the appropriate mode and memory + * configuration. + */ + + txslewrate_program(config); + + atxslewrate_program(config); + +#if STM32MP_DDR3_TYPE || STM32MP_DDR4_TYPE + dfidatacsdestmap_program(mb_ddr_1d); +#endif /* STM32MP_DDR3_TYPE || STM32MP_DDR4_TYPE */ + + pllctrl2_program(config); + + ardptrinitval_program(config, ardptrinitval); + +#if STM32MP_LPDDR4_TYPE + procodtctl_program(); +#endif /* STM32MP_LPDDR4_TYPE */ + + dbytedllmodecntrl_program(config, &twotckrxdqspre); + + procodttimectl_program(config, twotckrxdqspre); + + ret = txodtdrvstren_program(config); + if (ret != 0) { + return ret; + } + + ret = tximpedancectrl1_program(config); + if (ret != 0) { + return ret; + } + + ret = atximpedance_program(config); + if (ret != 0) { + return ret; + } + + dfimode_program(config); + + dficamode_program(); + + caldrvstr0_program(config); + + caluclkinfo_program(config); + + calibration_program(config); + + vrefinglobal_program(config, mb_ddr_1d); + + dfifreqratio_program(config); + + tristatemodeca_program(config); + + dfixlat_program(config); + + dqdqsrcvcntrl1_program(config, mb_ddr_1d); + + masterx4config_program(config); + +#if !STM32MP_DDR3_TYPE + dmipinpresent_program(config, mb_ddr_1d); + +#if STM32MP_LPDDR4_TYPE + /* + * Program DFIPHYUPD + * - Fields: + * - DFIPHYUPDMODE + * - DFIPHYUPDCNT + * - Dependencies: + * - user_input_advanced.disablephyupdate + */ + if (config->uia.disablephyupdate != 0U) { + mmio_write_16((uintptr_t)(DDRPHYC_BASE + (4U * (TMASTER | CSR_DFIPHYUPD_ADDR))), + 0x0U); + } +#endif /* STM32MP_LPDDR4_TYPE */ +#endif /* !STM32MP_DDR3_TYPE */ + + aforcetricont_acx4anibdis_program(config); + + return 0; +} diff --git a/drivers/st/ddr/phy/phyinit/src/ddrphy_phyinit_calcmb.c b/drivers/st/ddr/phy/phyinit/src/ddrphy_phyinit_calcmb.c new file mode 100644 index 000000000..c5fa5f1ba --- /dev/null +++ b/drivers/st/ddr/phy/phyinit/src/ddrphy_phyinit_calcmb.c @@ -0,0 +1,210 @@ +/* + * Copyright (C) 2021-2024, STMicroelectronics - All Rights Reserved + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include + +#include + +#include + +/* + * Reads PhyInit inputs structures and sets relevant message block + * parameters. + * + * This function sets Message Block parameters based on user_input_basic and + * user_input_advanced. user changes in these files takes precedence + * over this function call. + * + * MessageBlock fields set : + * - dramtype + * - pstate + * - dramfreq + * - pllbypassen + * - dfifreqratio + * - phyodtimpedance + * - phydrvimpedance + * - bpznresval + * - enableddqscha (LPDDR4) + * - cspresentcha (LPDDR4) + * - enableddqsChb (LPDDR4) + * - cspresentchb (LPDDR4) + * - enableddqs (DDR3/DDR4) + * - phycfg (DDR3/DDR4) + * - x16present (DDR4) + * + * \return 0 on success. + */ +int ddrphy_phyinit_calcmb(struct stm32mp_ddr_config *config, struct pmu_smb_ddr_1d *mb_ddr_1d) +{ + uint32_t nad0 = config->uib.numactivedbytedfi0; + uint32_t nad1 = 0; + uint16_t mr4 __maybe_unused; + uint16_t disableddbyte __maybe_unused; + uint32_t dbyte __maybe_unused; + int ret; + +#if STM32MP_LPDDR4_TYPE + nad1 = config->uib.numactivedbytedfi1; +#endif /* STM32MP_LPDDR4_TYPE */ + + /* A few checks to make sure valid programming */ + if ((nad0 == 0U) || (config->uib.numdbyte == 0U)) { + ERROR("%s %d\n", __func__, __LINE__); + VERBOSE("%s numactivedbytedfi0, numactivedbytedfi0, NumByte out of range.\n", + __func__); + return -1; + } + + if ((nad0 + nad1) > config->uib.numdbyte) { + ERROR("%s %d\n", __func__, __LINE__); + VERBOSE("%s numactivedbytedfi0+numactivedbytedfi1 is larger than numdbyteDfi0\n", + __func__); + return -1; + } + + if ((config->uib.dfi1exists == 0U) && (nad1 != 0U)) { + ERROR("%s %d\n", __func__, __LINE__); + VERBOSE("%s dfi1exists==0 but numdbyteDfi0 != 0\n", __func__); + return -1; + } + +#if STM32MP_DDR4_TYPE + /* OR all mr4 masked values, to help check in next loop */ + mr4 = mb_ddr_1d->mr4 & 0x1C0U; + + /* 1D message block defaults */ + if (mr4 != 0x0U) { + ERROR("mr4 != 0x0\n"); + VERBOSE("%s Setting DRAM CAL mode is not supported by the PHY.\n", __func__); + VERBOSE("Memory controller may set CAL mode after PHY has entered mission\n"); + VERBOSE("mode. Please check value programmed in mb_ddr_1d[*].mr4\n"); + VERBOSE("and unset A8:6\n"); + return -1; + } +#endif /* STM32MP_DDR4_TYPE */ + +#if STM32MP_DDR3_TYPE + if (config->uib.dimmtype == DDR_DIMMTYPE_NODIMM) { + ret = ddrphy_phyinit_softsetmb(mb_ddr_1d, MB_FIELD_DRAMTYPE, 0x1U); + if (ret != 0) { + return ret; + } + } +#elif STM32MP_DDR4_TYPE + if (config->uib.dimmtype == DDR_DIMMTYPE_NODIMM) { + ret = ddrphy_phyinit_softsetmb(mb_ddr_1d, MB_FIELD_DRAMTYPE, 0x2U); + if (ret != 0) { + return ret; + } + } +#else /* STM32MP_LPDDR4_TYPE */ + /* Nothing to do */ +#endif /* STM32MP_DDR3_TYPE */ + + ret = ddrphy_phyinit_softsetmb(mb_ddr_1d, MB_FIELD_PSTATE, 0U); + if (ret != 0) { + return ret; + } + + ret = ddrphy_phyinit_softsetmb(mb_ddr_1d, MB_FIELD_DRAMFREQ, config->uib.frequency * 2U); + if (ret != 0) { + return ret; + } + + ret = ddrphy_phyinit_softsetmb(mb_ddr_1d, MB_FIELD_PLLBYPASSEN, config->uib.pllbypass); + if (ret != 0) { + return ret; + } + + if (config->uib.dfifreqratio == 1U) { + ret = ddrphy_phyinit_softsetmb(mb_ddr_1d, MB_FIELD_DFIFREQRATIO, 0x2U); + if (ret != 0) { + return ret; + } + } + + ret = ddrphy_phyinit_softsetmb(mb_ddr_1d, MB_FIELD_PHYODTIMPEDANCE, 0U); + if (ret != 0) { + return ret; + } + + ret = ddrphy_phyinit_softsetmb(mb_ddr_1d, MB_FIELD_PHYDRVIMPEDANCE, 0U); + if (ret != 0) { + return ret; + } + + ret = ddrphy_phyinit_softsetmb(mb_ddr_1d, MB_FIELD_BPZNRESVAL, 0U); + if (ret != 0) { + return ret; + } + +#if STM32MP_DDR3_TYPE || STM32MP_DDR4_TYPE + ret = ddrphy_phyinit_softsetmb(mb_ddr_1d, MB_FIELD_ENABLEDDQS, nad0 * 8U); + if (ret != 0) { + return ret; + } + + disableddbyte = 0x0U; + + for (dbyte = 0U; (dbyte < config->uib.numdbyte) && (dbyte < 8U); dbyte++) { + if (ddrphy_phyinit_isdbytedisabled(config, mb_ddr_1d, dbyte) != 0) { + disableddbyte |= 0x1U << dbyte; + } + } + + ret = ddrphy_phyinit_softsetmb(mb_ddr_1d, MB_FIELD_DISABLEDDBYTE, disableddbyte); + if (ret != 0) { + return ret; + } + +#if STM32MP_DDR3_TYPE + ret = ddrphy_phyinit_softsetmb(mb_ddr_1d, MB_FIELD_PHYCFG, config->uia.is2ttiming); + if (ret != 0) { + return ret; + } +#else /* STM32MP_DDR4_TYPE */ + ret = ddrphy_phyinit_softsetmb(mb_ddr_1d, MB_FIELD_PHYCFG, + ((mb_ddr_1d->mr3 & 0x8U) != 0U) ? + 0U : config->uia.is2ttiming); + if (ret != 0) { + return ret; + } + + ret = ddrphy_phyinit_softsetmb(mb_ddr_1d, MB_FIELD_X16PRESENT, + (config->uib.dramdatawidth == 0x10U) ? + mb_ddr_1d->cspresent : 0x0U); + if (ret != 0) { + return ret; + } +#endif /* STM32MP_DDR3_TYPE */ +#else /* STM32MP_LPDDR4_TYPE */ + ret = ddrphy_phyinit_softsetmb(mb_ddr_1d, MB_FIELD_ENABLEDDQSCHA, nad0 * 8U); + if (ret != 0) { + return ret; + } + + ret = ddrphy_phyinit_softsetmb(mb_ddr_1d, MB_FIELD_CSPRESENTCHA, + (config->uib.numrank_dfi0 == 2U) ? + 0x3U : config->uib.numrank_dfi0); + if (ret != 0) { + return ret; + } + + ret = ddrphy_phyinit_softsetmb(mb_ddr_1d, MB_FIELD_ENABLEDDQSCHB, nad1 * 8U); + if (ret != 0) { + return ret; + } + + ret = ddrphy_phyinit_softsetmb(mb_ddr_1d, MB_FIELD_CSPRESENTCHB, + (config->uib.numrank_dfi1 == 2U) ? + 0x3U : config->uib.numrank_dfi1); + if (ret != 0) { + return ret; + } +#endif /* STM32MP_DDR3_TYPE || STM32MP_DDR4_TYPE */ + + return 0; +} diff --git a/drivers/st/ddr/phy/phyinit/src/ddrphy_phyinit_d_loadimem.c b/drivers/st/ddr/phy/phyinit/src/ddrphy_phyinit_d_loadimem.c new file mode 100644 index 000000000..8bec30ba3 --- /dev/null +++ b/drivers/st/ddr/phy/phyinit/src/ddrphy_phyinit_d_loadimem.c @@ -0,0 +1,43 @@ +/* + * Copyright (C) 2021-2024, STMicroelectronics - All Rights Reserved + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include +#include + +#include + +#include + +#include + +#include + +/* + * This function loads the training firmware IMEM image into the PHY. + * + * This function reads the DDR firmware source memory area to generate a + * set of apb writes to load IMEM image into the PHY. The exact steps in this + * function are as follows: + * + * -# Ensure DRAM is in reset. + * -# Load the microcontroller memory with the provided training firmware + * -# Initialize the firmware mailbox structures to be able to communicate with + * the firmware. + * + * \return void + */ +void ddrphy_phyinit_d_loadimem(void) +{ + uint16_t memresetl; + uint32_t *ptr32; + + /* Set memresetl to avoid glitch on BP_MemReset_L during training */ + memresetl = CSR_PROTECTMEMRESET_MASK; + mmio_write_16((uintptr_t)(DDRPHYC_BASE + (4U * (TMASTER | CSR_MEMRESETL_ADDR))), memresetl); + + ptr32 = (uint32_t *)(STM32MP_DDR_FW_BASE + STM32MP_DDR_FW_IMEM_OFFSET); + ddrphy_phyinit_writeoutmem(ptr32, IMEM_ST_ADDR, IMEM_SIZE); +} diff --git a/drivers/st/ddr/phy/phyinit/src/ddrphy_phyinit_f_loaddmem.c b/drivers/st/ddr/phy/phyinit/src/ddrphy_phyinit_f_loaddmem.c new file mode 100644 index 000000000..3c6c87f45 --- /dev/null +++ b/drivers/st/ddr/phy/phyinit/src/ddrphy_phyinit_f_loaddmem.c @@ -0,0 +1,70 @@ +/* + * Copyright (C) 2021-2024, STMicroelectronics - All Rights Reserved + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include +#include + +#include + +#include + +#include + +/* + * This function loads the training firmware DMEM image and write the + * Message Block parameters for the training firmware into the PHY. + * + * This function performs the following tasks: + * + * -# Load the firmware DMEM segment to initialize the data structures from the + * DDR firmware source memory area. + * -# Write the Firmware Message Block with the required contents detailing the training parameters. + * + * \return 0 on success. + */ +int ddrphy_phyinit_f_loaddmem(struct stm32mp_ddr_config *config, struct pmu_smb_ddr_1d *mb_ddr_1d) +{ + uint32_t sizeofmsgblk; + uint16_t *ptr16; + uint32_t *ptr32; + + /* Some basic checks on MessageBlock */ +#if STM32MP_DDR3_TYPE || STM32MP_DDR4_TYPE + if ((mb_ddr_1d->enableddqs > (8U * (uint8_t)config->uib.numactivedbytedfi0)) || + (mb_ddr_1d->enableddqs <= 0U)) { + ERROR("%s %d\n", __func__, __LINE__); + VERBOSE("%s enableddqs is Zero or greater than NumActiveDbytes for Dfi0\n", + __func__); + return -1; + } +#else /* STM32MP_LPDDR4_TYPE */ + if (((mb_ddr_1d->enableddqscha % 16U) != 0U) || ((mb_ddr_1d->enableddqschb % 16U) != 0U)) { + ERROR("%s %d\n", __func__, __LINE__); + VERBOSE("%s Lp3/Lp4 - Number of Dq's Enabled per Channel much be multipe of 16\n", + __func__); + return -1; + } + + if ((mb_ddr_1d->enableddqscha > (uint8_t)(8U * config->uib.numactivedbytedfi0)) || + (mb_ddr_1d->enableddqschb > (uint8_t)(8U * config->uib.numactivedbytedfi1)) || + ((mb_ddr_1d->enableddqscha == 0U) && (mb_ddr_1d->enableddqschb == 0U))) { + ERROR("%s %d\n", __func__, __LINE__); + VERBOSE("%s EnabledDqsChA/B are not set correctly./1\n", __func__); + return -1; + } +#endif /* STM32MP_DDR3_TYPE || STM32MP_DDR4_TYPE */ + + sizeofmsgblk = sizeof(struct pmu_smb_ddr_1d); + + ptr16 = (uint16_t *)mb_ddr_1d; + ddrphy_phyinit_writeoutmsgblk(ptr16, DMEM_ST_ADDR, sizeofmsgblk); + + ptr32 = (uint32_t *)(STM32MP_DDR_FW_BASE + STM32MP_DDR_FW_DMEM_OFFSET); + ddrphy_phyinit_writeoutmem(ptr32, DMEM_ST_ADDR + DMEM_BIN_OFFSET, + DMEM_SIZE - STM32MP_DDR_FW_DMEM_OFFSET); + + return 0; +} diff --git a/drivers/st/ddr/phy/phyinit/src/ddrphy_phyinit_g_execfw.c b/drivers/st/ddr/phy/phyinit/src/ddrphy_phyinit_g_execfw.c new file mode 100644 index 000000000..0c11594b2 --- /dev/null +++ b/drivers/st/ddr/phy/phyinit/src/ddrphy_phyinit_g_execfw.c @@ -0,0 +1,66 @@ +/* + * Copyright (C) 2021-2024, STMicroelectronics - All Rights Reserved + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include + +#include + +#include + +#include + +/* + * Execute the Training Firmware + * + * The training firmware is executed with the procedure: + * + * -# Reset the firmware microcontroller by writing the MicroReset register to + * set the StallToMicro and ResetToMicro fields to 1 (all other fields should be + * zero). Then rewrite the registers so that only the StallToMicro remains set + * (all other fields should be zero). + * -# Begin execution of the training firmware by setting the MicroReset + * register to 0. + * -# Wait for the training firmware to complete by following the procedure implemented in + * ddrphy_phyinit_usercustom_g_waitfwdone() function. + * -# Halt the microcontroller. + * + * \return 0 on success. + */ +int ddrphy_phyinit_g_execfw(void) +{ + int ret; + + /* + * 1. Reset the firmware microcontroller by writing the MicroReset CSR to set the + * StallToMicro and ResetToMicro fields to 1 (all other fields should be zero). + * Then rewrite the CSR so that only the StallToMicro remains set (all other fields should + * be zero). + */ + mmio_write_16((uintptr_t)(DDRPHYC_BASE + (4U * (TAPBONLY | CSR_MICROCONTMUXSEL_ADDR))), + CSR_STALLTOMICRO_MASK); + mmio_write_16((uintptr_t)(DDRPHYC_BASE + (4U * (TAPBONLY | CSR_MICRORESET_ADDR))), + CSR_RESETTOMICRO_MASK | CSR_STALLTOMICRO_MASK); + mmio_write_16((uintptr_t)(DDRPHYC_BASE + (4U * (TAPBONLY | CSR_MICRORESET_ADDR))), + CSR_STALLTOMICRO_MASK); + + /* 2. Begin execution of the training firmware by setting the MicroReset CSR to 0 */ + mmio_write_16((uintptr_t)(DDRPHYC_BASE + (4U * (TAPBONLY | CSR_MICRORESET_ADDR))), 0x0U); + + /* + * 3. Wait for the training firmware to complete by following the procedure + * implemented in ddrphy_phyinit_usercustom_g_waitfwdone() function. + */ + ret = ddrphy_phyinit_usercustom_g_waitfwdone(); + if (ret != 0) { + return ret; + } + + /* 4. Halt the microcontroller */ + mmio_write_16((uintptr_t)(DDRPHYC_BASE + (4U * (TAPBONLY | CSR_MICRORESET_ADDR))), + CSR_STALLTOMICRO_MASK); + + return 0; +} diff --git a/drivers/st/ddr/phy/phyinit/src/ddrphy_phyinit_i_loadpieimage.c b/drivers/st/ddr/phy/phyinit/src/ddrphy_phyinit_i_loadpieimage.c new file mode 100644 index 000000000..6ca0ddcd6 --- /dev/null +++ b/drivers/st/ddr/phy/phyinit/src/ddrphy_phyinit_i_loadpieimage.c @@ -0,0 +1,394 @@ +/* + * Copyright (C) 2021-2024, STMicroelectronics - All Rights Reserved + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include + +#include + +#include + +#include + +#include + +#if STM32MP_LPDDR4_TYPE +/* + * Program DfiWrRdDataCsConfig + * - Fields: + * - dfiwrdatacspolarity + * - dfirddatacspolarity + */ +static void dfiwrrddatacsconfig_program(void) +{ + uint16_t dfiwrdatacspolarity; + uint16_t dfirddatacspolarity; + + /* + * DfiWrRdDataCsConfig : dfiwrdatacspolarity=0x1 and dfirddatacspolarity=0x1. + * Set DataCsPolarity bits to enable active high + */ + dfiwrdatacspolarity = 0x1U; + dfirddatacspolarity = 0x1U; + + mmio_write_16((uintptr_t)(DDRPHYC_BASE + (4U * (TMASTER | C0 | + CSR_DFIWRRDDATACSCONFIG_ADDR))), + (dfiwrdatacspolarity << CSR_DFIWRDATACSPOLARITY_LSB) | + (dfirddatacspolarity << CSR_DFIRDDATACSPOLARITY_LSB)); +} +#endif /* STM32MP_LPDDR4_TYPE */ + +/* + * Registers: Seq0BDLY0, Seq0BDLY1, Seq0BDLY2, Seq0BDLY3 + * - Program PIE instruction delays + * - Dependencies: + * - user_input_basic.frequency + */ +static void seq0bdly_program(struct stm32mp_ddr_config *config) +{ + uint16_t lowfreqopt __unused; + uint16_t dfifrq_x10; + uint16_t pscount_ref; + uint16_t pscount[4]; /* Need delays for 0.5us, 1us, 10us, and 25us */ + + /* + * Calculate the counts to obtain the correct delay for each frequency + * Need to divide by 4 since the delay value are specified in units of + * 4 clocks. + */ + dfifrq_x10 = (10U * (uint16_t)config->uib.frequency) / 2U; + pscount_ref = dfifrq_x10 / 4U; + pscount[0] = pscount_ref / (2U * 10U); + +#if STM32MP_DDR3_TYPE || STM32MP_DDR4_TYPE + if (config->uib.frequency < 400U) { + lowfreqopt = 3U; + } else if (config->uib.frequency < 533U) { + lowfreqopt = 11U; + } else { + lowfreqopt = 0U; + } + + pscount[1] = (pscount_ref / 10U) - lowfreqopt; +#else /* STM32MP_LPDDR4_TYPE */ + pscount[1] = pscount_ref / 10U; +#endif /* STM32MP_DDR3_TYPE || STM32MP_DDR4_TYPE */ + pscount[2] = pscount_ref; + + if (dfifrq_x10 > 2665U) { + pscount[3] = 44U; + } else if ((dfifrq_x10 <= 2665U) && (dfifrq_x10 > 2000U)) { + pscount[3] = 33U; + } else { + pscount[3] = 16U; + } + + mmio_write_16((uintptr_t)(DDRPHYC_BASE + (4U * (C0 | TMASTER | CSR_SEQ0BDLY0_ADDR))), + pscount[0]); + + mmio_write_16((uintptr_t)(DDRPHYC_BASE + (4U * (C0 | TMASTER | CSR_SEQ0BDLY1_ADDR))), + pscount[1]); + + mmio_write_16((uintptr_t)(DDRPHYC_BASE + (4U * (C0 | TMASTER | CSR_SEQ0BDLY2_ADDR))), + pscount[2]); + + mmio_write_16((uintptr_t)(DDRPHYC_BASE + (4U * (C0 | TMASTER | CSR_SEQ0BDLY3_ADDR))), + pscount[3]); +} + +/* + * Registers: Seq0BDisableFlag0..7 + * - Program PIE Instruction Disable Flags + * - Dependencies: + * - user_input_advanced.DisableRetraining (LPDDR4) + * - skip_training (LPDDR4) + * - user_input_basic.frequency (LPDDR4) + */ +static void seq0bdisableflag_program(struct stm32mp_ddr_config *config, bool skip_training) +{ + mmio_write_16((uintptr_t)(DDRPHYC_BASE + (4U * (TINITENG | CSR_SEQ0BDISABLEFLAG0_ADDR))), + 0x0000U); + mmio_write_16((uintptr_t)(DDRPHYC_BASE + (4U * (TINITENG | CSR_SEQ0BDISABLEFLAG1_ADDR))), + 0x0173U); + mmio_write_16((uintptr_t)(DDRPHYC_BASE + (4U * (TINITENG | CSR_SEQ0BDISABLEFLAG2_ADDR))), + 0x0060U); + mmio_write_16((uintptr_t)(DDRPHYC_BASE + (4U * (TINITENG | CSR_SEQ0BDISABLEFLAG3_ADDR))), + 0x6110U); + mmio_write_16((uintptr_t)(DDRPHYC_BASE + (4U * (TINITENG | CSR_SEQ0BDISABLEFLAG4_ADDR))), + 0x2152U); + mmio_write_16((uintptr_t)(DDRPHYC_BASE + (4U * (TINITENG | CSR_SEQ0BDISABLEFLAG5_ADDR))), + 0xDFBDU); + +#if STM32MP_DDR3_TYPE || STM32MP_DDR4_TYPE + mmio_write_16((uintptr_t)(DDRPHYC_BASE + (4U * (TINITENG | CSR_SEQ0BDISABLEFLAG6_ADDR))), + 0xFFFFU); +#else /* STM32MP_LPDDR4_TYPE */ + if (skip_training || (config->uia.disableretraining != 0U) || + (config->uib.frequency < 333U)) { + /* Disabling DRAM drift compensation */ + mmio_write_16((uintptr_t)(DDRPHYC_BASE + (4U * (TINITENG | + CSR_SEQ0BDISABLEFLAG6_ADDR))), + 0xFFFFU); + } else { + mmio_write_16((uintptr_t)(DDRPHYC_BASE + (4U * (TINITENG | + CSR_SEQ0BDISABLEFLAG6_ADDR))), + 0x2060U); + } +#endif /* STM32MP_DDR3_TYPE || STM32MP_DDR4_TYPE */ + + /* + * - Register: Seq0BGPR7 + * - Program active CSx for MRS7 during D4 RDIMM frequency change + */ + mmio_write_16((uintptr_t)(DDRPHYC_BASE + (4U * (TINITENG | CSR_SEQ0BDISABLEFLAG7_ADDR))), + 0x6152U); +} + +#if STM32MP_LPDDR4_TYPE +/* + * Registers: ppttrainsetup and ppttrainsetup2 + * - Related to DFI PHY Master Interface (PMI). + * - Enable DFI PMI if training firmware was run + * - Fields: + * - PhyMstrTrainInterval + * - PhyMstrMaxReqToAck + * - PhyMstrFreqOverride + * - Dependencies: + * - user_input_basic.frequency + * - user_input_advanced.PhyMstrTrainInterval + * - user_input_advanced.PhyMstrMaxReqToAck + */ +static void ppttrainsetup_program(struct stm32mp_ddr_config *config) +{ + uint16_t ppttrainsetup; + + /* Enabling Phy Master Interface for DRAM drift compensation */ + if (config->uib.frequency >= 333U) { + ppttrainsetup = (uint16_t)((config->uia.phymstrtraininterval << + CSR_PHYMSTRTRAININTERVAL_LSB) | + (config->uia.phymstrmaxreqtoack << + CSR_PHYMSTRMAXREQTOACK_LSB)); + + mmio_write_16((uintptr_t)(DDRPHYC_BASE + (4U * (TMASTER | CSR_PPTTRAINSETUP_ADDR))), + ppttrainsetup); + mmio_write_16((uintptr_t)(DDRPHYC_BASE + (4U * (TMASTER | + CSR_PPTTRAINSETUP2_ADDR))), + 0x0003U); + } +} + +/* + * Registers AcsmPlayback*x* + * - Program Address/Command Sequence Engine (ACSM) registers with + * required instructions for retraining algorithm. + */ +static void acsmplayback_program(void) +{ + uint32_t vec; + + for (vec = 0U; vec < 3U; vec++) { + mmio_write_16((uintptr_t)(DDRPHYC_BASE + (4U * (TACSM | (CSR_ACSMPLAYBACK0X0_ADDR + + (vec * 2U))))), + 0xE0U); + + mmio_write_16((uintptr_t)(DDRPHYC_BASE + (4U * (TACSM | (CSR_ACSMPLAYBACK1X0_ADDR + + (vec * 2U))))), + 0x12U); + } +} + +/* + * Program Training Hardware Registers for mission mode retraining + * and DRAM drift compensation algorithm. + */ +static void traininghwreg_program(struct stm32mp_ddr_config *config) +{ + uint32_t byte; + + /* Programing Training Hardware Registers for mission mode retraining */ + + /* + * - Register: AcsmCtrl13 + * - Fields: AcsmCkeEnb + */ + mmio_write_16((uintptr_t)(DDRPHYC_BASE + (4U * (C0 | TACSM | CSR_ACSMCTRL13_ADDR))), + 0xFU << CSR_ACSMCKEENB_LSB); + + /* + * - Register: AcsmCtrl1 + * - Fields: AcsmRepCnt + * Need 19 iterations @ 0.25ui increments to cover 4.5UI + */ + mmio_write_16((uintptr_t)(DDRPHYC_BASE + (4U * (C0 | TACSM | CSR_ACSMCTRL1_ADDR))), + 0xEU << CSR_ACSMREPCNT_LSB); + + /* + * - Register: TsmByte1, TsmByte2 + * - Dependencies: config->uib.numdbyte + */ + + for (byte = 0U; byte < config->uib.numdbyte; byte++) { + uint32_t c_addr; + uint32_t i_addr; + uint16_t regdata; + uint32_t vec; + + c_addr = byte * C1; + mmio_write_16((uintptr_t)(DDRPHYC_BASE + (4U * (c_addr | TDBYTE | + CSR_TSMBYTE1_ADDR))), + 0x1U); /* [15:8] gstep; [7:0]bstep; */ + mmio_write_16((uintptr_t)(DDRPHYC_BASE + (4U * (c_addr | TDBYTE | + CSR_TSMBYTE2_ADDR))), + 0x1U); /* [15:0] good_bar; */ + + regdata = (CSR_DTSMSTATICCMPR_MASK | CSR_DTSMSTATICCMPRVAL_MASK); + + /* + * - Register: TsmByte3, TsmByte5 + * - Fields: + * - DtsmStaticCmpr + * - DtsmStaticCmprVal + */ + mmio_write_16((uintptr_t)(DDRPHYC_BASE + (4U * (c_addr | TDBYTE | + CSR_TSMBYTE3_ADDR))), + regdata); + mmio_write_16((uintptr_t)(DDRPHYC_BASE + (4U * (c_addr | TDBYTE | + CSR_TSMBYTE5_ADDR))), + 0x1U); /* [15:0] bad_bar; */ + + /* + * - Register: TrainingParam + * - Fields: + * - EnDynRateReduction + * - RollIntoCoarse + * - IncDecRate + * - TrainEnRxEn + * - Dependencies: + * - user_input_advanced.DisableRetraining + */ + regdata = (CSR_ENDYNRATEREDUCTION_MASK | CSR_ROLLINTOCOARSE_MASK | + (0x3U << CSR_INCDECRATE_LSB)); + regdata = config->uia.disableretraining ? + regdata : (regdata | CSR_TRAINENRXEN_MASK); + mmio_write_16((uintptr_t)(DDRPHYC_BASE + (4U * (c_addr | TDBYTE | + CSR_TRAININGPARAM_ADDR))), + regdata); + + /* + * - Register: Tsm0 + * - Fields: + * - DtsmEnb + */ + regdata = (0x1U << CSR_DTSMENB_LSB); + mmio_write_16((uintptr_t)(DDRPHYC_BASE + (4U * (c_addr | I0 | TDBYTE | + CSR_TSM0_ADDR))), + regdata); + + /* + * - Register: Tsm2 + * - Fields: + * - DtsmDisErrChk + */ + regdata = (0x1U << CSR_DTSMDISERRCHK_LSB); + for (vec = 1U; vec <= I_MAX; vec++) { + i_addr = vec * I1; + mmio_write_16((uintptr_t)(DDRPHYC_BASE + (4U * (c_addr | i_addr | TDBYTE | + CSR_TSM2_ADDR))), + regdata); + } + } +} +#endif /* STM32MP_LPDDR4_TYPE */ + +/* + * - Register: calrate + * - Fields: + * - calOnce + * - calinterval + * - Dependencies + * - user_input_advanced.calinterval + * - user_input_advanced.calonce + */ +static void calrate_program(struct stm32mp_ddr_config *config) +{ + uint32_t calinterval; + uint32_t calonce; + uint16_t calrate; + + calinterval = config->uia.calinterval; + calonce = config->uia.calonce; + + calrate = (uint16_t)((0x1U << CSR_CALRUN_LSB) | (calonce << CSR_CALONCE_LSB) | + (calinterval << CSR_CALINTERVAL_LSB)); + + mmio_write_16((uintptr_t)(DDRPHYC_BASE + (4U * (TMASTER | CSR_CALRATE_ADDR))), calrate); +} + +/* + * Loads registers after training + * + * This function programs the PHY Initialization Engine (PIE) instructions and + * the associated registers. + * Training hardware registers are also programmed to for mission mode + * retraining. (LPDDR4) + * + * \return void + */ +void ddrphy_phyinit_i_loadpieimage(struct stm32mp_ddr_config *config, bool skip_training) +{ + /* + * Enable access to the internal CSRs by setting the MicroContMuxSel CSR to 0. + * This allows the memory controller unrestricted access to the configuration CSRs. + */ + mmio_write_16((uintptr_t)(DDRPHYC_BASE + (4U * (TAPBONLY | CSR_MICROCONTMUXSEL_ADDR))), + 0x0U); + + ddrphy_phyinit_loadpieprodcode(); + +#if STM32MP_LPDDR4_TYPE + /* + * No user specified EnableDfiCsPolarityFix, running with new PUB with DFI CS polarity fix + * so program the data polarity CSR. + */ + dfiwrrddatacsconfig_program(); +#endif /* STM32MP_LPDDR4_TYPE */ + + seq0bdly_program(config); + + seq0bdisableflag_program(config, skip_training); + +#if STM32MP_LPDDR4_TYPE + if (!skip_training) { + ppttrainsetup_program(config); + } + + acsmplayback_program(); + + traininghwreg_program(config); +#endif /* STM32MP_LPDDR4_TYPE */ + + /* + * - Register: CalZap + * - Prepare the calibration controller for mission mode. + * Turn on calibration and hold idle until dfi_init_start is asserted sequence is + * triggered. + */ + mmio_write_16((uintptr_t)(DDRPHYC_BASE + (4U * (TMASTER | CSR_CALZAP_ADDR))), 0x1U); + + calrate_program(config); + + /* + * At the end of this function, PHY Clk gating register UcclkHclkEnables is + * set for mission mode. Additionally APB access is Isolated by setting + * MicroContMuxSel. + */ + /* Disabling Ucclk (PMU) and Hclk (training hardware) */ + mmio_write_16((uintptr_t)(DDRPHYC_BASE + (4U * (TDRTUB | CSR_UCCLKHCLKENABLES_ADDR))), + 0x0U); + + /* Isolate the APB access from the internal CSRs by setting the MicroContMuxSel CSR to 1 */ + mmio_write_16((uintptr_t)(DDRPHYC_BASE + (4U * (TAPBONLY | CSR_MICROCONTMUXSEL_ADDR))), + 0x1U); +} diff --git a/drivers/st/ddr/phy/phyinit/src/ddrphy_phyinit_initstruct.c b/drivers/st/ddr/phy/phyinit/src/ddrphy_phyinit_initstruct.c new file mode 100644 index 000000000..50a88be4d --- /dev/null +++ b/drivers/st/ddr/phy/phyinit/src/ddrphy_phyinit_initstruct.c @@ -0,0 +1,262 @@ +/* + * Copyright (C) 2021-2024, STMicroelectronics - All Rights Reserved + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include + +#include + +#include + +/* + * This is used to initialize the PhyInit structures before user defaults and overrides are applied. + * + * @return Void + */ +void ddrphy_phyinit_initstruct(struct stm32mp_ddr_config *config, struct pmu_smb_ddr_1d *mb_ddr_1d) +{ + /* + * ############################################################## + * Basic Message Block Variables + * ############################################################## + */ + + uint8_t msgmisc = 0x00U; /* For fast simulation */ + uint8_t reserved00 = 0x0U; /* + * Set reserved00[7] = 1 (If using T28 attenuated receivers) + * Set reserved00[6:0] = 0 (Reserved; must be set to 0) + */ + + uint8_t hdtctrl = 0xFFU; +#if STM32MP_DDR3_TYPE || STM32MP_DDR4_TYPE + uint8_t cspresent = 0x01U; /* + * Indicates presence of DRAM at each chip select for PHY. + * + * If the bit is set to 1, the CS is connected to DRAM. + * If the bit is set to 0, the CS is not connected to DRAM. + * + * Set cspresent[0] = 1 (if CS0 is populated with DRAM) + * Set cspresent[1] = 1 (if CS1 is populated with DRAM) + * Set cspresent[2] = 1 (if CS2 is populated with DRAM) + * Set cspresent[3] = 1 (if CS3 is populated with DRAM) + * Set cspresent[7:4] = 0 (Reserved; must be set to 0) + */ + uint8_t dfimrlmargin = 0x01U; /* 1 is typically good in DDR3 */ +#if STM32MP_DDR3_TYPE + uint8_t addrmirror = 0x00U; /* + * Set addrmirror if CS is mirrored. + * (typically odd CS are mirroed in DIMMs) + */ +#else /* STM32MP_DDR4_TYPE */ + uint8_t addrmirror = 0xAAU; +#endif /* STM32MP_DDR3_TYPE */ + uint8_t wrodtpat_rank0 = 0x01U; /* + * When Writing Rank0 : Bits[3:0] should be set to the + * desired setting of ODT[3:0] to the DRAM + */ + uint8_t wrodtpat_rank1 = 0x02U; /* + * When Writing Rank1 : Bits[3:0] should be set to the + * desired setting of ODT[3:0] to the DRAM + */ +#if STM32MP_DDR3_TYPE + uint8_t wrodtpat_rank2 = 0x04U; /* + * When Writing Rank2 : Bits[3:0] should be set to the + * desired setting of ODT[3:0] to the DRAM + */ + uint8_t wrodtpat_rank3 = 0x08U; /* + * When Writing Rank3 : Bits[3:0] should be set to the + * desired setting of ODT[3:0] to the DRAM + */ +#else /* STM32MP_DDR4_TYPE */ + uint8_t wrodtpat_rank2 = 0x00U; + uint8_t wrodtpat_rank3 = 0x00U; +#endif /* STM32MP_DDR3_TYPE */ + uint8_t rdodtpat_rank0 = 0x20U; /* + * When Reading Rank0 : Bits[7:4] should be set to the + * desired setting of ODT[3:0] to the DRAM + */ + uint8_t rdodtpat_rank1 = 0x10U; /* + * When Reading Rank1 : Bits[7:4] should be set to the + * desired setting of ODT[3:0] to the DRAM + */ +#if STM32MP_DDR3_TYPE + uint8_t rdodtpat_rank2 = 0x80U; /* + * When Reading Rank2 : Bits[7:4] should be set to the + * desired setting of ODT[3:0] to the DRAM + */ + uint8_t rdodtpat_rank3 = 0x40U; /* + * When Reading Rank3 : Bits[7:4] should be set to the + * desired setting of ODT[3:0] to the DRAM + */ +#else /* STM32MP_DDR4_TYPE */ + uint8_t rdodtpat_rank2 = 0x00U; + uint8_t rdodtpat_rank3 = 0x00U; + + uint8_t d4misc = 0x1U; /* + * Protect memory reset: + * 0x1 = dfi_reset_n cannot control BP_MEMRESERT_L to + * devices after training. + * 0x0 = dfi_resert_n can control BP_MEMRESERT_L to + * devices after training. + */ +#endif /* STM32MP_DDR3_TYPE */ +#else /* STM32MP_LPDDR4_TYPE */ + uint8_t caterminatingrankcha = 0x00U; /* Usually Rank0 is terminating rank */ + uint8_t caterminatingrankchb = 0x00U; /* Usually Rank0 is terminating rank */ + uint8_t dfimrlmargin = 0x02U; /* This needs to be large enough for max tDQSCK variation */ +#endif /* STM32MP_DDR3_TYPE || STM32MP_DDR4_TYPE */ + +#if STM32MP_DDR3_TYPE + uint8_t share2dvrefresult = 0x0U; /* + * Bitmap that controls which vref generator the + * phy will use per pstate + * If share2dvrefresult[x] = 1, pstate x will + * use the per-lane VrefDAC0/1 CSRs which can be + * trained by 2d training. If 2D has not run + * yet, VrefDAC0/1 will default to pstate 0's + * 1D phyVref messageBlock setting. + * If share2dvrefresult[x] = 0, pstate x will + * use the per-phy VrefInGlobal CSR, which are + * set to pstate x's 1D phyVref messageBlock + * setting. + */ +#elif STM32MP_DDR4_TYPE + uint8_t share2dvrefresult = 0x1U; +#else /* STM32MP_LPDDR4_TYPE */ + uint8_t share2dvrefresult = 0x1U; + uint8_t usebroadcastmr = 0x00U; +#endif /* STM32MP_DDR3_TYPE */ + + /* 1D message block defaults */ + memset((void *)mb_ddr_1d, 0, sizeof(struct pmu_smb_ddr_1d)); + + mb_ddr_1d->pstate = 0U; + mb_ddr_1d->sequencectrl = (uint16_t)config->uia.sequencectrl; + mb_ddr_1d->phyconfigoverride = 0x0U; + mb_ddr_1d->hdtctrl = hdtctrl; + mb_ddr_1d->msgmisc = msgmisc; + mb_ddr_1d->reserved00 = reserved00; + mb_ddr_1d->dfimrlmargin = dfimrlmargin; + mb_ddr_1d->phyvref = (uint8_t)config->uia.phyvref; + +#if STM32MP_DDR3_TYPE || STM32MP_DDR4_TYPE + mb_ddr_1d->cspresent = cspresent; + mb_ddr_1d->cspresentd0 = cspresent; + /* mb_ddr_1d->cspresentd1 = 0x0U; Unused */ + mb_ddr_1d->addrmirror = addrmirror; + + mb_ddr_1d->acsmodtctrl0 = wrodtpat_rank0 | rdodtpat_rank0; + mb_ddr_1d->acsmodtctrl1 = wrodtpat_rank1 | rdodtpat_rank1; + mb_ddr_1d->acsmodtctrl2 = wrodtpat_rank2 | rdodtpat_rank2; + mb_ddr_1d->acsmodtctrl3 = wrodtpat_rank3 | rdodtpat_rank3; + + /* mb_ddr_1d->acsmodtctrl4 = 0x0U; Unused */ + /* mb_ddr_1d->acsmodtctrl5 = 0x0U; Unused */ + /* mb_ddr_1d->acsmodtctrl6 = 0x0U; Unused */ + /* mb_ddr_1d->acsmodtctrl7 = 0x0U; Unused */ + mb_ddr_1d->enableddqs = (uint8_t)((config->uib.numactivedbytedfi0 + + config->uib.numactivedbytedfi1) * 8U); +#if STM32MP_DDR3_TYPE + mb_ddr_1d->phycfg = (uint8_t)config->uia.is2ttiming; +#else /* STM32MP_DDR4_TYPE */ + mb_ddr_1d->phycfg = ((config->uim.mr3 & 0x8U) == 0x8U) ? + 0U : (uint8_t)config->uia.is2ttiming; + mb_ddr_1d->x16present = (config->uib.dramdatawidth == 0x10) ? + mb_ddr_1d->cspresent : 0x0U; + mb_ddr_1d->d4misc = d4misc; + mb_ddr_1d->cssetupgddec = 0x1U; /* If Geardown is chosen, dynamically modify CS timing */ + + /* + * Outputs - just initialize these to zero + * mb_ddr_1d->rtt_nom_wr_park<0..7> + */ +#endif /* STM32MP_DDR3_TYPE */ + + mb_ddr_1d->mr0 = (uint16_t)config->uim.mr0; + mb_ddr_1d->mr1 = (uint16_t)config->uim.mr1; + mb_ddr_1d->mr2 = (uint16_t)config->uim.mr2; +#if STM32MP_DDR4_TYPE + mb_ddr_1d->mr3 = (uint16_t)config->uim.mr3; + mb_ddr_1d->mr4 = (uint16_t)config->uim.mr4; + mb_ddr_1d->mr5 = (uint16_t)config->uim.mr5; + mb_ddr_1d->mr6 = (uint16_t)config->uim.mr6; + + mb_ddr_1d->alt_cas_l = 0x0U; + mb_ddr_1d->alt_wcas_l = 0x0U; + + /* + * Outputs - just initialize these to zero + * mb_ddr_1d->vrefdqr<0..3>nib<0..19> + */ +#endif /* STM32MP_DDR4_TYPE */ +#else /* STM32MP_LPDDR4_TYPE */ + mb_ddr_1d->enableddqscha = (uint8_t)(config->uib.numactivedbytedfi0 * 8U); + mb_ddr_1d->cspresentcha = (config->uib.numrank_dfi0 == 2U) ? + 0x3U : (uint8_t)config->uib.numrank_dfi0; + mb_ddr_1d->enableddqschb = (uint8_t)(config->uib.numactivedbytedfi1 * 8U); + mb_ddr_1d->cspresentchb = (config->uib.numrank_dfi1 == 2U) ? + 0x3U : (uint8_t)config->uib.numrank_dfi1; + mb_ddr_1d->usebroadcastmr = usebroadcastmr; + + mb_ddr_1d->lp4misc = 0x00U; + mb_ddr_1d->caterminatingrankcha = caterminatingrankcha; + mb_ddr_1d->caterminatingrankchb = caterminatingrankchb; + mb_ddr_1d->lp4quickboot = 0x00U; + mb_ddr_1d->catrainopt = 0x00U; + mb_ddr_1d->x8mode = 0x00U; + + mb_ddr_1d->mr1_a0 = (uint8_t)config->uim.mr1; + mb_ddr_1d->mr2_a0 = (uint8_t)config->uim.mr2; + mb_ddr_1d->mr3_a0 = (uint8_t)config->uim.mr3; + mb_ddr_1d->mr4_a0 = (uint8_t)config->uim.mr4; + mb_ddr_1d->mr11_a0 = (uint8_t)config->uim.mr11; + mb_ddr_1d->mr12_a0 = (uint8_t)config->uim.mr12; + mb_ddr_1d->mr13_a0 = (uint8_t)config->uim.mr13; + mb_ddr_1d->mr14_a0 = (uint8_t)config->uim.mr14; + mb_ddr_1d->mr16_a0 = 0x00U; + mb_ddr_1d->mr17_a0 = 0x00U; + mb_ddr_1d->mr22_a0 = (uint8_t)config->uim.mr22; + mb_ddr_1d->mr24_a0 = 0x00U; + mb_ddr_1d->mr1_a1 = (uint8_t)config->uim.mr1; + mb_ddr_1d->mr2_a1 = (uint8_t)config->uim.mr2; + mb_ddr_1d->mr3_a1 = (uint8_t)config->uim.mr3; + mb_ddr_1d->mr4_a1 = (uint8_t)config->uim.mr4; + mb_ddr_1d->mr11_a1 = (uint8_t)config->uim.mr11; + mb_ddr_1d->mr12_a1 = (uint8_t)config->uim.mr12; + mb_ddr_1d->mr13_a1 = (uint8_t)config->uim.mr13; + mb_ddr_1d->mr14_a1 = (uint8_t)config->uim.mr14; + mb_ddr_1d->mr16_a1 = 0x00U; + mb_ddr_1d->mr17_a1 = 0x00U; + mb_ddr_1d->mr22_a1 = (uint8_t)config->uim.mr22; + mb_ddr_1d->mr24_a1 = 0x00U; + + mb_ddr_1d->mr1_b0 = (uint8_t)config->uim.mr1; + mb_ddr_1d->mr2_b0 = (uint8_t)config->uim.mr2; + mb_ddr_1d->mr3_b0 = (uint8_t)config->uim.mr3; + mb_ddr_1d->mr4_b0 = (uint8_t)config->uim.mr4; + mb_ddr_1d->mr11_b0 = (uint8_t)config->uim.mr11; + mb_ddr_1d->mr12_b0 = (uint8_t)config->uim.mr12; + mb_ddr_1d->mr13_b0 = (uint8_t)config->uim.mr13; + mb_ddr_1d->mr14_b0 = (uint8_t)config->uim.mr14; + mb_ddr_1d->mr16_b0 = 0x00U; + mb_ddr_1d->mr17_b0 = 0x00U; + mb_ddr_1d->mr22_b0 = (uint8_t)config->uim.mr22; + mb_ddr_1d->mr24_b0 = 0x00U; + mb_ddr_1d->mr1_b1 = (uint8_t)config->uim.mr1; + mb_ddr_1d->mr2_b1 = (uint8_t)config->uim.mr2; + mb_ddr_1d->mr3_b1 = (uint8_t)config->uim.mr3; + mb_ddr_1d->mr4_b1 = (uint8_t)config->uim.mr4; + mb_ddr_1d->mr11_b1 = (uint8_t)config->uim.mr11; + mb_ddr_1d->mr12_b1 = (uint8_t)config->uim.mr12; + mb_ddr_1d->mr13_b1 = (uint8_t)config->uim.mr13; + mb_ddr_1d->mr14_b1 = (uint8_t)config->uim.mr14; + mb_ddr_1d->mr16_b1 = 0x00U; + mb_ddr_1d->mr17_b1 = 0x00U; + mb_ddr_1d->mr22_b1 = (uint8_t)config->uim.mr22; + mb_ddr_1d->mr24_b1 = 0x00U; +#endif /* STM32MP_DDR3_TYPE || STM32MP_DDR4_TYPE */ + + mb_ddr_1d->share2dvrefresult = share2dvrefresult; +} diff --git a/drivers/st/ddr/phy/phyinit/src/ddrphy_phyinit_isdbytedisabled.c b/drivers/st/ddr/phy/phyinit/src/ddrphy_phyinit_isdbytedisabled.c new file mode 100644 index 000000000..4daf2bb02 --- /dev/null +++ b/drivers/st/ddr/phy/phyinit/src/ddrphy_phyinit_isdbytedisabled.c @@ -0,0 +1,88 @@ +/* + * Copyright (C) 2021-2024, STMicroelectronics - All Rights Reserved + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include + +#include + +#include +#include + +/* + * Helper function to determine if a given DByte is Disabled given PhyInit inputs. + * @return 1 if disabled, 0 if enabled. + */ +int ddrphy_phyinit_isdbytedisabled(struct stm32mp_ddr_config *config, + struct pmu_smb_ddr_1d *mb_ddr_1d, uint32_t dbytenumber) +{ + int disabledbyte; + uint32_t nad0 __maybe_unused; + uint32_t nad1 __maybe_unused; + + disabledbyte = 0; /* Default assume Dbyte is Enabled */ + +#if STM32MP_DDR3_TYPE || STM32MP_DDR4_TYPE + disabledbyte = (dbytenumber > (config->uib.numactivedbytedfi0 - 1U)) ? 1 : 0; +#else /* STM32MP_LPDDR4_TYPE */ + nad0 = config->uib.numactivedbytedfi0; + nad1 = config->uib.numactivedbytedfi1; + + if ((nad0 + nad1) > config->uib.numdbyte) { + ERROR("%s %d\n", __func__, __LINE__); + VERBOSE("%s invalid PHY configuration:\n", __func__); + VERBOSE("numactivedbytedfi0(%u)+numactivedbytedfi1(%u)>numdbytes(%u).\n", + nad0, nad1, config->uib.numdbyte); + } + + if (config->uib.dfi1exists != 0U) { + if (config->uib.numactivedbytedfi1 == 0U) { + /* Only dfi0 (ChA) is enabled, dfi1 (ChB) disabled */ + disabledbyte = (dbytenumber > (config->uib.numactivedbytedfi0 - 1U)) ? + 1 : 0; + } else { + /* DFI1 enabled */ + disabledbyte = (((config->uib.numactivedbytedfi0 - 1U) < dbytenumber) && + (dbytenumber < (config->uib.numdbyte / 2U))) ? + 1 : (dbytenumber > + ((config->uib.numdbyte / 2U) + + config->uib.numactivedbytedfi1 - 1U)) ? 1 : 0; + } + } else { + disabledbyte = (dbytenumber > (config->uib.numactivedbytedfi0 - 1U)) ? 1 : 0; + } +#endif /* STM32MP_DDR3_TYPE || STM32MP_DDR4_TYPE */ + + /* Qualify results against MessageBlock */ +#if STM32MP_DDR3_TYPE || STM32MP_DDR4_TYPE + if ((mb_ddr_1d->enableddqs < 1U) || + (mb_ddr_1d->enableddqs > (uint8_t)(8U * config->uib.numactivedbytedfi0))) { + ERROR("%s %d\n", __func__, __LINE__); + VERBOSE("%s enableddqs(%u)\n", __func__, mb_ddr_1d->enableddqs); + VERBOSE("Value must be 0 < enableddqs < config->uib.numactivedbytedfi0 * 8.\n"); + } + + if (dbytenumber < 8) { + disabledbyte |= (int)mb_ddr_1d->disableddbyte & (0x1 << dbytenumber); + } +#else /* STM32MP_LPDDR4_TYPE */ + if ((mb_ddr_1d->enableddqscha < 1U) || + (mb_ddr_1d->enableddqscha > (uint8_t)(8U * config->uib.numactivedbytedfi0))) { + ERROR("%s %d\n", __func__, __LINE__); + VERBOSE("%s enableddqscha(%u)\n", __func__, mb_ddr_1d->enableddqscha); + VERBOSE("Value must be 0 < enableddqscha < config->uib.numactivedbytedfi0*8\n"); + } + + if ((config->uib.dfi1exists != 0U) && (config->uib.numactivedbytedfi1 > 0U) && + ((mb_ddr_1d->enableddqschb < 1U) || + (mb_ddr_1d->enableddqschb > (uint8_t)(8U * config->uib.numactivedbytedfi1)))) { + ERROR("%s %d\n", __func__, __LINE__); + VERBOSE("%s enableddqschb(%u)\n", __func__, mb_ddr_1d->enableddqschb); + VERBOSE("Value must be 0 < enableddqschb < config->uib.numactivedbytedfi1*8\n"); + } +#endif /* STM32MP_DDR3_TYPE || STM32MP_DDR4_TYPE */ + + return disabledbyte; +} diff --git a/drivers/st/ddr/phy/phyinit/src/ddrphy_phyinit_loadpieprodcode.c b/drivers/st/ddr/phy/phyinit/src/ddrphy_phyinit_loadpieprodcode.c new file mode 100644 index 000000000..2843b10ea --- /dev/null +++ b/drivers/st/ddr/phy/phyinit/src/ddrphy_phyinit_loadpieprodcode.c @@ -0,0 +1,189 @@ +/* + * Copyright (C) 2021-2024, STMicroelectronics - All Rights Reserved + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include + +#include + +#include + +#include + +#include + +#if STM32MP_DDR3_TYPE || STM32MP_DDR4_TYPE +#define PRODCODE_SIZE 177 + +static const uint32_t prodcode_addr[PRODCODE_SIZE] = { + 0x90000U, 0x90001U, 0x90002U, 0x90003U, 0x90004U, 0x90005U, 0x90029U, 0x9002AU, 0x9002BU, + 0x9002CU, 0x9002DU, 0x9002EU, 0x9002FU, 0x90030U, 0x90031U, 0x90032U, 0x90033U, 0x90034U, + 0x90035U, 0x90036U, 0x90037U, 0x90038U, 0x90039U, 0x9003AU, 0x9003BU, 0x9003CU, 0x9003DU, + 0x9003EU, 0x9003FU, 0x90040U, 0x90041U, 0x90042U, 0x90043U, 0x90044U, 0x90045U, 0x90046U, + 0x90047U, 0x90048U, 0x90049U, 0x9004AU, 0x9004BU, 0x9004CU, 0x9004DU, 0x9004EU, 0x9004FU, + 0x90050U, 0x90051U, 0x90052U, 0x90053U, 0x90054U, 0x90055U, 0x90056U, 0x90057U, 0x90058U, + 0x90059U, 0x9005AU, 0x9005BU, 0x9005CU, 0x9005DU, 0x9005EU, 0x9005FU, 0x90060U, 0x90061U, + 0x90062U, 0x90063U, 0x90064U, 0x90065U, 0x90066U, 0x90067U, 0x90068U, 0x90069U, 0x9006AU, + 0x9006BU, 0x9006CU, 0x9006DU, 0x9006EU, 0x9006FU, 0x90070U, 0x90071U, 0x90072U, 0x90073U, + 0x90074U, 0x90075U, 0x90076U, 0x90077U, 0x90078U, 0x90079U, 0x9007AU, 0x9007BU, 0x9007CU, + 0x9007DU, 0x9007EU, 0x9007FU, 0x90080U, 0x90081U, 0x90082U, 0x90083U, 0x90084U, 0x90085U, + 0x90086U, 0x90087U, 0x90088U, 0x90089U, 0x9008AU, 0x9008BU, 0x9008CU, 0x9008DU, 0x9008EU, + 0x9008FU, 0x90090U, 0x90091U, 0x90092U, 0x90093U, 0x90094U, 0x90095U, 0x90096U, 0x90097U, + 0x90098U, 0x90099U, 0x9009AU, 0x9009BU, 0x9009CU, 0x9009DU, 0x9009EU, 0x9009FU, 0x900A0U, + 0x900A1U, 0x900A2U, 0x900A3U, 0x900A4U, 0x900A5U, 0x900A6U, 0x900A7U, 0x900A8U, 0x900A9U, + 0x900AAU, 0x900ABU, 0x900ACU, 0x900ADU, 0x900AEU, 0x900AFU, 0x900B0U, 0x900B1U, 0x900B2U, + 0x900B3U, 0x900B4U, 0x900B5U, 0x900B6U, 0x900B7U, 0x900B8U, 0x900B9U, 0x900BAU, 0x900BBU, + 0x900BCU, 0x900BDU, 0x900BEU, 0x900BFU, 0x900C0U, 0x900C1U, 0x900C2U, 0x900C3U, 0x900C4U, + 0x900C5U, 0x900C6U, 0x900C7U, 0x900C8U, 0x900C9U, 0x900CAU, 0x90006U, 0x90007U, 0x90008U, + 0x90009U, 0x9000AU, 0x9000BU, 0xD00E7U, 0x90017U, 0x90026U, +}; + +static const uint16_t prodcode_data[PRODCODE_SIZE] = { + 0x0010U, 0x0400U, 0x010EU, 0x0000U, 0x0000U, 0x0008U, 0x000BU, 0x0480U, 0x0109U, 0x0008U, + 0x0448U, 0x0139U, 0x0008U, 0x0478U, 0x0109U, 0x0002U, 0x0010U, 0x0139U, 0x000BU, 0x07C0U, + 0x0139U, 0x0044U, 0x0633U, 0x0159U, 0x014FU, 0x0630U, 0x0159U, 0x0047U, 0x0633U, 0x0149U, + 0x004FU, 0x0633U, 0x0179U, 0x0008U, 0x00E0U, 0x0109U, 0x0000U, 0x07C8U, 0x0109U, 0x0000U, + 0x0001U, 0x0008U, 0x0030U, 0x065AU, 0x0009U, 0x0000U, 0x045AU, 0x0009U, 0x0000U, 0x0448U, + 0x0109U, 0x0040U, 0x0633U, 0x0179U, 0x0001U, 0x0618U, 0x0109U, 0x40C0U, 0x0633U, 0x0149U, + 0x0008U, 0x0004U, 0x0048U, 0x4040U, 0x0633U, 0x0149U, 0x0000U, 0x0004U, 0x0048U, 0x0040U, + 0x0633U, 0x0149U, 0x0000U, 0x0658U, 0x0109U, 0x0010U, 0x0004U, 0x0018U, 0x0000U, 0x0004U, + 0x0078U, 0x0549U, 0x0633U, 0x0159U, 0x0D49U, 0x0633U, 0x0159U, 0x094AU, 0x0633U, 0x0159U, + 0x0441U, 0x0633U, 0x0149U, 0x0042U, 0x0633U, 0x0149U, 0x0001U, 0x0633U, 0x0149U, 0x0000U, + 0x00E0U, 0x0109U, 0x000AU, 0x0010U, 0x0109U, 0x0009U, 0x03C0U, 0x0149U, 0x0009U, 0x03C0U, + 0x0159U, 0x0018U, 0x0010U, 0x0109U, 0x0000U, 0x03C0U, 0x0109U, 0x0018U, 0x0004U, 0x0048U, + 0x0018U, 0x0004U, 0x0058U, 0x000BU, 0x0010U, 0x0109U, 0x0001U, 0x0010U, 0x0109U, 0x0005U, + 0x07C0U, 0x0109U, 0x0000U, 0x8140U, 0x010CU, 0x0010U, 0x8138U, 0x0104U, 0x0008U, 0x0448U, + 0x0109U, 0x000FU, 0x07C0U, 0x0109U, 0x0047U, 0x0630U, 0x0109U, 0x0008U, 0x0618U, 0x0109U, + 0x0008U, 0x00E0U, 0x0109U, 0x0000U, 0x07C8U, 0x0109U, 0x0008U, 0x8140U, 0x010CU, 0x0000U, + 0x0478U, 0x0109U, 0x0000U, 0x0001U, 0x0008U, 0x0008U, 0x0004U, 0x0000U, 0x0008U, 0x07C8U, + 0x0109U, 0x0000U, 0x0400U, 0x0106U, 0x0400U, 0x0000U, 0x002CU, + }; + +#else /* STM32MP_LPDDR4_TYPE */ +#define PRODCODE_SIZE 481 + +static const uint32_t prodcode_addr[PRODCODE_SIZE] = { + 0x90000U, 0x90001U, 0x90002U, 0x90003U, 0x90004U, 0x90005U, 0x90029U, 0x9002AU, 0x9002BU, + 0x9002CU, 0x9002DU, 0x9002EU, 0x9002FU, 0x90030U, 0x90031U, 0x90032U, 0x90033U, 0x90034U, + 0x90035U, 0x90036U, 0x90037U, 0x90038U, 0x90039U, 0x9003AU, 0x9003BU, 0x9003CU, 0x9003DU, + 0x9003EU, 0x9003FU, 0x90040U, 0x90041U, 0x90042U, 0x90043U, 0x90044U, 0x90045U, 0x90046U, + 0x90047U, 0x90048U, 0x90049U, 0x9004AU, 0x9004BU, 0x9004CU, 0x9004DU, 0x9004EU, 0x9004FU, + 0x90050U, 0x90051U, 0x90052U, 0x90053U, 0x90054U, 0x90055U, 0x90056U, 0x90057U, 0x90058U, + 0x90059U, 0x9005AU, 0x9005BU, 0x9005CU, 0x9005DU, 0x9005EU, 0x9005FU, 0x90060U, 0x90061U, + 0x90062U, 0x90063U, 0x90064U, 0x90065U, 0x90066U, 0x90067U, 0x90068U, 0x90069U, 0x9006AU, + 0x9006BU, 0x9006CU, 0x9006DU, 0x9006EU, 0x9006FU, 0x90070U, 0x90071U, 0x90072U, 0x90073U, + 0x90074U, 0x90075U, 0x90076U, 0x90077U, 0x90078U, 0x90079U, 0x9007AU, 0x9007BU, 0x9007CU, + 0x9007DU, 0x9007EU, 0x9007FU, 0x90080U, 0x90081U, 0x90082U, 0x90083U, 0x90084U, 0x90085U, + 0x90086U, 0x90087U, 0x90088U, 0x90089U, 0x9008AU, 0x9008BU, 0x9008CU, 0x9008DU, 0x9008EU, + 0x9008FU, 0x90090U, 0x90091U, 0x90092U, 0x90093U, 0x90094U, 0x90095U, 0x90096U, 0x90097U, + 0x90098U, 0x90099U, 0x9009AU, 0x9009BU, 0x9009CU, 0x9009DU, 0x9009EU, 0x9009FU, 0x900A0U, + 0x900A1U, 0x900A2U, 0x900A3U, 0x900A4U, 0x900A5U, 0x900A6U, 0x900A7U, 0x900A8U, 0x900A9U, + 0x40000U, 0x40020U, 0x40040U, 0x40060U, 0x40001U, 0x40021U, 0x40041U, 0x40061U, 0x40002U, + 0x40022U, 0x40042U, 0x40062U, 0x40003U, 0x40023U, 0x40043U, 0x40063U, 0x40004U, 0x40024U, + 0x40044U, 0x40064U, 0x40005U, 0x40025U, 0x40045U, 0x40065U, 0x40006U, 0x40026U, 0x40046U, + 0x40066U, 0x40007U, 0x40027U, 0x40047U, 0x40067U, 0x40008U, 0x40028U, 0x40048U, 0x40068U, + 0x40009U, 0x40029U, 0x40049U, 0x40069U, 0x4000AU, 0x4002AU, 0x4004AU, 0x4006AU, 0x4000BU, + 0x4002BU, 0x4004BU, 0x4006BU, 0x4000CU, 0x4002CU, 0x4004CU, 0x4006CU, 0x4000DU, 0x4002DU, + 0x4004DU, 0x4006DU, 0x4000EU, 0x4002EU, 0x4004EU, 0x4006EU, 0x4000FU, 0x4002FU, 0x4004FU, + 0x4006FU, 0x40010U, 0x40030U, 0x40050U, 0x40070U, 0x40011U, 0x40031U, 0x40051U, 0x40071U, + 0x40012U, 0x40032U, 0x40052U, 0x40072U, 0x40013U, 0x40033U, 0x40053U, 0x40073U, 0x40014U, + 0x40034U, 0x40054U, 0x40074U, 0x40015U, 0x40035U, 0x40055U, 0x40075U, 0x40016U, 0x40036U, + 0x40056U, 0x40076U, 0x40017U, 0x40037U, 0x40057U, 0x40077U, 0x40018U, 0x40038U, 0x40058U, + 0x40078U, 0x40019U, 0x40039U, 0x40059U, 0x40079U, 0x4001AU, 0x4003AU, 0x4005AU, 0x4007AU, + 0x900AAU, 0x900ABU, 0x900ACU, 0x900ADU, 0x900AEU, 0x900AFU, 0x900B0U, 0x900B1U, 0x900B2U, + 0x900B3U, 0x900B4U, 0x900B5U, 0x900B6U, 0x900B7U, 0x900B8U, 0x900B9U, 0x900BAU, 0x900BBU, + 0x900BCU, 0x900BDU, 0x900BEU, 0x900BFU, 0x900C0U, 0x900C1U, 0x900C2U, 0x900C3U, 0x900C4U, + 0x900C5U, 0x900C6U, 0x900C7U, 0x900C8U, 0x900C9U, 0x900CAU, 0x900CBU, 0x900CCU, 0x900CDU, + 0x900CEU, 0x900CFU, 0x900D0U, 0x900D1U, 0x900D2U, 0x900D3U, 0x900D4U, 0x900D5U, 0x900D6U, + 0x900D7U, 0x900D8U, 0x900D9U, 0x900DAU, 0x900DBU, 0x900DCU, 0x900DDU, 0x900DEU, 0x900DFU, + 0x900E0U, 0x900E1U, 0x900E2U, 0x900E3U, 0x900E4U, 0x900E5U, 0x900E6U, 0x900E7U, 0x900E8U, + 0x900E9U, 0x900EAU, 0x900EBU, 0x900ECU, 0x900EDU, 0x900EEU, 0x900EFU, 0x900F0U, 0x900F1U, + 0x900F2U, 0x900F3U, 0x900F4U, 0x900F5U, 0x900F6U, 0x900F7U, 0x900F8U, 0x900F9U, 0x900FAU, + 0x900FBU, 0x900FCU, 0x900FDU, 0x900FEU, 0x900FFU, 0x90100U, 0x90101U, 0x90102U, 0x90103U, + 0x90104U, 0x90105U, 0x90106U, 0x90107U, 0x90108U, 0x90109U, 0x9010AU, 0x9010BU, 0x9010CU, + 0x9010DU, 0x9010EU, 0x9010FU, 0x90110U, 0x90111U, 0x90112U, 0x90113U, 0x90114U, 0x90115U, + 0x90116U, 0x90117U, 0x90118U, 0x90119U, 0x9011AU, 0x9011BU, 0x9011CU, 0x9011DU, 0x9011EU, + 0x9011FU, 0x90120U, 0x90121U, 0x90122U, 0x90123U, 0x90124U, 0x90125U, 0x90126U, 0x90127U, + 0x90128U, 0x90129U, 0x9012AU, 0x9012BU, 0x9012CU, 0x9012DU, 0x9012EU, 0x9012FU, 0x90130U, + 0x90131U, 0x90132U, 0x90133U, 0x90134U, 0x90135U, 0x90136U, 0x90137U, 0x90138U, 0x90139U, + 0x9013AU, 0x9013BU, 0x9013CU, 0x9013DU, 0x9013EU, 0x9013FU, 0x90140U, 0x90141U, 0x90142U, + 0x90143U, 0x90144U, 0x90145U, 0x90146U, 0x90147U, 0x90148U, 0x90149U, 0x9014AU, 0x9014BU, + 0x9014CU, 0x9014DU, 0x9014EU, 0x9014FU, 0x90150U, 0x90151U, 0x90152U, 0x90153U, 0x90154U, + 0x90155U, 0x90156U, 0x90157U, 0x90158U, 0x90159U, 0x9015AU, 0x9015BU, 0x9015CU, 0x9015DU, + 0x9015EU, 0x9015FU, 0x90160U, 0x90161U, 0x90162U, 0x90163U, 0x90164U, 0x90165U, 0x90166U, + 0x90167U, 0x90168U, 0x90169U, 0x9016AU, 0x9016BU, 0x9016CU, 0x9016DU, 0x9016EU, 0x9016FU, + 0x90170U, 0x90171U, 0x90172U, 0x90173U, 0x90174U, 0x90175U, 0x90176U, 0x90177U, 0x90178U, + 0x90179U, 0x9017AU, 0x9017BU, 0x9017CU, 0x9017DU, 0x9017EU, 0x9017FU, 0x90180U, 0x90181U, + 0x90182U, 0x90183U, 0x90184U, 0x90006U, 0x90007U, 0x90008U, 0x90009U, 0x9000AU, 0x9000BU, + 0xD00E7U, 0x90017U, 0x9001FU, 0x90026U, 0x400D0U, 0x400D1U, 0x400D2U, 0x400D3U, 0x400D4U, + 0x400D5U, 0x400D6U, 0x400D7U, 0x2003AU, + }; + +static const uint16_t prodcode_data[PRODCODE_SIZE] = { + 0x0010U, 0x0400U, 0x010EU, 0x0000U, 0x0000U, 0x0008U, 0x000BU, 0x0480U, 0x0109U, 0x0008U, + 0x0448U, 0x0139U, 0x0008U, 0x0478U, 0x0109U, 0x0000U, 0x00E8U, 0x0109U, 0x0002U, 0x0010U, + 0x0139U, 0x000BU, 0x07C0U, 0x0139U, 0x0044U, 0x0633U, 0x0159U, 0x014FU, 0x0630U, 0x0159U, + 0x0047U, 0x0633U, 0x0149U, 0x004FU, 0x0633U, 0x0179U, 0x0008U, 0x00E0U, 0x0109U, 0x0000U, + 0x07C8U, 0x0109U, 0x0000U, 0x0001U, 0x0008U, 0x0030U, 0x065AU, 0x0009U, 0x0000U, 0x045AU, + 0x0009U, 0x0000U, 0x0448U, 0x0109U, 0x0040U, 0x0633U, 0x0179U, 0x0001U, 0x0618U, 0x0109U, + 0x40C0U, 0x0633U, 0x0149U, 0x0008U, 0x0004U, 0x0048U, 0x4040U, 0x0633U, 0x0149U, 0x0000U, + 0x0004U, 0x0048U, 0x0040U, 0x0633U, 0x0149U, 0x0000U, 0x0658U, 0x0109U, 0x0010U, 0x0004U, + 0x0018U, 0x0000U, 0x0004U, 0x0078U, 0x0549U, 0x0633U, 0x0159U, 0x0D49U, 0x0633U, 0x0159U, + 0x094AU, 0x0633U, 0x0159U, 0x0441U, 0x0633U, 0x0149U, 0x0042U, 0x0633U, 0x0149U, 0x0001U, + 0x0633U, 0x0149U, 0x0000U, 0x00E0U, 0x0109U, 0x000AU, 0x0010U, 0x0109U, 0x0009U, 0x03C0U, + 0x0149U, 0x0009U, 0x03C0U, 0x0159U, 0x0018U, 0x0010U, 0x0109U, 0x0000U, 0x03C0U, 0x0109U, + 0x0018U, 0x0004U, 0x0048U, 0x0018U, 0x0004U, 0x0058U, 0x000BU, 0x0010U, 0x0109U, 0x0001U, + 0x0010U, 0x0109U, 0x0005U, 0x07C0U, 0x0109U, 0x0811U, 0x0880U, 0x0000U, 0x0000U, 0x4008U, + 0x0083U, 0x004FU, 0x0000U, 0x4040U, 0x0083U, 0x0051U, 0x0000U, 0x0811U, 0x0880U, 0x0000U, + 0x0000U, 0x0720U, 0x000FU, 0x1740U, 0x0000U, 0x0016U, 0x0083U, 0x004BU, 0x0000U, 0x0716U, + 0x000FU, 0x2001U, 0x0000U, 0x0716U, 0x000FU, 0x2800U, 0x0000U, 0x0716U, 0x000FU, 0x0F00U, + 0x0000U, 0x0720U, 0x000FU, 0x1400U, 0x0000U, 0x0E08U, 0x0C15U, 0x0000U, 0x0000U, 0x0625U, + 0x0015U, 0x0000U, 0x0000U, 0x4028U, 0x0080U, 0x0000U, 0x0000U, 0x0E08U, 0x0C1AU, 0x0000U, + 0x0000U, 0x0625U, 0x001AU, 0x0000U, 0x0000U, 0x4040U, 0x0080U, 0x0000U, 0x0000U, 0x2604U, + 0x0015U, 0x0000U, 0x0000U, 0x0708U, 0x0005U, 0x0000U, 0x2002U, 0x0008U, 0x0080U, 0x0000U, + 0x0000U, 0x2604U, 0x001AU, 0x0000U, 0x0000U, 0x0708U, 0x000AU, 0x0000U, 0x2002U, 0x4040U, + 0x0080U, 0x0000U, 0x0000U, 0x060AU, 0x0015U, 0x1200U, 0x0000U, 0x061AU, 0x0015U, 0x1300U, + 0x0000U, 0x060AU, 0x001AU, 0x1200U, 0x0000U, 0x0642U, 0x001AU, 0x1300U, 0x0000U, 0x4808U, + 0x0880U, 0x0000U, 0x0000U, 0x0000U, 0x0790U, 0x011AU, 0x0008U, 0x07AAU, 0x002AU, 0x0010U, + 0x07B2U, 0x002AU, 0x0000U, 0x07C8U, 0x0109U, 0x0010U, 0x0010U, 0x0109U, 0x0010U, 0x02A8U, + 0x0129U, 0x0008U, 0x0370U, 0x0129U, 0x000AU, 0x03C8U, 0x01A9U, 0x000CU, 0x0408U, 0x0199U, + 0x0014U, 0x0790U, 0x011AU, 0x0008U, 0x0004U, 0x0018U, 0x000EU, 0x0408U, 0x0199U, 0x0008U, + 0x8568U, 0x0108U, 0x0018U, 0x0790U, 0x016AU, 0x0008U, 0x01D8U, 0x0169U, 0x0010U, 0x8558U, + 0x0168U, 0x1FF8U, 0x85A8U, 0x01E8U, 0x0050U, 0x0798U, 0x016AU, 0x0060U, 0x07A0U, 0x016AU, + 0x0008U, 0x8310U, 0x0168U, 0x0008U, 0xA310U, 0x0168U, 0x000AU, 0x0408U, 0x0169U, 0x006EU, + 0x0000U, 0x0068U, 0x0000U, 0x0408U, 0x0169U, 0x0000U, 0x8310U, 0x0168U, 0x0000U, 0xA310U, + 0x0168U, 0x1FF8U, 0x85A8U, 0x01E8U, 0x0068U, 0x0798U, 0x016AU, 0x0078U, 0x07A0U, 0x016AU, + 0x0068U, 0x0790U, 0x016AU, 0x0008U, 0x8B10U, 0x0168U, 0x0008U, 0xAB10U, 0x0168U, 0x000AU, + 0x0408U, 0x0169U, 0x0058U, 0x0000U, 0x0068U, 0x0000U, 0x0408U, 0x0169U, 0x0000U, 0x8B10U, + 0x0168U, 0x0001U, 0xAB10U, 0x0168U, 0x0000U, 0x01D8U, 0x0169U, 0x0080U, 0x0790U, 0x016AU, + 0x0018U, 0x07AAU, 0x006AU, 0x000AU, 0x0000U, 0x01E9U, 0x0008U, 0x8080U, 0x0108U, 0x000FU, + 0x0408U, 0x0169U, 0x000CU, 0x0000U, 0x0068U, 0x0009U, 0x0000U, 0x01A9U, 0x0000U, 0x0408U, + 0x0169U, 0x0000U, 0x8080U, 0x0108U, 0x0008U, 0x07AAU, 0x006AU, 0x0000U, 0x8568U, 0x0108U, + 0x00B7U, 0x0790U, 0x016AU, 0x001FU, 0x0000U, 0x0068U, 0x0008U, 0x8558U, 0x0168U, 0x000FU, + 0x0408U, 0x0169U, 0x000DU, 0x0000U, 0x0068U, 0x0000U, 0x0408U, 0x0169U, 0x0000U, 0x8558U, + 0x0168U, 0x0008U, 0x03C8U, 0x01A9U, 0x0003U, 0x0370U, 0x0129U, 0x0020U, 0x02AAU, 0x0009U, + 0x0008U, 0x00E8U, 0x0109U, 0x0000U, 0x8140U, 0x010CU, 0x0010U, 0x8138U, 0x0104U, 0x0008U, + 0x0448U, 0x0109U, 0x000FU, 0x07C0U, 0x0109U, 0x0000U, 0x00E8U, 0x0109U, 0x0047U, 0x0630U, + 0x0109U, 0x0008U, 0x0618U, 0x0109U, 0x0008U, 0x00E0U, 0x0109U, 0x0000U, 0x07C8U, 0x0109U, + 0x0008U, 0x8140U, 0x010CU, 0x0000U, 0x0478U, 0x0109U, 0x0000U, 0x0001U, 0x0008U, 0x0008U, + 0x0004U, 0x0000U, 0x0008U, 0x07C8U, 0x0109U, 0x0000U, 0x0400U, 0x0106U, 0x0400U, 0x0000U, + 0x002BU, 0x0069U, 0x0000U, 0x0101U, 0x0105U, 0x0107U, 0x010FU, 0x0202U, 0x020AU, 0x020BU, + 0x0002U, + }; +#endif /* STM32MP_DDR3_TYPE || STM32MP_DDR4_TYPE */ + +/* + * Loads PIE instruction sequence PHY registers + * @returns void + */ +void ddrphy_phyinit_loadpieprodcode(void) +{ + int i; + + for (i = 0; i < PRODCODE_SIZE; i++) { + mmio_write_16((uintptr_t)(DDRPHYC_BASE + (4U * prodcode_addr[i])), + prodcode_data[i]); + } +} diff --git a/drivers/st/ddr/phy/phyinit/src/ddrphy_phyinit_mapdrvstren.c b/drivers/st/ddr/phy/phyinit/src/ddrphy_phyinit_mapdrvstren.c new file mode 100644 index 000000000..f1eeb8208 --- /dev/null +++ b/drivers/st/ddr/phy/phyinit/src/ddrphy_phyinit_mapdrvstren.c @@ -0,0 +1,282 @@ +/* + * Copyright (C) 2021-2024, STMicroelectronics - All Rights Reserved + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include +#include + +#include + +#include + +/* + * Maps impedance values to register settings + * + * Reads the pull-up/pull-down driver impedance from drvstren_ohm input + * and encodes that value for the CSR field specified in targetcsr input, + * based on DDR protocol. + * + * @param[in] drvstren_ohm drive strenght / ODT impedance in Ohms + * + * @param[in] targetcsr Target CSR for the impedance value. on of following + * enum drvtype: + * - DRVSTRENFSDQP + * - DRVSTRENFSDQN + * - ODTSTRENP + * - ODTSTRENN + * - ADRVSTRENP + * - ADRVSTRENN + * + * \return >=0 value on success, else negative. + */ +int ddrphy_phyinit_mapdrvstren(uint32_t drvstren_ohm, enum drvtype targetcsr) +{ + int stren_setting = -1; + + if ((targetcsr == DRVSTRENFSDQP) || (targetcsr == DRVSTRENFSDQN)) { + if (drvstren_ohm == 0U) { + stren_setting = 0x00; /* High-impedance */ + } else if (drvstren_ohm < 29U) { + stren_setting = 0x3f; + } else if (drvstren_ohm < 31U) { + stren_setting = 0x3e; + } else if (drvstren_ohm < 33U) { + stren_setting = 0x3b; + } else if (drvstren_ohm < 35U) { + stren_setting = 0x3a; + } else if (drvstren_ohm < 38U) { + stren_setting = 0x39; + } else if (drvstren_ohm < 41U) { + stren_setting = 0x38; + } else if (drvstren_ohm < 45U) { + stren_setting = 0x1b; + } else if (drvstren_ohm < 50U) { + stren_setting = 0x1a; + } else if (drvstren_ohm < 56U) { + stren_setting = 0x19; + } else if (drvstren_ohm < 64U) { + stren_setting = 0x18; + } else if (drvstren_ohm < 74U) { + stren_setting = 0x0b; + } else if (drvstren_ohm < 88U) { + stren_setting = 0x0a; + } else if (drvstren_ohm < 108U) { + stren_setting = 0x09; + } else if (drvstren_ohm < 140U) { + stren_setting = 0x08; + } else if (drvstren_ohm < 200U) { + stren_setting = 0x03; + } else if (drvstren_ohm < 360U) { + stren_setting = 0x02; + } else if (drvstren_ohm < 481U) { + stren_setting = 0x01; + } else { + stren_setting = 0x00; /* High-impedance */ + } + } else if (targetcsr == ODTSTRENP) { +#if STM32MP_DDR3_TYPE + /* + * DDR3 - P and N has the same impedance and non-zero. + * user input is half the individual pull-up and pull-down impedances values + * because of parallel between them. + */ + if (drvstren_ohm == 0U) { + stren_setting = 0x00; /* High-impedance */ + } else if (drvstren_ohm < 15U) { + stren_setting = 0x3f; + } else if (drvstren_ohm < 16U) { + stren_setting = 0x3e; + } else if (drvstren_ohm < 17U) { + stren_setting = 0x3b; + } else if (drvstren_ohm < 18U) { + stren_setting = 0x3a; + } else if (drvstren_ohm < 20U) { + stren_setting = 0x39; + } else if (drvstren_ohm < 21U) { + stren_setting = 0x38; + } else if (drvstren_ohm < 23U) { + stren_setting = 0x1b; + } else if (drvstren_ohm < 26U) { + stren_setting = 0x1a; + } else if (drvstren_ohm < 29U) { + stren_setting = 0x19; + } else if (drvstren_ohm < 33U) { + stren_setting = 0x18; + } else if (drvstren_ohm < 38U) { + stren_setting = 0x0b; + } else if (drvstren_ohm < 45U) { + stren_setting = 0x0a; + } else if (drvstren_ohm < 55U) { + stren_setting = 0x09; + } else if (drvstren_ohm < 71U) { + stren_setting = 0x08; + } else if (drvstren_ohm < 101U) { + stren_setting = 0x03; + } else if (drvstren_ohm < 181U) { + stren_setting = 0x02; + } else if (drvstren_ohm < 241U) { + stren_setting = 0x01; + } else { + stren_setting = 0x00; /* High-impedance */ + } +#elif STM32MP_DDR4_TYPE + /* DDR4 - P is non-zero */ + if (drvstren_ohm == 0U) { + stren_setting = 0x00; /* High-impedance */ + } else if (drvstren_ohm < 29U) { + stren_setting = 0x3f; + } else if (drvstren_ohm < 31U) { + stren_setting = 0x3e; + } else if (drvstren_ohm < 33U) { + stren_setting = 0x3b; + } else if (drvstren_ohm < 35U) { + stren_setting = 0x3a; + } else if (drvstren_ohm < 38U) { + stren_setting = 0x39; + } else if (drvstren_ohm < 41U) { + stren_setting = 0x38; + } else if (drvstren_ohm < 45U) { + stren_setting = 0x1b; + } else if (drvstren_ohm < 50U) { + stren_setting = 0x1a; + } else if (drvstren_ohm < 56U) { + stren_setting = 0x19; + } else if (drvstren_ohm < 64U) { + stren_setting = 0x18; + } else if (drvstren_ohm < 74U) { + stren_setting = 0x0b; + } else if (drvstren_ohm < 88U) { + stren_setting = 0x0a; + } else if (drvstren_ohm < 108U) { + stren_setting = 0x09; + } else if (drvstren_ohm < 140U) { + stren_setting = 0x08; + } else if (drvstren_ohm < 200U) { + stren_setting = 0x03; + } else if (drvstren_ohm < 360U) { + stren_setting = 0x02; + } else if (drvstren_ohm < 481U) { + stren_setting = 0x01; + } else { + stren_setting = 0x00; /* High-impedance */ + } +#else /* STM32MP_LPDDR4_TYPE */ + /* LPDDR4 - P is high-Z */ + stren_setting = 0x00; /* High-impedance */ +#endif /* STM32MP_DDR3_TYPE */ + } else if (targetcsr == ODTSTRENN) { +#if STM32MP_DDR3_TYPE + /* + * DDR3 - P and N has the same impedance and non-zero. + * Times 2 of user input because of parallel pull-up and pull-down termination. + */ + if (drvstren_ohm == 0U) { + stren_setting = 0x00; /* High-impedance */ + } else if (drvstren_ohm < 15U) { + stren_setting = 0x3f; + } else if (drvstren_ohm < 16U) { + stren_setting = 0x3e; + } else if (drvstren_ohm < 17U) { + stren_setting = 0x3b; + } else if (drvstren_ohm < 18U) { + stren_setting = 0x3a; + } else if (drvstren_ohm < 20U) { + stren_setting = 0x39; + } else if (drvstren_ohm < 21U) { + stren_setting = 0x38; + } else if (drvstren_ohm < 23U) { + stren_setting = 0x1b; + } else if (drvstren_ohm < 26U) { + stren_setting = 0x1a; + } else if (drvstren_ohm < 29U) { + stren_setting = 0x19; + } else if (drvstren_ohm < 33U) { + stren_setting = 0x18; + } else if (drvstren_ohm < 38U) { + stren_setting = 0x0b; + } else if (drvstren_ohm < 45U) { + stren_setting = 0x0a; + } else if (drvstren_ohm < 55U) { + stren_setting = 0x09; + } else if (drvstren_ohm < 71U) { + stren_setting = 0x08; + } else if (drvstren_ohm < 101U) { + stren_setting = 0x03; + } else if (drvstren_ohm < 181U) { + stren_setting = 0x02; + } else if (drvstren_ohm < 241U) { + stren_setting = 0x01; + } else { + stren_setting = 0x00; /* High-impedance */ + } +#elif STM32MP_DDR4_TYPE + /* DDR4 - N is high-Z */ + stren_setting = 0x00; /* High-impedance */ +#else /* STM32MP_LPDDR4_TYPE */ + /* LPDDR4 - N is non-zero */ + if (drvstren_ohm == 0U) { + stren_setting = 0x00; /* High-impedance */ + } else if (drvstren_ohm < 29U) { + stren_setting = 0x3f; + } else if (drvstren_ohm < 31U) { + stren_setting = 0x3e; + } else if (drvstren_ohm < 33U) { + stren_setting = 0x3b; + } else if (drvstren_ohm < 35U) { + stren_setting = 0x3a; + } else if (drvstren_ohm < 38U) { + stren_setting = 0x39; + } else if (drvstren_ohm < 41U) { + stren_setting = 0x38; + } else if (drvstren_ohm < 45U) { + stren_setting = 0x1b; + } else if (drvstren_ohm < 50U) { + stren_setting = 0x1a; + } else if (drvstren_ohm < 56U) { + stren_setting = 0x19; + } else if (drvstren_ohm < 64U) { + stren_setting = 0x18; + } else if (drvstren_ohm < 74U) { + stren_setting = 0x0b; + } else if (drvstren_ohm < 88U) { + stren_setting = 0x0a; + } else if (drvstren_ohm < 108U) { + stren_setting = 0x09; + } else if (drvstren_ohm < 140U) { + stren_setting = 0x08; + } else if (drvstren_ohm < 200U) { + stren_setting = 0x03; + } else if (drvstren_ohm < 360U) { + stren_setting = 0x02; + } else if (drvstren_ohm < 481U) { + stren_setting = 0x01; + } else { + stren_setting = 0x00; /* High-impedance */ + } +#endif /* STM32MP_DDR3_TYPE */ + } else { + /* if ((targetcsr == ADRVSTRENP) || (targetcsr == ADRVSTRENN)) */ + if (drvstren_ohm == 120U) { + stren_setting = 0x00; + } else if (drvstren_ohm == 60U) { + stren_setting = 0x01; + } else if (drvstren_ohm == 40U) { + stren_setting = 0x03; + } else if (drvstren_ohm == 30U) { + stren_setting = 0x07; + } else if (drvstren_ohm == 24U) { + stren_setting = 0x0F; + } else if (drvstren_ohm == 20U) { + stren_setting = 0x1F; + } else { + ERROR("%s %d\n", __func__, __LINE__); + VERBOSE("%s userinputadvanced.atximpedance %u Ohms value is not valid.\n", + __func__, drvstren_ohm); + VERBOSE("Valid values are: 20, 24, 30, 40, 60 and 120 Ohms.\n"); + } + } + + return stren_setting; +} diff --git a/drivers/st/ddr/phy/phyinit/src/ddrphy_phyinit_progcsrskiptrain.c b/drivers/st/ddr/phy/phyinit/src/ddrphy_phyinit_progcsrskiptrain.c new file mode 100644 index 000000000..c9a71f4de --- /dev/null +++ b/drivers/st/ddr/phy/phyinit/src/ddrphy_phyinit_progcsrskiptrain.c @@ -0,0 +1,893 @@ +/* + * Copyright (C) 2021-2024, STMicroelectronics - All Rights Reserved + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include + +#include + +#include +#include + +#include + +#include + +struct phyinit_timings { + int tstaoff; + int tpdm; + int tcasl_add; +}; + +static struct phyinit_timings timings; + +/* + * Program dfimrl according to this formula: + * + * dfimrl = ceiling( (ARdPtrinitval*UI + phy_tx_insertion_dly + + * phy_rx_insertion_dly + PHY_Rx_Fifo_dly + tDQSCK + tstaoff) / + * dficlk_period) + * + * All terms in above equation specified in ps + * tDQSCK - determine from memory model + * tstaoff - determine from memory model + * phy_tx_insertion_dly = 200ps + * phy_rx_insertion_dly = 200ps + * phy_rx_fifo_dly = 200ps + 4UI + */ +static void dfimrl_program(struct stm32mp_ddr_config *config, struct pmu_smb_ddr_1d *mb_ddr_1d, + int ardptrinitval) +{ + uint32_t byte; + int dfimrl_in_dficlk; + int phy_rx_fifo_dly; + int phy_rx_insertion_dly = 200; + int phy_tx_insertion_dly = 200; + long long dficlk_period_x1000; + long long dfimrl_in_fs; + long long uifs; + uint16_t dfimrl; + + uifs = (1000 * 1000000) / ((int)config->uib.frequency * 2); + dficlk_period_x1000 = 4 * uifs; + + phy_rx_fifo_dly = (int)(((200 * 1000) + (4 * uifs)) / 1000); + + dfimrl_in_fs = (ardptrinitval * uifs) + + ((phy_tx_insertion_dly + phy_rx_insertion_dly + phy_rx_fifo_dly + + timings.tstaoff + timings.tcasl_add + timings.tpdm) * 1000); + + dfimrl_in_dficlk = (int)(dfimrl_in_fs / dficlk_period_x1000); + if ((dfimrl_in_fs % dficlk_period_x1000) != 0) { + dfimrl_in_dficlk++; + } + dfimrl = (uint16_t)(dfimrl_in_dficlk + mb_ddr_1d->dfimrlmargin); + + /* + * mmio_write_16((uintptr_t)(DDRPHYC_BASE + (4U * (TDBYTE | CBRD | CSR_DFIMRL_ADDR))), + * dfimrl); + */ + for (byte = 0U; byte < config->uib.numdbyte; byte++) { + uint32_t c_addr; + + c_addr = byte << 12; + mmio_write_16((uintptr_t)(DDRPHYC_BASE + (4U * (TDBYTE | c_addr | + CSR_DFIMRL_ADDR))), + dfimrl); + } + + mmio_write_16((uintptr_t)(DDRPHYC_BASE + (4U * (TMASTER | CSR_HWTMRL_ADDR))), dfimrl); +} + +/* + * Program txdqsdlytg0/1[9:0]: + * + * txdqsdlytg*[9:6] = floor( (4*UI + tstaoff) / UI) + * txdqsdlytg*[5:0] = ceiling( (tstaoff%UI / UI) * 32) + * + * tstaoff and UI expressed in ps + * + * For HMD and LPDDR4X and MEMCLK <= 533 mhz: + * txdqsdlytg*[9:6] = 0x5 + * + * For other dimm types, leave TDqsDlyTg*[9:0] at default 0x100 + * + * ppp_0001_cccc_uuuu_1101_0000 + * + * if DDR3 or DDR4 + * num_timingroup = numrank_dfi0; + * else + * num_timingroup = numrank_dfi0 + numrank_dfi1 * dfi1exists; + */ +static void txdqsdlytg_program(struct stm32mp_ddr_config *config, struct pmu_smb_ddr_1d *mb_ddr_1d, + uint16_t *txdqsdly) +{ + uint32_t byte; + int txdqsdlytg_5to0; /* Fine delay - 1/32UI per increment */ + int txdqsdlytg_9to6; /* Coarse delay - 1UI per increment */ + int txdqsdlytg_fine_default = 0; + int txdqsdlytg_coarse_default = 4; + long long tmp_value; + long long uifs; + + uifs = (1000 * 1000000) / ((int)config->uib.frequency * 2); + + txdqsdlytg_9to6 = (int)(((int)((txdqsdlytg_coarse_default * uifs) / 1000) + + timings.tstaoff + timings.tcasl_add + - timings.tpdm) / (int)(uifs / 1000)); + + tmp_value = fmodll(((txdqsdlytg_fine_default * uifs / 32) + + ((timings.tstaoff + timings.tcasl_add) * 1000) - + (timings.tpdm * 1000)), + uifs); + txdqsdlytg_5to0 = (int)(tmp_value / uifs * 32); + if ((tmp_value % uifs) != 0) { + txdqsdlytg_5to0++; + } + + /* Bit-5 of LCDL is no longer used, so bumping bit-5 of fine_dly up to coarse_dly */ + if (txdqsdlytg_5to0 >= 32) { + txdqsdlytg_9to6 = txdqsdlytg_9to6 + 1; + txdqsdlytg_5to0 = txdqsdlytg_5to0 - 32; + } + + *txdqsdly = (uint16_t)((txdqsdlytg_9to6 << 6) | txdqsdlytg_5to0); + + for (byte = 0U; byte < config->uib.numdbyte; byte++) { + uint32_t c_addr; + uint32_t nibble; + + c_addr = byte << 12; + for (nibble = 0U; nibble < 2U; nibble++) { + uint32_t u_addr; + + if (ddrphy_phyinit_isdbytedisabled(config, mb_ddr_1d, byte) != 0) { + continue; + } + + u_addr = nibble << 8; + +#if STM32MP_DDR3_TYPE || STM32MP_DDR4_TYPE + if ((mb_ddr_1d->cspresent & 0x1U) != 0U) { +#else /* STM32MP_LPDDR4_TYPE */ + if (((mb_ddr_1d->cspresentcha & 0x1U) | + (mb_ddr_1d->cspresentchb & 0x1U)) != 0U) { +#endif /* STM32MP_DDR3_TYPE || STM32MP_DDR4_TYPE */ + mmio_write_16((uintptr_t) + (DDRPHYC_BASE + (4U * (TDBYTE | c_addr | u_addr | + CSR_TXDQSDLYTG0_ADDR))), + *txdqsdly); + } + +#if STM32MP_LPDDR4_TYPE + if ((((mb_ddr_1d->cspresentcha & 0x2U) >> 1) | + ((mb_ddr_1d->cspresentchb & 0x2U) >> 1)) != 0U) { + mmio_write_16((uintptr_t) + (DDRPHYC_BASE + (4U * (TDBYTE | c_addr | u_addr | + CSR_TXDQSDLYTG1_ADDR))), + *txdqsdly); + } +#endif /* STM32MP_LPDDR4_TYPE */ + } + } +} + +/* + * ############################################################## + * + * Program txdqdlyTg0/1[8:0]: + * + * txdqdlyTg*[8:6] = floor( (txdqsdlytg*[5:0]*UI/32 + tDQS2DQ + 0.5UI) / UI) + * txdqdlyTg*[5:0] = ceil( ((txdqsdlytg*[5:0]*UI/32 + tDQS2DQ + 0.5UI)%UI / UI) * 32) + * + * ############################################################## + */ +static void txdqdlytg_program(struct stm32mp_ddr_config *config, struct pmu_smb_ddr_1d *mb_ddr_1d, + uint16_t txdqsdly) +{ + uint32_t byte; + int txdqdly_5to0; /* Fine delay - 1/32UI per increment */ + int txdqdly_8to6; /* Coarse delay - 1UI per increment */ + int txdqsdlytg_5to0; /* Fine delay - 1/32UI per increment */ + long long tmp_value; + long long uifs; + uint16_t txdqdly; + + uifs = (1000 * 1000000) / ((int)config->uib.frequency * 2); + + txdqsdlytg_5to0 = (int)txdqsdly & 0x3F; + + txdqdly_8to6 = (int)(((txdqsdlytg_5to0 * uifs / 32) + (uifs / 2)) / uifs); + tmp_value = fmodll(((txdqsdlytg_5to0 * uifs / 32) + (uifs / 2)), uifs); + txdqdly_5to0 = (int)(((tmp_value * 32) / uifs)); + if ((tmp_value % uifs) != 0) { + txdqdly_5to0++; + } + + /* Bit-5 of LCDL is no longer used, so bumping bit-5 of fine_dly up to coarse_dly */ + if (txdqdly_5to0 >= 32) { + txdqdly_8to6 = txdqdly_8to6 + 1; + txdqdly_5to0 = txdqdly_5to0 - 32; + } + + txdqdly = (uint16_t)((txdqdly_8to6 << 6) | txdqdly_5to0); + + for (byte = 0U; byte < config->uib.numdbyte; byte++) { + uint32_t c_addr; + uint32_t lane; + + c_addr = byte << 12; + for (lane = 0U; lane < 9U; lane++) { + uint32_t r_addr; + + if (ddrphy_phyinit_isdbytedisabled(config, mb_ddr_1d, byte) != 0) { + continue; + } + + r_addr = lane << 8; + +#if STM32MP_DDR3_TYPE || STM32MP_DDR4_TYPE + if ((mb_ddr_1d->cspresent & 0x1U) != 0U) { +#else /* STM32MP_LPDDR4_TYPE */ + if (((mb_ddr_1d->cspresentcha & 0x1U) | + (mb_ddr_1d->cspresentchb & 0x1U)) != 0U) { +#endif /* STM32MP_DDR3_TYPE || STM32MP_DDR4_TYPE */ + mmio_write_16((uintptr_t) + (DDRPHYC_BASE + (4U * (TDBYTE | c_addr | r_addr | + CSR_TXDQDLYTG0_ADDR))), + txdqdly); + } + +#if STM32MP_LPDDR4_TYPE + if ((((mb_ddr_1d->cspresentcha & 0x2U) >> 1) | + ((mb_ddr_1d->cspresentchb & 0x2U) >> 1)) != 0U) { + mmio_write_16((uintptr_t) + (DDRPHYC_BASE + (4U * (TDBYTE | c_addr | r_addr | + CSR_TXDQDLYTG1_ADDR))), + txdqdly); + } +#endif /* STM32MP_LPDDR4_TYPE */ + } + } +} + +/* + * Program rxendly0/1[10:0]: + * + * rxendly[10:6] = floor( (4*UI + tDQSCK + tstaoff) / UI) + * rxendly[5:0] = ceil( ((tDQSCK + tstaoff) % UI) * 32) + * + * tDQSCK, tstaoff and UI expressed in ps + */ +static void rxendly_program(struct stm32mp_ddr_config *config, struct pmu_smb_ddr_1d *mb_ddr_1d) +{ + int rxendly_coarse_default = 4; + int rxendly_fine_default = 0; + + int backoff_x1000 __maybe_unused; + int zerobackoff_x1000 __maybe_unused; + uint32_t byte; + int rxendly_10to6; /* Coarse delay - 1UI per increment */ + int rxendly_5to0; /* Fine delay - 1/32UI per increment */ + int totfinestep; + long long finestepfs; /* Fine steps in fs */ + long long rxendly_offset_x1000000 = 0; /* 0 Offset is 1UI before the first DQS. */ + long long totfs; + long long uifs; + uint16_t rxendly; + + uifs = (1000 * 1000000) / ((int)config->uib.frequency * 2); + +#if STM32MP_LPDDR4_TYPE + /* Compensate for pptenrxenbackoff */ + zerobackoff_x1000 = (1000 * 24) / 32; + if (config->uia.lp4rxpreamblemode == 1U) { + backoff_x1000 = 1000 - ((1000 * 2) / 32); + } else { + backoff_x1000 = (1000 * (int)config->uia.rxenbackoff) - ((1000 * 2) / 32); + } + + if (config->uia.disableretraining == 0U) { + rxendly_offset_x1000000 = config->uib.frequency < 333U ? + backoff_x1000 * uifs : zerobackoff_x1000 * uifs; + } else { + rxendly_offset_x1000000 = zerobackoff_x1000 * uifs; + } +#endif /* STM32MP_LPDDR4_TYPE */ + + finestepfs = uifs / 32; + totfs = ((32 * rxendly_coarse_default * finestepfs) + + (rxendly_fine_default * finestepfs) + + ((timings.tstaoff + timings.tcasl_add + + timings.tpdm) * 1000) + (rxendly_offset_x1000000 / 1000)); + totfinestep = totfs / finestepfs; + + rxendly_10to6 = totfinestep / 32; + rxendly_5to0 = fmodi(totfinestep, 32); + + /* Bit-5 of LCDL is no longer used, so bumping bit-5 of fine_dly up to coarse_dly */ + if (rxendly_5to0 >= 32) { + rxendly_10to6 = rxendly_10to6 + 1; + rxendly_5to0 = rxendly_5to0 - 32; + } + + rxendly = (uint16_t)((rxendly_10to6 << 6) | rxendly_5to0); + + for (byte = 0U; byte < config->uib.numdbyte; byte++) { + uint32_t c_addr; + uint32_t nibble; + + c_addr = byte << 12; + for (nibble = 0U; nibble < 2U; nibble++) { + uint32_t u_addr; + + if (ddrphy_phyinit_isdbytedisabled(config, mb_ddr_1d, byte) != 0) { + continue; + } + + u_addr = nibble << 8; + +#if STM32MP_DDR3_TYPE || STM32MP_DDR4_TYPE + if ((mb_ddr_1d->cspresent & 0x1U) != 0) { +#else /* STM32MP_LPDDR4_TYPE */ + if (((mb_ddr_1d->cspresentcha & 0x1U) | + (mb_ddr_1d->cspresentchb & 0x1U)) != 0U) { +#endif /* STM32MP_DDR3_TYPE || STM32MP_DDR4_TYPE */ + mmio_write_16((uintptr_t) + (DDRPHYC_BASE + (4U * (TDBYTE | c_addr | u_addr | + CSR_RXENDLYTG0_ADDR))), + rxendly); + } + +#if STM32MP_LPDDR4_TYPE + if ((((mb_ddr_1d->cspresentcha & 0x2U) >> 1) | + ((mb_ddr_1d->cspresentchb & 0x2U) >> 1)) != 0U) { + mmio_write_16((uintptr_t) + (DDRPHYC_BASE + (4U * (TDBYTE | c_addr | u_addr | + CSR_RXENDLYTG1_ADDR))), + rxendly); + } +#endif /* STM32MP_LPDDR4_TYPE */ + } + } +} + +#if STM32MP_LPDDR4_TYPE +/* + * Programming Seq0BGPR1/2/3 for LPDDR4 + */ +static void seq0bgpr_program(struct stm32mp_ddr_config *config) +{ + uint32_t extradly = 3U; + uint32_t rl = 0U; /* Computed read latency */ + uint32_t wl = 0U; /* Computed write latency */ + uint16_t mr_dbi_rd; /* Extracted field from MR */ + uint16_t mr_rl; + uint16_t mr_wl; + uint16_t mr_wls; + uint16_t regdata; + + mr_rl = (uint16_t)config->uia.lp4rl; /* RL[2:0] */ + mr_wl = (uint16_t)config->uia.lp4wl; /* WL[5:3] */ + mr_wls = (uint16_t)config->uia.lp4wls; /* WLS */ + mr_dbi_rd = (uint16_t)config->uia.lp4dbird; /* DBI-RD */ + + switch ((mr_dbi_rd << 3) | mr_rl) { + /* DBI-RD Disabled */ + case 0U: + rl = 6U; + break; + case 1U: + rl = 10U; + break; + case 2U: + rl = 14U; + break; + case 3U: + rl = 20U; + break; + case 4U: + rl = 24U; + break; + case 5U: + rl = 28U; + break; + case 6U: + rl = 32U; + break; + case 7U: + rl = 36U; + break; + /* DBI-RD Enabled */ + case 8U: + rl = 6U; + break; + case 9U: + rl = 12U; + break; + case 10U: + rl = 16U; + break; + case 11U: + rl = 22U; + break; + case 12U: + rl = 28U; + break; + case 13U: + rl = 32U; + break; + case 14U: + rl = 36U; + break; + case 15U: + rl = 40U; + break; + default: + rl = 6U; + break; + } + + switch ((mr_wls << 3) | mr_wl) { + /* DBI-RD Disabled */ + case 0U: + wl = 4U; + break; + case 1U: + wl = 6U; + break; + case 2U: + wl = 8U; + break; + case 3U: + wl = 10U; + break; + case 4U: + wl = 12U; + break; + case 5U: + wl = 14U; + break; + case 6U: + wl = 16U; + break; + case 7U: + wl = 18U; + break; + /* DBI-RD Enabled */ + case 8U: + wl = 4U; + break; + case 9U: + wl = 8U; + break; + case 10U: + wl = 12U; + break; + case 11U: + wl = 18U; + break; + case 12U: + wl = 22U; + break; + case 13U: + wl = 26U; + break; + case 14U: + wl = 30U; + break; + case 15U: + wl = 34U; + break; + default: + wl = 4U; + break; + } + + /* Program Seq0b_GPRx */ + regdata = (uint16_t)((rl - 5U + extradly) << CSR_ACSMRCASLAT_LSB); + mmio_write_16((uintptr_t)(DDRPHYC_BASE + (4U * (P0 | C0 | TINITENG | R2 | + CSR_SEQ0BGPR1_ADDR))), + regdata); + + regdata = (uint16_t)((wl - 5U + extradly) << CSR_ACSMWCASLAT_LSB); + mmio_write_16((uintptr_t)(DDRPHYC_BASE + (4U * (P0 | C0 | TINITENG | R2 | + CSR_SEQ0BGPR2_ADDR))), + regdata); + + regdata = (uint16_t)((rl - 5U + extradly + 4U + 8U) << CSR_ACSMRCASLAT_LSB); + mmio_write_16((uintptr_t)(DDRPHYC_BASE + (4U * (P0 | C0 | TINITENG | R2 | + CSR_SEQ0BGPR3_ADDR))), + regdata); +} + +/* + * Program hwtlpcsena and hwtlpcsenb based on number of ranks per channel + * Applicable only for LPDDR4. These CSRs have no effect for DDR3/4. + * + * CSRs to program: + * hwtlpcsena + * hwtlpcsenb + * + * User input dependencies: + * config->uib.numrank_dfi0 + * config->uib.numrank_dfi1 + * config->uib.dfi1exists + * config->uib.numactivedbytedfi1 + */ +static void hwtlpcsen_program(struct stm32mp_ddr_config *config) +{ + uint16_t hwtlpcsena; + uint16_t hwtlpcsenb; + + /* Channel A - 1'b01 if signal-rank, 2'b11 if dual-rank */ + hwtlpcsena = (uint16_t)config->uib.numrank_dfi0 | 0x1U; + mmio_write_16((uintptr_t)(DDRPHYC_BASE + (4U * (TMASTER | CSR_HWTLPCSENA_ADDR))), + hwtlpcsena); + + /* + * Channel B - 1'b01 if signal-rank, 2'b11 if dual-rank + * If DFI1 exists but disabled, numrank_dfi0 is used to program CsEnB + */ + if ((config->uib.dfi1exists != 0U) && (config->uib.numactivedbytedfi1 == 0U)) { + hwtlpcsenb = (uint16_t)config->uib.numrank_dfi0 | 0x1U; + mmio_write_16((uintptr_t)(DDRPHYC_BASE + (4U * (TMASTER | CSR_HWTLPCSENB_ADDR))), + hwtlpcsenb); + } else if ((config->uib.dfi1exists != 0U) && (config->uib.numactivedbytedfi1 > 0U)) { + hwtlpcsenb = (uint16_t)config->uib.numrank_dfi1 | 0x1U; + mmio_write_16((uintptr_t)(DDRPHYC_BASE + (4U * (TMASTER | CSR_HWTLPCSENB_ADDR))), + hwtlpcsenb); + } else { + /* Disable Channel B */ + hwtlpcsenb = 0x0U; + mmio_write_16((uintptr_t)(DDRPHYC_BASE + (4U * (TMASTER | CSR_HWTLPCSENB_ADDR))), + hwtlpcsenb); + } +} + +/* + * Program pptdqscntinvtrntg0 and pptdqscntinvtrntg1 + * Calculated based on tDQS2DQ and Frequencey + * Applicable to LPDDR4 only + * + * 65536*(tdqs2dq_value_rank_chan*2)/(2*2048*UI(ps)_int) + * + * CSRs to program: + * pptdqscntinvtrntg0 + * pptdqscntinvtrntg1 + * + * User input dependencies: + * config->uib.numrank_dfi0 + * config->uib.numrank_dfi1 + * config->uib.dfi1exists + * config->uib.numdbyte + */ +static void pptdqscntinvtrntg_program(struct stm32mp_ddr_config *config) +{ + uint32_t numrank_total = config->uib.numrank_dfi0; + uint32_t rank; + + /* Calculate total number of timing groups (ranks) */ + if (config->uib.dfi1exists != 0U) { + numrank_total += config->uib.numrank_dfi1; + } + + /* Set per timing group */ + for (rank = 0U; rank < numrank_total; rank++) { + uint32_t byte; + + for (byte = 0U; byte < config->uib.numdbyte; byte++) { + uint32_t c_addr; + + c_addr = byte << 12; + if (rank == 0U) { + mmio_write_16((uintptr_t) + (DDRPHYC_BASE + (4U * (TDBYTE | c_addr | + CSR_PPTDQSCNTINVTRNTG0_ADDR))), + 0U); + } else if (rank == 1U) { + mmio_write_16((uintptr_t) + (DDRPHYC_BASE + (4U * (TDBYTE | c_addr | + CSR_PPTDQSCNTINVTRNTG1_ADDR))), + 0U); + } + } + } +} + +/* + * CSRs to program: + * PptCtlStatic:: DOCByteSelTg0/1 + * :: pptenrxenbackoff + * + * User input dependencies:: + * config->uib.numdbyte + * config->uib.numrank_dfi0 + * config->uib.numrank_dfi1 + * config->uia.lp4rxpreamblemode + * config->uia.rxenbackoff + * config->uia.drambyteswap + */ +static void pptctlstatic_program(struct stm32mp_ddr_config *config) +{ + uint32_t byte; + uint32_t pptenrxenbackoff; + + /* + * The customer will setup some fields in this csr so the fw needs to do a + * read-modify-write here. + */ + + if (config->uia.lp4rxpreamblemode == 1U) { + /* Rx-preamble mode for PS0 */ + /* Programming PptCtlStatic detected toggling preamble */ + pptenrxenbackoff = 0x1U; /* Toggling RD_PRE */ + } else { + pptenrxenbackoff = config->uia.rxenbackoff; /* Static RD_PRE */ + } + + for (byte = 0U; byte < config->uib.numdbyte; byte++) { + uint32_t c_addr; + uint16_t regdata; + uint8_t pptentg1; + uint32_t docbytetg0; + uint32_t docbytetg1; + + /* Each Dbyte could have a different configuration */ + c_addr = byte * C1; + if ((byte % 2) == 0) { + docbytetg0 = 0x1U & (config->uia.drambyteswap >> byte); + docbytetg1 = 0x1U & (config->uia.drambyteswap >> byte); + } else { + docbytetg0 = 0x1U & (~(config->uia.drambyteswap >> byte)); + docbytetg1 = 0x1U & (~(config->uia.drambyteswap >> byte)); + } + + pptentg1 = ((config->uib.numrank_dfi0 == 2U) || (config->uib.numrank_dfi1 == 2U)) ? + 0x1U : 0x0U; + regdata = (uint16_t)((0x1U << CSR_PPTENDQS2DQTG0_LSB) | + (pptentg1 << CSR_PPTENDQS2DQTG1_LSB) | + (0x1U << CSR_PPTENRXENDLYTG0_LSB) | + (pptentg1 << CSR_PPTENRXENDLYTG1_LSB) | + (pptenrxenbackoff << CSR_PPTENRXENBACKOFF_LSB) | + (docbytetg0 << CSR_DOCBYTESELTG0_LSB) | + (docbytetg1 << CSR_DOCBYTESELTG1_LSB)); + + mmio_write_16((uintptr_t)(DDRPHYC_BASE + (4U * (c_addr | TDBYTE | + CSR_PPTCTLSTATIC_ADDR))), + regdata); + } +} +#endif /* STM32MP_LPDDR4_TYPE */ + +/* + * Program hwtcamode based on dram type + * + * CSRs to program: + * hwtcamode::hwtlp3camode + * ::hwtd4camode + * ::hwtlp4camode + * ::hwtd4altcamode + * ::hwtcsinvert + * ::hwtdbiinvert + */ +static void hwtcamode_program(void) +{ + uint32_t hwtlp3camode = 0U; + uint32_t hwtd4camode = 0U; + uint32_t hwtlp4camode = 0U; + uint32_t hwtd4altcamode = 0U; + uint32_t hwtcsinvert = 0U; + uint32_t hwtdbiinvert = 0U; + uint16_t hwtcamode; + +#if STM32MP_DDR4_TYPE + hwtd4camode = 1U; +#elif STM32MP_LPDDR4_TYPE + hwtlp4camode = 1U; + hwtcsinvert = 1U; + hwtdbiinvert = 1U; +#else /* STM32MP_DDR3_TYPE */ + /* Nothing to declare */ +#endif /* STM32MP_DDR4_TYPE */ + + hwtcamode = (uint16_t)((hwtdbiinvert << CSR_HWTDBIINVERT_LSB) | + (hwtcsinvert << CSR_HWTCSINVERT_LSB) | + (hwtd4altcamode << CSR_HWTD4ALTCAMODE_LSB) | + (hwtlp4camode << CSR_HWTLP4CAMODE_LSB) | + (hwtd4camode << CSR_HWTD4CAMODE_LSB) | + (hwtlp3camode << CSR_HWTLP3CAMODE_LSB)); + + mmio_write_16((uintptr_t)(DDRPHYC_BASE + (4U * (TMASTER | CSR_HWTCAMODE_ADDR))), hwtcamode); +} + +/* + * Program DllGainCtl and DllLockParam based on frequency + */ +static void dllgainctl_dlllockparam_program(struct stm32mp_ddr_config *config) +{ + uint32_t dllgainiv; + uint32_t dllgaintv; + uint32_t lcdlseed; + uint32_t memck_freq; + uint32_t stepsize_x10 = 47U; /* + * Nominal stepsize, in units of tenths of a ps, + * if nominal=4.7ps use 47 + */ + uint16_t wddllgainctl; + uint16_t wddlllockparam; + + memck_freq = config->uib.frequency; + + /* + * lcdlseed = ((1000000/memck_freq)/2)/lcdl_stepsize ... + * where default lcdl_stepsize=4.7 in simulation. + */ + if (memck_freq >= 1200U) { + dllgainiv = 0x04U; + dllgaintv = 0x05U; + } else if (memck_freq >= 800U) { + dllgainiv = 0x03U; + dllgaintv = 0x05U; + } else if (memck_freq >= 532U) { + dllgainiv = 0x02U; + dllgaintv = 0x04U; + } else if (memck_freq >= 332U) { + dllgainiv = 0x01U; + dllgaintv = 0x03U; + } else { + dllgainiv = 0x00U; + dllgaintv = 0x02U; + } + + /* + * lcdlseed= (1000000/(2*memck_freq)) * (100/(120*(stepsize_nominal))); + * *100/105 is to bias the seed low. + */ + lcdlseed = (1000000U * 10U * 100U) / (2U * memck_freq * stepsize_x10 * 105U); + + if (lcdlseed > (511U - 32U)) { + lcdlseed = 511U - 32U; + } + + if (lcdlseed < 32U) { + lcdlseed = 32U; + } + + wddllgainctl = (uint16_t)((CSR_DLLGAINTV_MASK & (dllgaintv << CSR_DLLGAINTV_LSB)) | + (CSR_DLLGAINIV_MASK & (dllgainiv << CSR_DLLGAINIV_LSB))); + + mmio_write_16((uintptr_t)(DDRPHYC_BASE + (4U * (TMASTER | CSR_DLLGAINCTL_ADDR))), + wddllgainctl); + + wddlllockparam = (uint16_t)((CSR_LCDLSEED0_MASK & (lcdlseed << CSR_LCDLSEED0_LSB)) | + (CSR_DISDLLGAINIVSEED_MASK & 0xFFFFU)); + + mmio_write_16((uintptr_t)(DDRPHYC_BASE + (4U * (TMASTER | CSR_DLLLOCKPARAM_ADDR))), + wddlllockparam); +} + +/* + * Program AcsmCtrl23 for Fw and Ppt. + * + * CSRs to program: + * AcsmCtrl23::AcsmCsMask + * AcsmCsMode + */ +static void acsmctrl23_program(void) +{ + uint16_t regdata; + + regdata = (0x0FU << CSR_ACSMCSMASK_LSB) | (0x1U << CSR_ACSMCSMODE_LSB); + mmio_write_16((uintptr_t)(DDRPHYC_BASE + (4U * (C0 | TACSM | CSR_ACSMCTRL23_ADDR))), + regdata); +} + +/* + * Set PllForceCal to 1 and PllDacValIn to some arbitrary value + */ +static void pllforcecal_plldacvalin_program(void) +{ + uint32_t dacval_in = 0x10U; + uint32_t force_cal = 0x1U; + uint32_t pllencal = 0x1U; + uint32_t maxrange = 0x1FU; + uint16_t pllctrl3_gpr; + uint16_t pllctrl3_startup; + + pllctrl3_startup = (uint16_t)((dacval_in << CSR_PLLDACVALIN_LSB) | + (maxrange << CSR_PLLMAXRANGE_LSB)); + pllctrl3_gpr = pllctrl3_startup | (uint16_t)((force_cal << CSR_PLLFORCECAL_LSB) | + (pllencal << CSR_PLLENCAL_LSB)); + + mmio_write_16((uintptr_t)(DDRPHYC_BASE + (4U * (TMASTER | CSR_PLLCTRL3_ADDR))), + pllctrl3_startup); + mmio_write_16((uintptr_t)(DDRPHYC_BASE + (4U * (TINITENG | CSR_SEQ0BGPR6_ADDR))), + pllctrl3_gpr); +} + +/* + * This function programs registers that are normally set by training + * firmware. + * + * This function is used in place of running 1D or 1D training steps. PhyInit + * calls this function when skip_train = true. In that case, PhyInit does not + * execute training firmware and this function is called instead to program + * PHY registers according to DRAM timing parameters specified in userInput + * data structure. See documentation of ddrphy_phyinit_struct.h file + * details of timing parameters available in skip training. + * + * \warning ddrphy_phyinit_progcsrskiptrain() only supports zero board + * delay model. If system board delays are set or randomized, full 1D or 1D + * initialization flow must be executed. + * + * This function replaces these steps in the PHY Initialization sequence: + * - (E) Set the PHY input clocks to the desired frequency + * - (F) Write the Message Block parameters for the training firmware + * - (G) Execute the Training Firmware + * - (H) Read the Message Block results + * + * \returns \c void + */ +void ddrphy_phyinit_progcsrskiptrain(struct stm32mp_ddr_config *config, + struct pmu_smb_ddr_1d *mb_ddr_1d, uint32_t ardptrinitval) +{ + uint16_t txdqsdly; + + /* + * Program ATxDlY + * For DDR4, DDR3 and LPDDR4, leave AtxDly[6:0] at default (0x0) + */ + + dfimrl_program(config, mb_ddr_1d, ardptrinitval); + + txdqsdlytg_program(config, mb_ddr_1d, &txdqsdly); + + txdqdlytg_program(config, mb_ddr_1d, txdqsdly); + + rxendly_program(config, mb_ddr_1d); + +#if STM32MP_LPDDR4_TYPE + seq0bgpr_program(config); + + hwtlpcsen_program(config); + + pptdqscntinvtrntg_program(config); + + pptctlstatic_program(config); +#endif /* STM32MP_LPDDR4_TYPE */ + + hwtcamode_program(); + + dllgainctl_dlllockparam_program(config); + + acsmctrl23_program(); + + pllforcecal_plldacvalin_program(); + + /* + * ############################################################## + * + * Setting PhyInLP3 to 0 to cause PIE to execute LP2 sequence instead of INIT on first + * dfi_init_start. + * This prevents any DRAM commands before DRAM is initialized, which is the case for + * skip_train. + * + * Moved to here from dddrphy_phyinit_I_loadPIEImage() + * These should not be needed on S3-exit + * + * Note this executes for SkipTrain only, *not* DevInit+SkipTrain + * DevInit+SkipTrain already initializes DRAM and thus don't need to avoid DRAM commands + * + * ############################################################## + */ + + /* + * Special skipTraining configuration to Prevent DRAM Commands on the first dfi + * status interface handshake. In order to see this behavior, the first dfi_freq + * should be in the range of 0x0f < dfi_freq_sel[4:0] < 0x14. + */ + mmio_write_16((uintptr_t)(DDRPHYC_BASE + (4U * (TINITENG | CSR_PHYINLP3_ADDR))), 0x0U); +} diff --git a/drivers/st/ddr/phy/phyinit/src/ddrphy_phyinit_reginterface.c b/drivers/st/ddr/phy/phyinit/src/ddrphy_phyinit_reginterface.c new file mode 100644 index 000000000..21400f721 --- /dev/null +++ b/drivers/st/ddr/phy/phyinit/src/ddrphy_phyinit_reginterface.c @@ -0,0 +1,170 @@ +/* + * Copyright (C) 2021-2024, STMicroelectronics - All Rights Reserved + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* + * This file provides a group of functions that are used to track PHY register + * writes by intercepting io_write16 function calls. Once the registers are + * tracked, their value can be saved at a given time spot, and restored later + * as required. This implementation is useful to capture any PHY register + * programing in any function during PHY initialization. + */ + +#include + +#include + +#include + +#include + +#include + +/* + * MAX_NUM_RET_REGS default Max number of retention registers. + * + * This define is only used by the PhyInit Register interface to define the max + * amount of registered that can be saved. The user may increase this variable + * as desired if a larger number of registers need to be restored. + */ +#if STM32MP_DDR3_TYPE || STM32MP_DDR4_TYPE +#define MAX_NUM_RET_REGS 129 +#else /* STM32MP_LPDDR4_TYPE */ +#define MAX_NUM_RET_REGS 283 +#endif /* STM32MP_DDR3_TYPE || STM32MP_DDR4_TYPE */ + +/* + * Array of Address/value pairs used to store register values for the purpose + * of retention restore. + */ +#define RETREG_AREA (MAX_NUM_RET_REGS + 1) * sizeof(struct reg_addr_val) +#define RETREG_BASE RETRAM_BASE + RETRAM_SIZE - RETREG_AREA + +static int *retregsize = (int *)(RETREG_BASE); +static struct reg_addr_val *retreglist = (struct reg_addr_val *)(RETREG_BASE + sizeof(int)); + +static int numregsaved; /* Current Number of registers saved. */ +static int tracken = 1; /* Enabled tracking of registers */ + +/* + * Tags a register if tracking is enabled in the register + * interface. + * + * During PhyInit registers writes, keeps track of address + * for the purpose of restoring the PHY register state during PHY + * retention exit process. Tracking can be turned on/off via the + * ddrphy_phyinit_reginterface STARTTRACK, STOPTRACK instructions. By + * default tracking is always turned on. + * + * \return 0 on success. + */ +int ddrphy_phyinit_trackreg(uint32_t adr) +{ + int regindx = 0; + + /* Return if tracking is disabled */ + if (tracken == 0) { + return 0; + } + + /* Search register address within the array */ + for (regindx = 0; regindx < numregsaved; regindx++) { + if (retreglist[regindx].address == adr) { + /* Register found */ + return 0; + } + } + + /* Register not found, so add it */ + if (numregsaved > MAX_NUM_RET_REGS) { + ERROR("numregsaved > MAX_NUM_RET_REGS\n"); + VERBOSE("[ddrphy_phyinit_reginterface:%s]\n", __func__); + VERBOSE("Max Number of Restore Registers reached: %d.\n", numregsaved); + VERBOSE("Please recompile PhyInit with larger MAX_NUM_RET_REG value.\n"); + return -1; + } + + retreglist[regindx].address = adr; + numregsaved++; + + return 0; +} + +/* + * Register interface function used to track, save and restore retention registers. + * + * ### Usage + * Register tracking is enabled by calling: + * + * \code + * ddrphy_phyinit_reginterface(STARTTRACK,0,0); + * \endcode + * + * from this point on any call to mmio_write_16() in + * return will be capture by the register interface via a call to + * ddrphy_phyinit_trackreg(). Tracking is disabled by calling: + * + * \code + * ddrphy_phyinit_reginterface(STOPTRACK,0,0); + * \endcode + * + * On calling this function, register write via mmio_write_16 are no longer tracked until a + * STARTTRACK call is made. Once all the register write are complete, SAVEREGS + * command can be issue to save register values into the internal data array of + * the register interface. Upon retention exit RESTOREREGS are command can be + * used to issue register write commands to the PHY based on values stored in + * the array. + * \code + * ddrphy_phyinit_reginterface(SAVEREGS,0,0); + * ddrphy_phyinit_reginterface(RESTOREREGS,0,0); + * \endcode + * \return 0 on success. + */ +int ddrphy_phyinit_reginterface(enum reginstr myreginstr, uint32_t adr, uint16_t dat) +{ + if (myreginstr == SAVEREGS) { + int regindx; + + /* + * Go through all the tracked registers, issue a register read and place + * the result in the data structure for future recovery. + */ + for (regindx = 0; regindx < numregsaved; regindx++) { + uint16_t data; + + data = mmio_read_16((uintptr_t)(DDRPHYC_BASE + + (4U * retreglist[regindx].address))); + retreglist[regindx].value = data; + } + + *retregsize = numregsaved; + + return 0; + } else if (myreginstr == RESTOREREGS) { + int regindx; + + /* + * Write PHY registers based on Address, Data value pairs stores in + * retreglist. + */ + for (regindx = 0; regindx < *retregsize; regindx++) { + mmio_write_16((uintptr_t) + (DDRPHYC_BASE + (4U * retreglist[regindx].address)), + retreglist[regindx].value); + } + + return 0; + } else if (myreginstr == STARTTRACK) { + /* Enable tracking */ + tracken = 1; + return 0; + } else if (myreginstr == STOPTRACK) { + /* Disable tracking */ + tracken = 0; + return 0; + } else { + return -1; + } +} diff --git a/drivers/st/ddr/phy/phyinit/src/ddrphy_phyinit_restore_sequence.c b/drivers/st/ddr/phy/phyinit/src/ddrphy_phyinit_restore_sequence.c new file mode 100644 index 000000000..cddb95528 --- /dev/null +++ b/drivers/st/ddr/phy/phyinit/src/ddrphy_phyinit_restore_sequence.c @@ -0,0 +1,78 @@ +/* + * Copyright (C) 2021-2024, STMicroelectronics - All Rights Reserved + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include + +#include + +#include + +#include + +/* + * This function implements the register restore portion of S3/IO + * retention sequence. + * + * \note This function requiers the runtime_config.reten=1 to enable PhyInit exit retention feature. + * This variable can be set as in + * \return 0 on completion of the sequence, EXIT_FAILURE on error. + */ +int ddrphy_phyinit_restore_sequence(void) +{ + int ret; + + /* + * Before you call this functions perform the following: + * -------------------------------------------------------------------------- + * -# Bring up VDD, VDDQ should already be up + * -# Since the CKE* and MEMRESET pin state must be protected, special care + * must be taken to ensure that the following signals + * - atpg_mode = 1'b0 + * - PwrOkIn = 1'b0 + * + * -# The {BypassModeEn*, WRSTN} signals may be defined at VDD power-on, but + * must be driven to ZERO at least 10ns prior to the asserting edge of PwrOkIn. + * + * -# Start Clocks and Reset the PHY + * This step is identical to ddrphy_phyinit_usercustom_b_startclockresetphy() + */ + + /* Write the MicroContMuxSel CSR to 0x0 to allow access to the internal CSRs */ + mmio_write_16((uintptr_t)(DDRPHYC_BASE + (4U * (TAPBONLY | CSR_MICROCONTMUXSEL_ADDR))), + 0x0U); + + /* + * Write the UcclkHclkEnables CSR to 0x3 to enable all the clocks so the reads can + * complete. + */ + mmio_write_16((uintptr_t)(DDRPHYC_BASE + (4U * (TDRTUB | CSR_UCCLKHCLKENABLES_ADDR))), + 0x3U); + + /* + * Assert CalZap to force impedance calibration FSM to idle. + * De-asserted as part of dfi_init_start/complete handshake by the PIE when DfiClk is valid. + */ + mmio_write_16((uintptr_t)(DDRPHYC_BASE + (4U * (TMASTER | CSR_CALZAP_ADDR))), 0x1U); + + /* Issue register writes to restore registers values */ + ret = ddrphy_phyinit_reginterface(RESTOREREGS, 0U, 0U); + if (ret != 0) { + return ret; + } + + /* + * Write the UcclkHclkEnables CSR to disable the appropriate clocks after all reads done. + * Disabling Ucclk (PMU) and Hclk (training hardware). + */ + mmio_write_16((uintptr_t)(DDRPHYC_BASE + (4U * (TDRTUB | CSR_UCCLKHCLKENABLES_ADDR))), + 0x0U); + + /* Write the MicroContMuxSel CSR to 0x1 to isolate the internal CSRs during mission mode */ + mmio_write_16((uintptr_t)(DDRPHYC_BASE + (4U * (TAPBONLY | CSR_MICROCONTMUXSEL_ADDR))), + 0x1U); + + return 0; +} diff --git a/drivers/st/ddr/phy/phyinit/src/ddrphy_phyinit_sequence.c b/drivers/st/ddr/phy/phyinit/src/ddrphy_phyinit_sequence.c new file mode 100644 index 000000000..adc437730 --- /dev/null +++ b/drivers/st/ddr/phy/phyinit/src/ddrphy_phyinit_sequence.c @@ -0,0 +1,121 @@ +/* + * Copyright (C) 2021-2024, STMicroelectronics - All Rights Reserved + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include + +#include + +#include + +/* + * This function implements the flow of PhyInit software to initialize the PHY. + * + * The execution sequence follows the overview figure provided in the Reference Manual. + * + * \returns 0 on completion of the sequence, EXIT_FAILURE on error. + */ +int ddrphy_phyinit_sequence(struct stm32mp_ddr_config *config, bool skip_training, bool reten) +{ + int ret; + uint32_t ardptrinitval; /* + * Represents the value stored in Step C into the register with the + * same name. Defined as a global variable so that implementation + * of ddrphy_phyinit_progcsrskiptrain() function does not require + * a PHY read register implementation. + */ + struct pmu_smb_ddr_1d mb_ddr_1d; /* Firmware 1D Message Block structure */ + + /* Check user input pstate number consistency vs. SW capabilities */ + if (config->uib.numpstates > 1U) { + return -1; + } + + /* Initialize structures */ + ddrphy_phyinit_initstruct(config, &mb_ddr_1d); + + /* Re-calculate Firmware Message Block input based on final user input */ + ret = ddrphy_phyinit_calcmb(config, &mb_ddr_1d); + if (ret != 0) { + return ret; + } + + /* (A) Bring up VDD, VDDQ, and VAA */ + /* ddrphy_phyinit_usercustom_a_bringuppower(); */ + + /* (B) Start Clocks and Reset the PHY */ + /* ddrphy_phyinit_usercustom_b_startclockresetphy(); */ + + /* (C) Initialize PHY Configuration */ + ret = ddrphy_phyinit_c_initphyconfig(config, &mb_ddr_1d, &ardptrinitval); + if (ret != 0) { + return ret; + } + /* + * Customize any register write desired; This can include any CSR not covered by PhyInit + * or user wish to override values calculated in step_C. + */ + ddrphy_phyinit_usercustom_custompretrain(config); + + /* Stop retention register tracking for training firmware related registers */ + ret = ddrphy_phyinit_reginterface(STOPTRACK, 0U, 0U); + if (ret != 0) { + return ret; + } + + if (skip_training) { + /* Skip running training firmware entirely */ + ddrphy_phyinit_progcsrskiptrain(config, &mb_ddr_1d, ardptrinitval); + } else { + /* (D) Load the IMEM Memory for 1D training */ + ddrphy_phyinit_d_loadimem(); + + /* (E) Set the PHY input clocks to the desired frequency */ + /* ddrphy_phyinit_usercustom_e_setdficlk(pstate); */ + + /* (F) Write the Message Block parameters for the training firmware */ + ret = ddrphy_phyinit_f_loaddmem(config, &mb_ddr_1d); + if (ret != 0) { + return ret; + } + + /* (G) Execute the Training Firmware */ + ret = ddrphy_phyinit_g_execfw(); + if (ret != 0) { + return ret; + } + + /* (H) Read the Message Block results */ + /* ddrphy_phyinit_h_readmsgblock(); */ + } + + /* Start retention register tracking for training firmware related registers */ + ret = ddrphy_phyinit_reginterface(STARTTRACK, 0U, 0U); + if (ret != 0) { + return ret; + } + + /* (I) Load PHY Init Engine Image */ + ddrphy_phyinit_i_loadpieimage(config, skip_training); + + /* + * Customize any CSR write desired to override values programmed by firmware or + * ddrphy_phyinit_i_loadpieimage() + */ + /* ddrphy_phyinit_usercustom_customposttrain(); */ + + if (reten) { + /* Save value of tracked registers for retention restore sequence. */ + ret = ddrphy_phyinit_usercustom_saveretregs(config); + if (ret != 0) { + return ret; + } + } + + /* (J) Initialize the PHY to Mission Mode through DFI Initialization */ + /* ddrphy_phyinit_usercustom_j_entermissionmode(); */ + + return 0; +} diff --git a/drivers/st/ddr/phy/phyinit/src/ddrphy_phyinit_softsetmb.c b/drivers/st/ddr/phy/phyinit/src/ddrphy_phyinit_softsetmb.c new file mode 100644 index 000000000..86b084d6f --- /dev/null +++ b/drivers/st/ddr/phy/phyinit/src/ddrphy_phyinit_softsetmb.c @@ -0,0 +1,100 @@ +/* + * Copyright (C) 2021-2024, STMicroelectronics - All Rights Reserved + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include +#include + +#include + +#include + +/* + * Set messageBlock variable only if not set by user + * + * This function is used by ddrphy_phyinit_calcmb() to set calculated + * messageBlock variables only when the user has not directly programmed them. + * + * @param[in] field A string representing the messageBlock field to be programed. + * @param[in] value filed value + * + * @return 0 on success. + * On error returns the following values based on error: + * - -1 : message block field specified by the input \c field string is not + * found in the message block data structure. + */ +int ddrphy_phyinit_softsetmb(struct pmu_smb_ddr_1d *mb_ddr_1d, enum message_block_field field, + uint32_t value) +{ + int ret = 0; + + if (field == MB_FIELD_DRAMFREQ) { + assert(value <= UINT16_MAX); + } else { + assert(value <= UINT8_MAX); + } + + switch (field) { + case MB_FIELD_PSTATE: + mb_ddr_1d->pstate = (uint8_t)value; + break; + case MB_FIELD_PLLBYPASSEN: + mb_ddr_1d->pllbypassen = (uint8_t)value; + break; + case MB_FIELD_DRAMFREQ: + mb_ddr_1d->dramfreq = (uint16_t)value; + break; + case MB_FIELD_DFIFREQRATIO: + mb_ddr_1d->dfifreqratio = (uint8_t)value; + break; + case MB_FIELD_BPZNRESVAL: + mb_ddr_1d->bpznresval = (uint8_t)value; + break; + case MB_FIELD_PHYODTIMPEDANCE: + mb_ddr_1d->phyodtimpedance = (uint8_t)value; + break; + case MB_FIELD_PHYDRVIMPEDANCE: + mb_ddr_1d->phydrvimpedance = (uint8_t)value; + break; +#if STM32MP_DDR3_TYPE || STM32MP_DDR4_TYPE + case MB_FIELD_DRAMTYPE: + mb_ddr_1d->dramtype = (uint8_t)value; + break; + case MB_FIELD_DISABLEDDBYTE: + mb_ddr_1d->disableddbyte = (uint8_t)value; + break; + case MB_FIELD_ENABLEDDQS: + mb_ddr_1d->enableddqs = (uint8_t)value; + break; + case MB_FIELD_PHYCFG: + mb_ddr_1d->phycfg = (uint8_t)value; + break; +#if STM32MP_DDR4_TYPE + case MB_FIELD_X16PRESENT: + mb_ddr_1d->x16present = (uint8_t)value; + break; +#endif /* STM32MP_DDR4_TYPE */ +#else /* STM32MP_LPDDR4_TYPE */ + case MB_FIELD_ENABLEDDQSCHA: + mb_ddr_1d->enableddqscha = (uint8_t)value; + break; + case MB_FIELD_CSPRESENTCHA: + mb_ddr_1d->cspresentcha = (uint8_t)value; + break; + case MB_FIELD_ENABLEDDQSCHB: + mb_ddr_1d->enableddqschb = (uint8_t)value; + break; + case MB_FIELD_CSPRESENTCHB: + mb_ddr_1d->cspresentchb = (uint8_t)value; + break; +#endif /* STM32MP_DDR3_TYPE || STM32MP_DDR4_TYPE */ + default: + ERROR("unknown message block field %u\n", field); + ret = -1; + break; + } + + return ret; +} diff --git a/drivers/st/ddr/phy/phyinit/src/ddrphy_phyinit_writeoutmem.c b/drivers/st/ddr/phy/phyinit/src/ddrphy_phyinit_writeoutmem.c new file mode 100644 index 000000000..868800e2a --- /dev/null +++ b/drivers/st/ddr/phy/phyinit/src/ddrphy_phyinit_writeoutmem.c @@ -0,0 +1,79 @@ +/* + * Copyright (C) 2021-2024, STMicroelectronics - All Rights Reserved + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include + +#include + +#include + +#include + +#include + +/* + * Writes local memory content into the SRAM via APB interface. + * + * This function issued APB writes commands to SRAM address based on values + * stored in a local PhyInit array that contains consolidated IMEM and DMEM + * data. + * @param[in] mem[] Local memory array. + * @param[in] mem_offset offset index. if provided, skips to the offset index + * from the local array and issues APB commands from mem_offset to mem_size. + * @param[in] mem_size size of the memroy (in mem array index) + * @returns void + */ +void ddrphy_phyinit_writeoutmem(uint32_t *mem, uint32_t mem_offset, uint32_t mem_size) +{ + uint32_t index; + + /* + * 1. Enable access to the internal CSRs by setting the MicroContMuxSel CSR to 0. + * This allows the memory controller unrestricted access to the configuration CSRs. + */ + mmio_write_16((uintptr_t)(DDRPHYC_BASE + (4U * (TAPBONLY | CSR_MICROCONTMUXSEL_ADDR))), + 0x0U); + + for (index = 0U; index < mem_size / sizeof(uint32_t); index++) { + uint32_t data = mem[index]; + + mmio_write_16((uintptr_t)(DDRPHYC_BASE + (4U * ((index * 2) + mem_offset))), + data & 0xFFFFU); + mmio_write_16((uintptr_t)(DDRPHYC_BASE + (4U * ((index * 2) + 1 + mem_offset))), + (data >> 16) & 0xFFFFU); + } + + /* + * 2. Isolate the APB access from the internal CSRs by setting the MicroContMuxSel CSR to 1. + * This allows the firmware unrestricted access to the configuration CSRs. + */ + mmio_write_16((uintptr_t)(DDRPHYC_BASE + (4U * (TAPBONLY | CSR_MICROCONTMUXSEL_ADDR))), + 0x1U); +} + +/* Similar function for message block */ +void ddrphy_phyinit_writeoutmsgblk(uint16_t *mem, uint32_t mem_offset, uint32_t mem_size) +{ + uint32_t index; + + /* + * 1. Enable access to the internal CSRs by setting the MicroContMuxSel CSR to 0. + * This allows the memory controller unrestricted access to the configuration CSRs. + */ + mmio_write_16((uintptr_t)(DDRPHYC_BASE + (4U * (TAPBONLY | CSR_MICROCONTMUXSEL_ADDR))), + 0x0U); + + for (index = 0U; index < mem_size / sizeof(uint16_t); index++) { + mmio_write_16((uintptr_t)(DDRPHYC_BASE + (4U * (index + mem_offset))), mem[index]); + } + + /* + * 2. Isolate the APB access from the internal CSRs by setting the MicroContMuxSel CSR to 1. + * This allows the firmware unrestricted access to the configuration CSRs. + */ + mmio_write_16((uintptr_t)(DDRPHYC_BASE + (4U * (TAPBONLY | CSR_MICROCONTMUXSEL_ADDR))), + 0x1U); +} diff --git a/drivers/st/ddr/phy/phyinit/usercustom/ddrphy_phyinit_usercustom_custompretrain.c b/drivers/st/ddr/phy/phyinit/usercustom/ddrphy_phyinit_usercustom_custompretrain.c new file mode 100644 index 000000000..6a2001315 --- /dev/null +++ b/drivers/st/ddr/phy/phyinit/usercustom/ddrphy_phyinit_usercustom_custompretrain.c @@ -0,0 +1,90 @@ +/* + * Copyright (C) 2021-2024, STMicroelectronics - All Rights Reserved + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include +#include + +#include + +#include + +#include + +#include + +/* DDRDBG registers */ +#define DDRDBG_DDR34_AC_SWIZZLE_ADD3_0 U(0x100) + +/* + * This function is called before training firmware is executed. Any + * register override in this function might affect the firmware training + * results. + * + * This function is executed before firmware execution loop. Thus this function + * should be used only for the following: + * + * - Override PHY register values written by + * ddrphy_phyinit_c_initphyconfig. An example use case is when this + * function does not perform the exact programing desired by the user. + * - Write custom PHY registers that need to take effect before training + * firmware execution. + * + * User shall use mmio_write_16 to write PHY registers in order for the register + * to be tracked by PhyInit for retention restore. + * + * To override settings in the message block, users can assign values to the + * fields in the message block data structure directly. + * + * \ref examples/simple/ddrphy_phyinit_usercustom_custompretrain.c example of this function. + * + * @return Void + */ +void ddrphy_phyinit_usercustom_custompretrain(struct stm32mp_ddr_config *config) +{ + uint32_t byte __unused; + uint32_t i = 0U; + uint32_t j; + uintptr_t base; + +#if STM32MP_DDR3_TYPE || STM32MP_DDR4_TYPE + base = (uintptr_t)(DDRPHYC_BASE + (4U * (TMASTER | CSR_HWTSWIZZLEHWTADDRESS0_ADDR))); + + for (i = 0U; i < NB_HWT_SWIZZLE; i++) { + mmio_write_16(base + (i * sizeof(uint32_t)), + (uint16_t)config->uis.swizzle[i]); + } + + base = (uintptr_t)(stm32_ddrdbg_get_base() + DDRDBG_DDR34_AC_SWIZZLE_ADD3_0); + + for (j = 0U; j < NB_AC_SWIZZLE; j++, i++) { + mmio_write_32(base + (j * sizeof(uint32_t)), config->uis.swizzle[i]); + } +#else /* STM32MP_LPDDR4_TYPE */ + for (byte = 0U; byte < config->uib.numdbyte; byte++) { + base = (uintptr_t)(DDRPHYC_BASE + (4U * + ((byte << 12) | TDBYTE | CSR_DQ0LNSEL_ADDR))); + + for (j = 0U; j < NB_DQLNSEL_SWIZZLE_PER_BYTE; j++, i++) { + mmio_write_16(base + (j * sizeof(uint32_t)), + (uint16_t)config->uis.swizzle[i]); + } + } + + base = (uintptr_t)(DDRPHYC_BASE + (4U * (TMASTER | CSR_MAPCAA0TODFI_ADDR))); + + for (j = 0U; j < NB_MAPCAATODFI_SWIZZLE; j++, i++) { + mmio_write_16(base + (j * sizeof(uint32_t)), + (uint16_t)config->uis.swizzle[i]); + } + + base = (uintptr_t)(DDRPHYC_BASE + (4U * (TMASTER | CSR_MAPCAB0TODFI_ADDR))); + + for (j = 0U; j < NB_MAPCABTODFI_SWIZZLE; j++, i++) { + mmio_write_16(base + (j * sizeof(uint32_t)), + (uint16_t)config->uis.swizzle[i]); + } +#endif /* STM32MP_DDR3_TYPE || STM32MP_DDR4_TYPE */ +} diff --git a/drivers/st/ddr/phy/phyinit/usercustom/ddrphy_phyinit_usercustom_g_waitfwdone.c b/drivers/st/ddr/phy/phyinit/usercustom/ddrphy_phyinit_usercustom_g_waitfwdone.c new file mode 100644 index 000000000..3d00d3d4a --- /dev/null +++ b/drivers/st/ddr/phy/phyinit/usercustom/ddrphy_phyinit_usercustom_g_waitfwdone.c @@ -0,0 +1,183 @@ +/* + * Copyright (C) 2021-2024, STMicroelectronics - All Rights Reserved + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include + +#include + +#include + +#include + +#include + +/* Firmware major messages */ +#define FW_MAJ_MSG_TRAINING_SUCCESS 0x0000007U +#define FW_MAJ_MSG_START_STREAMING 0x0000008U +#define FW_MAJ_MSG_TRAINING_FAILED 0x00000FFU + +#define PHYINIT_DELAY_1US 1U +#define PHYINIT_DELAY_10US 10U +#define PHYINIT_TIMEOUT_US_1S 1000000U + +static int wait_uctwriteprotshadow(bool state) +{ + uint64_t timeout; + uint16_t read_data; + uint16_t value = state ? BIT(0) : 0U; + + timeout = timeout_init_us(PHYINIT_TIMEOUT_US_1S); + + do { + read_data = mmio_read_16((uintptr_t)(DDRPHYC_BASE + + (4U * (TAPBONLY | CSR_UCTSHADOWREGS_ADDR)))); + udelay(PHYINIT_DELAY_1US); + if (timeout_elapsed(timeout)) { + return -1; + } + } while ((read_data & BIT(0)) != value); + + return 0; +} + +static int ack_message_receipt(void) +{ + int ret; + + /* Acknowledge the receipt of the message */ + mmio_write_16((uintptr_t)(DDRPHYC_BASE + (4U * (TAPBONLY | CSR_DCTWRITEPROT_ADDR))), 0U); + + udelay(PHYINIT_DELAY_1US); + + ret = wait_uctwriteprotshadow(true); + if (ret != 0) { + return ret; + } + + /* Complete the 4-phase protocol */ + mmio_write_16((uintptr_t)(DDRPHYC_BASE + (4U * (TAPBONLY | CSR_DCTWRITEPROT_ADDR))), 1U); + + udelay(PHYINIT_DELAY_1US); + + return 0; +} + +static int get_major_message(uint32_t *msg) +{ + uint16_t message_number; + int ret; + + ret = wait_uctwriteprotshadow(false); + if (ret != 0) { + return ret; + } + + message_number = mmio_read_16((uintptr_t)(DDRPHYC_BASE + + (4U * (TAPBONLY | + CSR_UCTWRITEONLYSHADOW_ADDR)))); + + ret = ack_message_receipt(); + if (ret != 0) { + return ret; + } + + *msg = (uint32_t)message_number; + + return 0; +} + +static int get_streaming_message(uint32_t *msg) +{ + uint16_t stream_word_lower_part; + uint16_t stream_word_upper_part; + int ret; + + ret = wait_uctwriteprotshadow(false); + if (ret != 0) { + return ret; + } + + stream_word_lower_part = mmio_read_16((uintptr_t)(DDRPHYC_BASE + + (4U * (TAPBONLY | + CSR_UCTWRITEONLYSHADOW_ADDR)))); + + stream_word_upper_part = mmio_read_16((uintptr_t)(DDRPHYC_BASE + + (4U * (TAPBONLY | + CSR_UCTDATWRITEONLYSHADOW_ADDR)))); + + ret = ack_message_receipt(); + if (ret != 0) { + return ret; + } + + *msg = (uint32_t)stream_word_lower_part | ((uint32_t)stream_word_upper_part << 16); + + return 0; +} + +/* + * Implements the mechanism to wait for completion of training firmware execution. + * + * The purpose of user this function is to wait for firmware to finish training. + * The user can either implement a counter to wait or implement the polling + * mechanism (our choice here). The wait time is highly dependent on the training features + * enabled via sequencectrl input to the message block. + * + * The default behavior of this function is to print comments relating to this + * process. A function call of the same name will be printed in the output text + * file. + * + * The user can choose to leave this function as is, or implement mechanism to + * trigger mailbox poling event in simulation. + * + * \return 0 on success. + */ +int ddrphy_phyinit_usercustom_g_waitfwdone(void) +{ + uint32_t fw_major_message; + int ret; + + do { + ret = get_major_message(&fw_major_message); + if (ret != 0) { + return ret; + } + + VERBOSE("fw_major_message = %x\n", (unsigned int)fw_major_message); + + if (fw_major_message == FW_MAJ_MSG_START_STREAMING) { + uint32_t i; + uint32_t read_data; + uint32_t stream_len; + + ret = get_streaming_message(&read_data); + if (ret != 0) { + return ret; + } + + stream_len = read_data & 0xFFFFU; + + for (i = 0U; i < stream_len; i++) { + ret = get_streaming_message(&read_data); + if (ret != 0) { + return ret; + } + + VERBOSE("streaming message = %x\n", (unsigned int)read_data); + } + } + } while ((fw_major_message != FW_MAJ_MSG_TRAINING_SUCCESS) && + (fw_major_message != FW_MAJ_MSG_TRAINING_FAILED)); + + udelay(PHYINIT_DELAY_10US); + + if (fw_major_message == FW_MAJ_MSG_TRAINING_FAILED) { + ERROR("%s Training has failed.\n", __func__); + return -1; + } + + return 0; +} diff --git a/drivers/st/ddr/phy/phyinit/usercustom/ddrphy_phyinit_usercustom_saveretregs.c b/drivers/st/ddr/phy/phyinit/usercustom/ddrphy_phyinit_usercustom_saveretregs.c new file mode 100644 index 000000000..b573de32f --- /dev/null +++ b/drivers/st/ddr/phy/phyinit/usercustom/ddrphy_phyinit_usercustom_saveretregs.c @@ -0,0 +1,399 @@ +/* + * Copyright (C) 2021-2024, STMicroelectronics - All Rights Reserved + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include + +#include + +#include + +#include + +#include + +/* + * This function can be used to implement saving of PHY registers to be + * restored on retention exit. + * + * The requirement of this function is to issue register reads and store the + * value to be recovered on retention exit. The following is an example + * implementation and the user may implement alternate methods that suit their + * specific SoC system needs. + * + * In this implementation PhyInit saves register values in an internal C array. + * During retention exit it restores register values from the array. The exact + * list of registers to save and later restore can be seen in the output txt + * file with an associated calls to mmio_read_16(). + * + * PhyInit provides a register interface and a tracking mechanism to minimize + * the number registers needing restore. Refer to source code for + * ddrphy_phyinit_reginterface() for detailed implementation of tracking + * mechanism. Tracking is disabled from step D to Step H as these involve + * loading, executing and checking the state of training firmware execution + * which are not required to implement the retention exit sequence. The registers + * specified representing training results are also saved in addition to registers + * written by PhyInit during PHY initialization. + * + * \return 0 on success. + */ +int ddrphy_phyinit_usercustom_saveretregs(struct stm32mp_ddr_config *config) +{ + uint32_t anib; + uint32_t byte; + uint32_t nibble; + uint32_t lane; + uint32_t c_addr; + uint32_t u_addr; + uint32_t b_addr; + uint32_t r_addr; + int ret; + + /* + * -------------------------------------------------------------------------- + * 1. Enable tracking of training firmware result registers + * + * \note The tagged registers in this step are in + * addition to what is automatically tagged during Steps C to I. + * + * -------------------------------------------------------------------------- + */ + + ret = ddrphy_phyinit_trackreg(TMASTER | CSR_PLLCTRL3_ADDR); + if (ret != 0) { + return ret; + } + + /* Non-PState Dbyte Registers */ + for (byte = 0U; byte < config->uib.numdbyte; byte++) { + c_addr = byte << 12; + + for (lane = 0U; lane <= R_MAX; lane++) { + r_addr = lane << 8; + + ret = ddrphy_phyinit_trackreg(TDBYTE | c_addr | r_addr | + CSR_RXPBDLYTG0_ADDR); + if (ret != 0) { + return ret; + } +#if STM32MP_LPDDR4_TYPE + ret = ddrphy_phyinit_trackreg(TDBYTE | c_addr | r_addr | + CSR_RXPBDLYTG1_ADDR); + if (ret != 0) { + return ret; + } +#endif /* STM32MP_LPDDR4_TYPE */ + } + +#if STM32MP_LPDDR4_TYPE + ret = ddrphy_phyinit_trackreg(TDBYTE | c_addr | CSR_PPTCTLSTATIC_ADDR); + if (ret != 0) { + return ret; + } + + ret = ddrphy_phyinit_trackreg(TDBYTE | c_addr | CSR_TRAININGINCDECDTSMEN_ADDR); + if (ret != 0) { + return ret; + } + + ret = ddrphy_phyinit_trackreg(TDBYTE | c_addr | CSR_TSMBYTE0_ADDR); + if (ret != 0) { + return ret; + } + + ret = ddrphy_phyinit_trackreg(TDBYTE | c_addr | CSR_DQ0LNSEL_ADDR); + if (ret != 0) { + return ret; + } + + ret = ddrphy_phyinit_trackreg(TDBYTE | c_addr | CSR_DQ1LNSEL_ADDR); + if (ret != 0) { + return ret; + } + + ret = ddrphy_phyinit_trackreg(TDBYTE | c_addr | CSR_DQ2LNSEL_ADDR); + if (ret != 0) { + return ret; + } + + ret = ddrphy_phyinit_trackreg(TDBYTE | c_addr | CSR_DQ3LNSEL_ADDR); + if (ret != 0) { + return ret; + } + + ret = ddrphy_phyinit_trackreg(TDBYTE | c_addr | CSR_DQ4LNSEL_ADDR); + if (ret != 0) { + return ret; + } + + ret = ddrphy_phyinit_trackreg(TDBYTE | c_addr | CSR_DQ5LNSEL_ADDR); + if (ret != 0) { + return ret; + } + + ret = ddrphy_phyinit_trackreg(TDBYTE | c_addr | CSR_DQ6LNSEL_ADDR); + if (ret != 0) { + return ret; + } + + ret = ddrphy_phyinit_trackreg(TDBYTE | c_addr | CSR_DQ7LNSEL_ADDR); + if (ret != 0) { + return ret; + } +#endif /* STM32MP_LPDDR4_TYPE */ + } + + ret = ddrphy_phyinit_trackreg(TMASTER | CSR_VREFINGLOBAL_ADDR); + if (ret != 0) { + return ret; + } + + /* Anib Registers */ + for (anib = 0U; anib < config->uib.numanib; anib++) { + c_addr = anib << 12; + + ret = ddrphy_phyinit_trackreg(TANIB | c_addr | CSR_ATXDLY_ADDR); + if (ret != 0) { + return ret; + } + } + + /* Dbyte Registers */ + for (byte = 0U; byte < config->uib.numdbyte; byte++) { + c_addr = byte << 12; + + ret = ddrphy_phyinit_trackreg(TDBYTE | c_addr | CSR_DFIMRL_ADDR); + if (ret != 0) { + return ret; + } + + for (nibble = 0U; nibble <= B_MAX; nibble++) { + b_addr = nibble << 8; + + ret = ddrphy_phyinit_trackreg(TDBYTE | c_addr | b_addr | + CSR_DQDQSRCVCNTRL_ADDR); + if (ret != 0) { + return ret; + } + } + + for (nibble = 0U; nibble < 2U; nibble++) { + u_addr = nibble << 8; + + ret = ddrphy_phyinit_trackreg(TDBYTE | c_addr | u_addr | + CSR_RXENDLYTG0_ADDR); + if (ret != 0) { + return ret; + } +#if STM32MP_LPDDR4_TYPE + ret = ddrphy_phyinit_trackreg(TDBYTE | c_addr | u_addr | + CSR_RXENDLYTG1_ADDR); + if (ret != 0) { + return ret; + } +#endif /* STM32MP_LPDDR4_TYPE */ + ret = ddrphy_phyinit_trackreg(TDBYTE | c_addr | u_addr | + CSR_TXDQSDLYTG0_ADDR); + if (ret != 0) { + return ret; + } +#if STM32MP_LPDDR4_TYPE + ret = ddrphy_phyinit_trackreg(TDBYTE | c_addr | u_addr | + CSR_TXDQSDLYTG1_ADDR); + if (ret != 0) { + return ret; + } +#endif /* STM32MP_LPDDR4_TYPE */ + ret = ddrphy_phyinit_trackreg(TDBYTE | c_addr | u_addr | + CSR_RXCLKDLYTG0_ADDR); + if (ret != 0) { + return ret; + } +#if STM32MP_LPDDR4_TYPE + ret = ddrphy_phyinit_trackreg(TDBYTE | c_addr | u_addr | + CSR_RXCLKDLYTG1_ADDR); + if (ret != 0) { + return ret; + } +#endif /* STM32MP_LPDDR4_TYPE */ + } + + for (lane = R_MIN; lane <= R_MAX; lane++) { + r_addr = lane << 8; + + ret = ddrphy_phyinit_trackreg(TDBYTE | c_addr | r_addr | + CSR_TXDQDLYTG0_ADDR); + if (ret != 0) { + return ret; + } +#if STM32MP_LPDDR4_TYPE + ret = ddrphy_phyinit_trackreg(TDBYTE | c_addr | r_addr | + CSR_TXDQDLYTG1_ADDR); + if (ret != 0) { + return ret; + } +#endif /* STM32MP_LPDDR4_TYPE */ + } + +#if STM32MP_LPDDR4_TYPE + ret = ddrphy_phyinit_trackreg(TDBYTE | c_addr | CSR_PPTDQSCNTINVTRNTG0_ADDR); + if (ret != 0) { + return ret; + } + ret = ddrphy_phyinit_trackreg(TDBYTE | c_addr | CSR_PPTDQSCNTINVTRNTG1_ADDR); + if (ret != 0) { + return ret; + } +#endif /* STM32MP_LPDDR4_TYPE */ + } + + /* PIE Registers */ + ret = ddrphy_phyinit_trackreg(TINITENG | CSR_SEQ0BGPR1_ADDR); + if (ret != 0) { + return ret; + } + + ret = ddrphy_phyinit_trackreg(TINITENG | CSR_SEQ0BGPR2_ADDR); + if (ret != 0) { + return ret; + } + + ret = ddrphy_phyinit_trackreg(TINITENG | CSR_SEQ0BGPR3_ADDR); + if (ret != 0) { + return ret; + } + + ret = ddrphy_phyinit_trackreg(TINITENG | CSR_SEQ0BGPR4_ADDR); + if (ret != 0) { + return ret; + } + + ret = ddrphy_phyinit_trackreg(TINITENG | CSR_SEQ0BGPR5_ADDR); + if (ret != 0) { + return ret; + } + + ret = ddrphy_phyinit_trackreg(TINITENG | CSR_SEQ0BGPR6_ADDR); + if (ret != 0) { + return ret; + } + + ret = ddrphy_phyinit_trackreg(TINITENG | CSR_SEQ0BGPR7_ADDR); + if (ret != 0) { + return ret; + } + + ret = ddrphy_phyinit_trackreg(TINITENG | CSR_SEQ0BGPR8_ADDR); + if (ret != 0) { + return ret; + } + + /* Master Registers */ + ret = ddrphy_phyinit_trackreg(TMASTER | CSR_DLLGAINCTL_ADDR); + if (ret != 0) { + return ret; + } + + ret = ddrphy_phyinit_trackreg(TMASTER | CSR_DLLLOCKPARAM_ADDR); + if (ret != 0) { + return ret; + } +#if STM32MP_LPDDR4_TYPE + ret = ddrphy_phyinit_trackreg(TMASTER | CSR_HWTMRL_ADDR); + if (ret != 0) { + return ret; + } + + /* INITENG Registers */ + ret = ddrphy_phyinit_trackreg(TINITENG | CSR_SEQ0BDISABLEFLAG6_ADDR); + if (ret != 0) { + return ret; + } +#endif /* STM32MP_LPDDR4_TYPE */ + + ret = ddrphy_phyinit_trackreg(TMASTER | CSR_HWTCAMODE_ADDR); + if (ret != 0) { + return ret; + } + +#if STM32MP_LPDDR4_TYPE + ret = ddrphy_phyinit_trackreg(TMASTER | CSR_HWTLPCSENA_ADDR); + if (ret != 0) { + return ret; + } + + ret = ddrphy_phyinit_trackreg(TMASTER | CSR_HWTLPCSENB_ADDR); + if (ret != 0) { + return ret; + } + + /* ACSM registers */ + ret = ddrphy_phyinit_trackreg(TACSM | CSR_ACSMCTRL13_ADDR); + if (ret != 0) { + return ret; + } + + ret = ddrphy_phyinit_trackreg(TACSM | CSR_ACSMCTRL23_ADDR); + if (ret != 0) { + return ret; + } +#endif /* STM32MP_LPDDR4_TYPE */ + + /* + * -------------------------------------------------------------------------- + * 2. Track any additional registers + * Register writes made using the any of the PhyInit functions are + * automatically tracked using the call to ddrphy_phyinit_trackreg() in + * mmio_write_16(). Use this section to track additional registers. + * -------------------------------------------------------------------------- + */ + + /* + * Example: + * ddrphy_phyinit_trackreg(); + */ + + /* + * -------------------------------------------------------------------------- + * 3. Prepare for register reads + * - Write the MicroContMuxSel CSR to 0x0 to allow access to the internal CSRs + * - Write the UcclkHclkEnables CSR to 0x3 to enable all the clocks so the reads + * can complete. + * -------------------------------------------------------------------------- + */ + mmio_write_16((uintptr_t)(DDRPHYC_BASE + (4U * (TAPBONLY | CSR_MICROCONTMUXSEL_ADDR))), + 0x0U); + mmio_write_16((uintptr_t)(DDRPHYC_BASE + (4U * (TDRTUB | CSR_UCCLKHCLKENABLES_ADDR))), + 0x3U); + + /* + * -------------------------------------------------------------------------- + * / 4. Read and save all the registers + * / - The list of registers differ depending on protocol and 1D training. + * -------------------------------------------------------------------------- + */ + + ret = ddrphy_phyinit_reginterface(SAVEREGS, 0U, 0U); + if (ret != 0) { + return ret; + } + + /* + * -------------------------------------------------------------------------- + * 5. Prepare for mission mode + * - Write the UcclkHclkEnables CSR to disable the appropriate clocks after all reads done. + * - Write the MicroContMuxSel CSR to 0x1 to isolate the internal CSRs during mission mode. + * -------------------------------------------------------------------------- + */ + + /* Disabling Ucclk (PMU) and Hclk (training hardware) */ + mmio_write_16((uintptr_t)(DDRPHYC_BASE + (4U * (TDRTUB | CSR_UCCLKHCLKENABLES_ADDR))), + 0x0U); + + mmio_write_16((uintptr_t)(DDRPHYC_BASE + (4U * (TAPBONLY | CSR_MICROCONTMUXSEL_ADDR))), + 0x1U); + + return 0; +} diff --git a/drivers/st/ddr/stm32mp2_ddr.c b/drivers/st/ddr/stm32mp2_ddr.c new file mode 100644 index 000000000..5193d1182 --- /dev/null +++ b/drivers/st/ddr/stm32mp2_ddr.c @@ -0,0 +1,479 @@ +/* + * Copyright (C) 2021-2024, STMicroelectronics - All Rights Reserved + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include + +#include + +#include + +#include +#include +#include +#include + +#include + +#include + +#define DDRDBG_FRAC_PLL_LOCK U(0x10) + +#define DDRCTL_REG(x, y, z) \ + { \ + .offset = offsetof(struct stm32mp_ddrctl, x), \ + .par_offset = offsetof(struct y, x), \ + .qd = z \ + } + +/* + * PARAMETERS: value get from device tree : + * size / order need to be aligned with binding + * modification NOT ALLOWED !!! + */ +#define DDRCTL_REG_REG_SIZE 48 /* st,ctl-reg */ +#define DDRCTL_REG_TIMING_SIZE 20 /* st,ctl-timing */ +#define DDRCTL_REG_MAP_SIZE 12 /* st,ctl-map */ +#if STM32MP_DDR_DUAL_AXI_PORT +#define DDRCTL_REG_PERF_SIZE 21 /* st,ctl-perf */ +#else /* !STM32MP_DDR_DUAL_AXI_PORT */ +#define DDRCTL_REG_PERF_SIZE 14 /* st,ctl-perf */ +#endif /* STM32MP_DDR_DUAL_AXI_PORT */ + +#define DDRPHY_REG_REG_SIZE 0 /* st,phy-reg */ +#define DDRPHY_REG_TIMING_SIZE 0 /* st,phy-timing */ + +#define DDRCTL_REG_REG(x, z) DDRCTL_REG(x, stm32mp2_ddrctrl_reg, z) +static const struct stm32mp_ddr_reg_desc ddr_reg[DDRCTL_REG_REG_SIZE] = { + DDRCTL_REG_REG(mstr, true), + DDRCTL_REG_REG(mrctrl0, false), + DDRCTL_REG_REG(mrctrl1, false), + DDRCTL_REG_REG(mrctrl2, false), + DDRCTL_REG_REG(derateen, true), + DDRCTL_REG_REG(derateint, false), + DDRCTL_REG_REG(deratectl, false), + DDRCTL_REG_REG(pwrctl, false), + DDRCTL_REG_REG(pwrtmg, true), + DDRCTL_REG_REG(hwlpctl, true), + DDRCTL_REG_REG(rfshctl0, false), + DDRCTL_REG_REG(rfshctl1, false), + DDRCTL_REG_REG(rfshctl3, true), + DDRCTL_REG_REG(crcparctl0, false), + DDRCTL_REG_REG(crcparctl1, false), + DDRCTL_REG_REG(init0, true), + DDRCTL_REG_REG(init1, false), + DDRCTL_REG_REG(init2, false), + DDRCTL_REG_REG(init3, true), + DDRCTL_REG_REG(init4, true), + DDRCTL_REG_REG(init5, false), + DDRCTL_REG_REG(init6, true), + DDRCTL_REG_REG(init7, true), + DDRCTL_REG_REG(dimmctl, false), + DDRCTL_REG_REG(rankctl, true), + DDRCTL_REG_REG(rankctl1, true), + DDRCTL_REG_REG(zqctl0, true), + DDRCTL_REG_REG(zqctl1, false), + DDRCTL_REG_REG(zqctl2, false), + DDRCTL_REG_REG(dfitmg0, true), + DDRCTL_REG_REG(dfitmg1, true), + DDRCTL_REG_REG(dfilpcfg0, false), + DDRCTL_REG_REG(dfilpcfg1, false), + DDRCTL_REG_REG(dfiupd0, true), + DDRCTL_REG_REG(dfiupd1, false), + DDRCTL_REG_REG(dfiupd2, false), + DDRCTL_REG_REG(dfimisc, true), + DDRCTL_REG_REG(dfitmg2, true), + DDRCTL_REG_REG(dfitmg3, false), + DDRCTL_REG_REG(dbictl, true), + DDRCTL_REG_REG(dfiphymstr, false), + DDRCTL_REG_REG(dbg0, false), + DDRCTL_REG_REG(dbg1, false), + DDRCTL_REG_REG(dbgcmd, false), + DDRCTL_REG_REG(swctl, false), /* forced qd value */ + DDRCTL_REG_REG(swctlstatic, false), + DDRCTL_REG_REG(poisoncfg, false), + DDRCTL_REG_REG(pccfg, false), +}; + +#define DDRCTL_REG_TIMING(x, z) DDRCTL_REG(x, stm32mp2_ddrctrl_timing, z) +static const struct stm32mp_ddr_reg_desc ddr_timing[DDRCTL_REG_TIMING_SIZE] = { + DDRCTL_REG_TIMING(rfshtmg, false), + DDRCTL_REG_TIMING(rfshtmg1, false), + DDRCTL_REG_TIMING(dramtmg0, true), + DDRCTL_REG_TIMING(dramtmg1, true), + DDRCTL_REG_TIMING(dramtmg2, true), + DDRCTL_REG_TIMING(dramtmg3, true), + DDRCTL_REG_TIMING(dramtmg4, true), + DDRCTL_REG_TIMING(dramtmg5, true), + DDRCTL_REG_TIMING(dramtmg6, true), + DDRCTL_REG_TIMING(dramtmg7, true), + DDRCTL_REG_TIMING(dramtmg8, true), + DDRCTL_REG_TIMING(dramtmg9, true), + DDRCTL_REG_TIMING(dramtmg10, true), + DDRCTL_REG_TIMING(dramtmg11, true), + DDRCTL_REG_TIMING(dramtmg12, true), + DDRCTL_REG_TIMING(dramtmg13, true), + DDRCTL_REG_TIMING(dramtmg14, true), + DDRCTL_REG_TIMING(dramtmg15, true), + DDRCTL_REG_TIMING(odtcfg, true), + DDRCTL_REG_TIMING(odtmap, false), +}; + +#define DDRCTL_REG_MAP(x) DDRCTL_REG(x, stm32mp2_ddrctrl_map, false) +static const struct stm32mp_ddr_reg_desc ddr_map[DDRCTL_REG_MAP_SIZE] = { + DDRCTL_REG_MAP(addrmap0), + DDRCTL_REG_MAP(addrmap1), + DDRCTL_REG_MAP(addrmap2), + DDRCTL_REG_MAP(addrmap3), + DDRCTL_REG_MAP(addrmap4), + DDRCTL_REG_MAP(addrmap5), + DDRCTL_REG_MAP(addrmap6), + DDRCTL_REG_MAP(addrmap7), + DDRCTL_REG_MAP(addrmap8), + DDRCTL_REG_MAP(addrmap9), + DDRCTL_REG_MAP(addrmap10), + DDRCTL_REG_MAP(addrmap11), +}; + +#define DDRCTL_REG_PERF(x, z) DDRCTL_REG(x, stm32mp2_ddrctrl_perf, z) +static const struct stm32mp_ddr_reg_desc ddr_perf[DDRCTL_REG_PERF_SIZE] = { + DDRCTL_REG_PERF(sched, true), + DDRCTL_REG_PERF(sched1, false), + DDRCTL_REG_PERF(perfhpr1, true), + DDRCTL_REG_PERF(perflpr1, true), + DDRCTL_REG_PERF(perfwr1, true), + DDRCTL_REG_PERF(sched3, false), + DDRCTL_REG_PERF(sched4, false), + DDRCTL_REG_PERF(pcfgr_0, false), + DDRCTL_REG_PERF(pcfgw_0, false), + DDRCTL_REG_PERF(pctrl_0, false), + DDRCTL_REG_PERF(pcfgqos0_0, true), + DDRCTL_REG_PERF(pcfgqos1_0, true), + DDRCTL_REG_PERF(pcfgwqos0_0, true), + DDRCTL_REG_PERF(pcfgwqos1_0, true), +#if STM32MP_DDR_DUAL_AXI_PORT + DDRCTL_REG_PERF(pcfgr_1, false), + DDRCTL_REG_PERF(pcfgw_1, false), + DDRCTL_REG_PERF(pctrl_1, false), + DDRCTL_REG_PERF(pcfgqos0_1, true), + DDRCTL_REG_PERF(pcfgqos1_1, true), + DDRCTL_REG_PERF(pcfgwqos0_1, true), + DDRCTL_REG_PERF(pcfgwqos1_1, true), +#endif /* STM32MP_DDR_DUAL_AXI_PORT */ +}; + +static const struct stm32mp_ddr_reg_desc ddrphy_reg[DDRPHY_REG_REG_SIZE] = {}; + +static const struct stm32mp_ddr_reg_desc ddrphy_timing[DDRPHY_REG_TIMING_SIZE] = {}; + +/* + * REGISTERS ARRAY: used to parse device tree and interactive mode + */ +static const struct stm32mp_ddr_reg_info ddr_registers[REG_TYPE_NB] __unused = { + [REG_REG] = { + .name = "static", + .desc = ddr_reg, + .size = DDRCTL_REG_REG_SIZE, + .base = DDR_BASE + }, + [REG_TIMING] = { + .name = "timing", + .desc = ddr_timing, + .size = DDRCTL_REG_TIMING_SIZE, + .base = DDR_BASE + }, + [REG_PERF] = { + .name = "perf", + .desc = ddr_perf, + .size = DDRCTL_REG_PERF_SIZE, + .base = DDR_BASE + }, + [REG_MAP] = { + .name = "map", + .desc = ddr_map, + .size = DDRCTL_REG_MAP_SIZE, + .base = DDR_BASE + }, + [REGPHY_REG] = { + .name = "static", + .desc = ddrphy_reg, + .size = DDRPHY_REG_REG_SIZE, + .base = DDRPHY_BASE + }, + [REGPHY_TIMING] = { + .name = "timing", + .desc = ddrphy_timing, + .size = DDRPHY_REG_TIMING_SIZE, + .base = DDRPHY_BASE + }, +}; + +static void ddr_reset(struct stm32mp_ddr_priv *priv) +{ + udelay(DDR_DELAY_1US); + + mmio_setbits_32(priv->rcc + RCC_DDRITFCFGR, RCC_DDRITFCFGR_DDRRST); + mmio_write_32(priv->rcc + RCC_DDRPHYCAPBCFGR, + RCC_DDRPHYCAPBCFGR_DDRPHYCAPBEN | RCC_DDRPHYCAPBCFGR_DDRPHYCAPBLPEN | + RCC_DDRPHYCAPBCFGR_DDRPHYCAPBRST); + mmio_write_32(priv->rcc + RCC_DDRCAPBCFGR, + RCC_DDRCAPBCFGR_DDRCAPBEN | RCC_DDRCAPBCFGR_DDRCAPBLPEN | + RCC_DDRCAPBCFGR_DDRCAPBRST); + mmio_write_32(priv->rcc + RCC_DDRCFGR, + RCC_DDRCFGR_DDRCFGEN | RCC_DDRCFGR_DDRCFGLPEN | RCC_DDRCFGR_DDRCFGRST); + + udelay(DDR_DELAY_1US); + + mmio_setbits_32(priv->rcc + RCC_DDRITFCFGR, RCC_DDRITFCFGR_DDRRST); + mmio_write_32(priv->rcc + RCC_DDRPHYCAPBCFGR, + RCC_DDRPHYCAPBCFGR_DDRPHYCAPBEN | RCC_DDRPHYCAPBCFGR_DDRPHYCAPBLPEN); + mmio_write_32(priv->rcc + RCC_DDRCAPBCFGR, + RCC_DDRCAPBCFGR_DDRCAPBEN | RCC_DDRCAPBCFGR_DDRCAPBLPEN); + mmio_write_32(priv->rcc + RCC_DDRCFGR, RCC_DDRCFGR_DDRCFGEN | RCC_DDRCFGR_DDRCFGLPEN); + + udelay(DDR_DELAY_1US); +} + +static void ddr_standby_reset(struct stm32mp_ddr_priv *priv) +{ + udelay(DDR_DELAY_1US); + + mmio_write_32(priv->rcc + RCC_DDRCPCFGR, + RCC_DDRCPCFGR_DDRCPEN | RCC_DDRCPCFGR_DDRCPLPEN | RCC_DDRCPCFGR_DDRCPRST); + mmio_setbits_32(priv->rcc + RCC_DDRITFCFGR, RCC_DDRITFCFGR_DDRRST); + mmio_write_32(priv->rcc + RCC_DDRPHYCAPBCFGR, + RCC_DDRPHYCAPBCFGR_DDRPHYCAPBEN | RCC_DDRPHYCAPBCFGR_DDRPHYCAPBLPEN | + RCC_DDRPHYCAPBCFGR_DDRPHYCAPBRST); + mmio_write_32(priv->rcc + RCC_DDRCAPBCFGR, + RCC_DDRCAPBCFGR_DDRCAPBEN | RCC_DDRCAPBCFGR_DDRCAPBLPEN | + RCC_DDRCAPBCFGR_DDRCAPBRST); + + mmio_clrbits_32(priv->rcc + RCC_DDRITFCFGR, RCC_DDRITFCFGR_DDRPHYDLP); + mmio_setbits_32(priv->rcc + RCC_DDRPHYCCFGR, RCC_DDRPHYCCFGR_DDRPHYCEN); + + udelay(DDR_DELAY_1US); +} + +static void ddr_standby_reset_release(struct stm32mp_ddr_priv *priv) +{ + udelay(DDR_DELAY_1US); + + mmio_write_32(priv->rcc + RCC_DDRCPCFGR, RCC_DDRCPCFGR_DDRCPEN | RCC_DDRCPCFGR_DDRCPLPEN); + mmio_clrbits_32(priv->rcc + RCC_DDRITFCFGR, RCC_DDRITFCFGR_DDRRST); + mmio_clrbits_32(priv->rcc + RCC_DDRPHYCAPBCFGR, RCC_DDRPHYCAPBCFGR_DDRPHYCAPBRST); + mmio_write_32(priv->rcc + RCC_DDRCFGR, RCC_DDRCFGR_DDRCFGEN | RCC_DDRCFGR_DDRCFGLPEN); + + udelay(DDR_DELAY_1US); +} + +static void ddr_sysconf_configuration(struct stm32mp_ddr_priv *priv, + struct stm32mp_ddr_config *config) +{ + mmio_write_32(stm32_ddrdbg_get_base() + DDRDBG_LP_DISABLE, + DDRDBG_LP_DISABLE_LPI_XPI_DISABLE | DDRDBG_LP_DISABLE_LPI_DDRC_DISABLE); + + mmio_write_32(stm32_ddrdbg_get_base() + DDRDBG_BYPASS_PCLKEN, + (uint32_t)config->uib.pllbypass); + + mmio_write_32(priv->rcc + RCC_DDRPHYCCFGR, RCC_DDRPHYCCFGR_DDRPHYCEN); + mmio_setbits_32(priv->rcc + RCC_DDRITFCFGR, RCC_DDRITFCFGR_DDRRST); + + udelay(DDR_DELAY_1US); +} + +static void set_dfi_init_complete_en(struct stm32mp_ddrctl *ctl, bool phy_init_done) +{ + /* + * Manage quasi-dynamic registers modification + * dfimisc.dfi_init_complete_en : Group 3 + */ + stm32mp_ddr_set_qd3_update_conditions(ctl); + + udelay(DDR_DELAY_1US); + + if (phy_init_done) { + /* Indicates to controller that PHY has completed initialization */ + mmio_setbits_32((uintptr_t)&ctl->dfimisc, DDRCTRL_DFIMISC_DFI_INIT_COMPLETE_EN); + } else { + /* PHY not initialized yet, wait for completion */ + mmio_clrbits_32((uintptr_t)&ctl->dfimisc, DDRCTRL_DFIMISC_DFI_INIT_COMPLETE_EN); + } + + udelay(DDR_DELAY_1US); + + stm32mp_ddr_unset_qd3_update_conditions(ctl); + +} + +static void disable_refresh(struct stm32mp_ddrctl *ctl) +{ + mmio_setbits_32((uintptr_t)&ctl->rfshctl3, DDRCTRL_RFSHCTL3_DIS_AUTO_REFRESH); + + stm32mp_ddr_wait_refresh_update_done_ack(ctl); + + udelay(DDR_DELAY_1US); + + mmio_clrbits_32((uintptr_t)&ctl->pwrctl, + DDRCTRL_PWRCTL_POWERDOWN_EN | DDRCTRL_PWRCTL_SELFREF_EN); + + udelay(DDR_DELAY_1US); + + set_dfi_init_complete_en(ctl, false); +} + +static void restore_refresh(struct stm32mp_ddrctl *ctl, uint32_t rfshctl3, uint32_t pwrctl) +{ + if ((rfshctl3 & DDRCTRL_RFSHCTL3_DIS_AUTO_REFRESH) == 0U) { + mmio_clrbits_32((uintptr_t)&ctl->rfshctl3, DDRCTRL_RFSHCTL3_DIS_AUTO_REFRESH); + + stm32mp_ddr_wait_refresh_update_done_ack(ctl); + + udelay(DDR_DELAY_1US); + } + + if ((pwrctl & DDRCTRL_PWRCTL_SELFREF_SW) != 0U) { + mmio_clrbits_32((uintptr_t)&ctl->pwrctl, DDRCTRL_PWRCTL_SELFREF_SW); + + udelay(DDR_DELAY_1US); + } + + if ((pwrctl & DDRCTRL_PWRCTL_POWERDOWN_EN) != 0U) { + mmio_setbits_32((uintptr_t)&ctl->pwrctl, DDRCTRL_PWRCTL_POWERDOWN_EN); + + udelay(DDR_DELAY_1US); + } + + if ((pwrctl & DDRCTRL_PWRCTL_SELFREF_EN) != 0U) { + mmio_setbits_32((uintptr_t)&ctl->pwrctl, DDRCTRL_PWRCTL_SELFREF_EN); + + udelay(DDR_DELAY_1US); + } + + set_dfi_init_complete_en(ctl, true); +} + +void stm32mp2_ddr_init(struct stm32mp_ddr_priv *priv, + struct stm32mp_ddr_config *config) +{ + int ret = -EINVAL; + uint32_t ddr_retdis; + enum ddr_type ddr_type; + + if ((config->c_reg.mstr & DDRCTRL_MSTR_DDR3) != 0U) { + ddr_type = STM32MP_DDR3; + } else if ((config->c_reg.mstr & DDRCTRL_MSTR_DDR4) != 0U) { + ddr_type = STM32MP_DDR4; + } else if ((config->c_reg.mstr & DDRCTRL_MSTR_LPDDR4) != 0U) { + ddr_type = STM32MP_LPDDR4; + } else { + ERROR("DDR type not supported\n"); + panic(); + } + + VERBOSE("name = %s\n", config->info.name); + VERBOSE("speed = %u kHz\n", config->info.speed); + VERBOSE("size = 0x%zx\n", config->info.size); + if (config->self_refresh) { + VERBOSE("sel-refresh exit (zdata = 0x%x)\n", config->zdata); + } + + /* Check DDR PHY pads retention */ + ddr_retdis = mmio_read_32(priv->pwr + PWR_CR11) & PWR_CR11_DDRRETDIS; + if (config->self_refresh) { + if (ddr_retdis == PWR_CR11_DDRRETDIS) { + VERBOSE("self-refresh aborted: no retention\n"); + config->self_refresh = false; + } + } + + if (config->self_refresh) { + ddr_standby_reset(priv); + + VERBOSE("disable DDR PHY retention\n"); + mmio_setbits_32(priv->pwr + PWR_CR11, PWR_CR11_DDRRETDIS); + + udelay(DDR_DELAY_1US); + + mmio_clrbits_32(priv->rcc + RCC_DDRCAPBCFGR, RCC_DDRCAPBCFGR_DDRCAPBRST); + + udelay(DDR_DELAY_1US); + + } else { + if (stm32mp_board_ddr_power_init(ddr_type) != 0) { + ERROR("DDR power init failed\n"); + panic(); + } + + VERBOSE("disable DDR PHY retention\n"); + mmio_setbits_32(priv->pwr + PWR_CR11, PWR_CR11_DDRRETDIS); + + ddr_reset(priv); + + ddr_sysconf_configuration(priv, config); + } + +#if STM32MP_LPDDR4_TYPE + /* + * Enable PWRCTL.SELFREF_SW to ensure correct setting of PWRCTL.LPDDR4_SR_ALLOWED. + * Later disabled in restore_refresh(). + */ + config->c_reg.pwrctl |= DDRCTRL_PWRCTL_SELFREF_SW; +#endif /* STM32MP_LPDDR4_TYPE */ + + stm32mp_ddr_set_reg(priv, REG_REG, &config->c_reg, ddr_registers); + stm32mp_ddr_set_reg(priv, REG_TIMING, &config->c_timing, ddr_registers); + stm32mp_ddr_set_reg(priv, REG_MAP, &config->c_map, ddr_registers); + stm32mp_ddr_set_reg(priv, REG_PERF, &config->c_perf, ddr_registers); + + if (!config->self_refresh) { + /* DDR core and PHY reset de-assert */ + mmio_clrbits_32(priv->rcc + RCC_DDRITFCFGR, RCC_DDRITFCFGR_DDRRST); + + disable_refresh(priv->ctl); + } + + if (config->self_refresh) { + ddr_standby_reset_release(priv); + + /* Initialize DDR by skipping training and disabling result saving */ + ret = ddrphy_phyinit_sequence(config, true, false); + + if (ret == 0) { + ret = ddrphy_phyinit_restore_sequence(); + } + + /* Poll on ddrphy_initeng0_phyinlpx.phyinlp3 = 0 */ + ddr_wait_lp3_mode(false); + } else { + /* Initialize DDR including training and result saving */ + ret = ddrphy_phyinit_sequence(config, false, true); + } + + if (ret != 0) { + ERROR("DDR PHY init: Error %d\n", ret); + panic(); + } + + ddr_activate_controller(priv->ctl, false); + + if (config->self_refresh) { + struct stm32mp_ddrctl *ctl = priv->ctl; + + /* SW self refresh exit prequested */ + mmio_clrbits_32((uintptr_t)&ctl->pwrctl, DDRCTRL_PWRCTL_SELFREF_SW); + + if (ddr_sr_exit_loop() != 0) { + ERROR("DDR Standby exit error\n"); + panic(); + } + + /* Re-enable DFI low-power interface */ + mmio_clrbits_32((uintptr_t)&ctl->dfilpcfg0, DDRCTRL_DFILPCFG0_DFI_LP_EN_SR); + } else { + restore_refresh(priv->ctl, config->c_reg.rfshctl3, config->c_reg.pwrctl); + } + + stm32mp_ddr_enable_axi_port(priv->ctl); +} diff --git a/drivers/st/ddr/stm32mp2_ddr_helpers.c b/drivers/st/ddr/stm32mp2_ddr_helpers.c index e6be9ddaa..a2a408224 100644 --- a/drivers/st/ddr/stm32mp2_ddr_helpers.c +++ b/drivers/st/ddr/stm32mp2_ddr_helpers.c @@ -4,12 +4,524 @@ * SPDX-License-Identifier: BSD-3-Clause */ +#include + +#include +#include + +#include +#include +#include +#include +#include + #include #include +/* HW idle period (unit: Multiples of 32 DFI clock cycles) */ +#define HW_IDLE_PERIOD 0x3U + +static enum stm32mp2_ddr_sr_mode saved_ddr_sr_mode; + +#pragma weak stm32_ddrdbg_get_base +uintptr_t stm32_ddrdbg_get_base(void) +{ + return 0U; +} + +static void set_qd1_qd3_update_conditions(struct stm32mp_ddrctl *ctl) +{ + mmio_setbits_32((uintptr_t)&ctl->dbg1, DDRCTRL_DBG1_DIS_DQ); + + stm32mp_ddr_set_qd3_update_conditions(ctl); +} + +static void unset_qd1_qd3_update_conditions(struct stm32mp_ddrctl *ctl) +{ + stm32mp_ddr_unset_qd3_update_conditions(ctl); + + mmio_clrbits_32((uintptr_t)&ctl->dbg1, DDRCTRL_DBG1_DIS_DQ); +} + +static void wait_dfi_init_complete(struct stm32mp_ddrctl *ctl) +{ + uint64_t timeout; + uint32_t dfistat; + + timeout = timeout_init_us(DDR_TIMEOUT_US_1S); + do { + dfistat = mmio_read_32((uintptr_t)&ctl->dfistat); + VERBOSE("[0x%lx] dfistat = 0x%x ", (uintptr_t)&ctl->dfistat, dfistat); + + if (timeout_elapsed(timeout)) { + panic(); + } + } while ((dfistat & DDRCTRL_DFISTAT_DFI_INIT_COMPLETE) == 0U); + + VERBOSE("[0x%lx] dfistat = 0x%x\n", (uintptr_t)&ctl->dfistat, dfistat); +} + +static void disable_dfi_low_power_interface(struct stm32mp_ddrctl *ctl) +{ + uint64_t timeout; + uint32_t dfistat; + uint32_t stat; + + mmio_clrbits_32((uintptr_t)&ctl->dfilpcfg0, DDRCTRL_DFILPCFG0_DFI_LP_EN_SR); + + timeout = timeout_init_us(DDR_TIMEOUT_US_1S); + do { + dfistat = mmio_read_32((uintptr_t)&ctl->dfistat); + stat = mmio_read_32((uintptr_t)&ctl->stat); + VERBOSE("[0x%lx] dfistat = 0x%x ", (uintptr_t)&ctl->dfistat, dfistat); + VERBOSE("[0x%lx] stat = 0x%x ", (uintptr_t)&ctl->stat, stat); + + if (timeout_elapsed(timeout)) { + panic(); + } + } while (((dfistat & DDRCTRL_DFISTAT_DFI_LP_ACK) != 0U) || + ((stat & DDRCTRL_STAT_OPERATING_MODE_MASK) == DDRCTRL_STAT_OPERATING_MODE_SR)); + + VERBOSE("[0x%lx] dfistat = 0x%x\n", (uintptr_t)&ctl->dfistat, dfistat); + VERBOSE("[0x%lx] stat = 0x%x\n", (uintptr_t)&ctl->stat, stat); +} + +void ddr_activate_controller(struct stm32mp_ddrctl *ctl, bool sr_entry) +{ + /* + * Manage quasi-dynamic registers modification + * dfimisc.dfi_frequency : Group 1 + * dfimisc.dfi_init_complete_en and dfimisc.dfi_init_start : Group 3 + */ + set_qd1_qd3_update_conditions(ctl); + + if (sr_entry) { + mmio_setbits_32((uintptr_t)&ctl->dfimisc, DDRCTRL_DFIMISC_DFI_FREQUENCY); + } else { + mmio_clrbits_32((uintptr_t)&ctl->dfimisc, DDRCTRL_DFIMISC_DFI_FREQUENCY); + } + + mmio_setbits_32((uintptr_t)&ctl->dfimisc, DDRCTRL_DFIMISC_DFI_INIT_START); + mmio_clrbits_32((uintptr_t)&ctl->dfimisc, DDRCTRL_DFIMISC_DFI_INIT_START); + + wait_dfi_init_complete(ctl); + + udelay(DDR_DELAY_1US); + + if (sr_entry) { + mmio_clrbits_32((uintptr_t)&ctl->dfimisc, DDRCTRL_DFIMISC_DFI_INIT_COMPLETE_EN); + } else { + mmio_setbits_32((uintptr_t)&ctl->dfimisc, DDRCTRL_DFIMISC_DFI_INIT_COMPLETE_EN); + } + + udelay(DDR_DELAY_1US); + + unset_qd1_qd3_update_conditions(ctl); +} + +#if STM32MP_LPDDR4_TYPE +static void disable_phy_ddc(void) +{ + /* Enable APB access to internal CSR registers */ + mmio_write_32(stm32mp_ddrphyc_base() + DDRPHY_APBONLY0_MICROCONTMUXSEL, 0U); + mmio_write_32(stm32mp_ddrphyc_base() + DDRPHY_DRTUB0_UCCLKHCLKENABLES, + DDRPHY_DRTUB0_UCCLKHCLKENABLES_UCCLKEN | + DDRPHY_DRTUB0_UCCLKHCLKENABLES_HCLKEN); + + /* Disable DRAM drift compensation */ + mmio_write_32(stm32mp_ddrphyc_base() + DDRPHY_INITENG0_P0_SEQ0BDISABLEFLAG6, 0xFFFFU); + + /* Disable APB access to internal CSR registers */ + mmio_write_32(stm32mp_ddrphyc_base() + DDRPHY_DRTUB0_UCCLKHCLKENABLES, + DDRPHY_DRTUB0_UCCLKHCLKENABLES_HCLKEN); + mmio_write_32(stm32mp_ddrphyc_base() + DDRPHY_APBONLY0_MICROCONTMUXSEL, + DDRPHY_APBONLY0_MICROCONTMUXSEL_MICROCONTMUXSEL); +} +#endif /* STM32MP_LPDDR4_TYPE */ + +void ddr_wait_lp3_mode(bool sr_entry) +{ + uint64_t timeout; + bool repeat_loop = false; + + /* Enable APB access to internal CSR registers */ + mmio_write_32(stm32mp_ddrphyc_base() + DDRPHY_APBONLY0_MICROCONTMUXSEL, 0U); + mmio_write_32(stm32mp_ddrphyc_base() + DDRPHY_DRTUB0_UCCLKHCLKENABLES, + DDRPHY_DRTUB0_UCCLKHCLKENABLES_UCCLKEN | + DDRPHY_DRTUB0_UCCLKHCLKENABLES_HCLKEN); + + timeout = timeout_init_us(DDR_TIMEOUT_US_1S); + do { + uint16_t phyinlpx = mmio_read_32(stm32mp_ddrphyc_base() + + DDRPHY_INITENG0_P0_PHYINLPX); + + if (timeout_elapsed(timeout)) { + panic(); + } + + if (sr_entry) { + repeat_loop = (phyinlpx & DDRPHY_INITENG0_P0_PHYINLPX_PHYINLP3) == 0U; + } else { + repeat_loop = (phyinlpx & DDRPHY_INITENG0_P0_PHYINLPX_PHYINLP3) != 0U; + } + } while (repeat_loop); + + /* Disable APB access to internal CSR registers */ +#if STM32MP_DDR3_TYPE || STM32MP_DDR4_TYPE + mmio_write_32(stm32mp_ddrphyc_base() + DDRPHY_DRTUB0_UCCLKHCLKENABLES, 0U); +#else /* STM32MP_LPDDR4_TYPE */ + mmio_write_32(stm32mp_ddrphyc_base() + DDRPHY_DRTUB0_UCCLKHCLKENABLES, + DDRPHY_DRTUB0_UCCLKHCLKENABLES_HCLKEN); +#endif /* STM32MP_DDR3_TYPE || STM32MP_DDR4_TYPE */ + mmio_write_32(stm32mp_ddrphyc_base() + DDRPHY_APBONLY0_MICROCONTMUXSEL, + DDRPHY_APBONLY0_MICROCONTMUXSEL_MICROCONTMUXSEL); +} + +static int sr_loop(bool is_entry) +{ + uint32_t type; + uint32_t state __maybe_unused; + uint64_t timeout = timeout_init_us(DDR_TIMEOUT_US_1S); + bool repeat_loop = false; + + /* + * Wait for DDRCTRL to be out of or back to "normal/mission mode". + * Consider also SRPD mode for LPDDR4 only. + */ + do { + type = mmio_read_32(stm32mp_ddrctrl_base() + DDRCTRL_STAT) & + DDRCTRL_STAT_SELFREF_TYPE_MASK; +#if STM32MP_LPDDR4_TYPE + state = mmio_read_32(stm32mp_ddrctrl_base() + DDRCTRL_STAT) & + DDRCTRL_STAT_SELFREF_STATE_MASK; +#endif /* STM32MP_LPDDR4_TYPE */ + + if (timeout_elapsed(timeout)) { + return -ETIMEDOUT; + } + + if (is_entry) { +#if STM32MP_LPDDR4_TYPE + repeat_loop = (type == 0x0U) || (state != DDRCTRL_STAT_SELFREF_STATE_SRPD); +#else /* !STM32MP_LPDDR4_TYPE */ + repeat_loop = (type == 0x0U); +#endif /* STM32MP_LPDDR4_TYPE */ + } else { +#if STM32MP_LPDDR4_TYPE + repeat_loop = (type != 0x0U) || (state != 0x0U); +#else /* !STM32MP_LPDDR4_TYPE */ + repeat_loop = (type != 0x0U); +#endif /* STM32MP_LPDDR4_TYPE */ + } + } while (repeat_loop); + + return 0; +} + +static int sr_entry_loop(void) +{ + return sr_loop(true); +} + +int ddr_sr_exit_loop(void) +{ + return sr_loop(false); +} + +static int sr_ssr_set(void) +{ + uintptr_t ddrctrl_base = stm32mp_ddrctrl_base(); + + /* + * Disable Clock disable with LP modes + * (used in RUN mode for LPDDR2 with specific timing). + */ + mmio_clrbits_32(ddrctrl_base + DDRCTRL_PWRCTL, DDRCTRL_PWRCTL_EN_DFI_DRAM_CLK_DISABLE); + + /* Disable automatic Self-Refresh mode */ + mmio_clrbits_32(ddrctrl_base + DDRCTRL_PWRCTL, DDRCTRL_PWRCTL_SELFREF_EN); + + mmio_write_32(stm32_ddrdbg_get_base() + DDRDBG_LP_DISABLE, + DDRDBG_LP_DISABLE_LPI_XPI_DISABLE | DDRDBG_LP_DISABLE_LPI_DDRC_DISABLE); + + return 0; +} + +static int sr_ssr_entry(bool standby) +{ + uintptr_t ddrctrl_base = stm32mp_ddrctrl_base(); + uintptr_t rcc_base = stm32mp_rcc_base(); + + if (stm32mp_ddr_disable_axi_port((struct stm32mp_ddrctl *)ddrctrl_base) != 0) { + panic(); + } + +#if STM32MP_LPDDR4_TYPE + if (standby) { + /* Disable DRAM drift compensation */ + disable_phy_ddc(); + } +#endif /* STM32MP_LPDDR4_TYPE */ + + disable_dfi_low_power_interface((struct stm32mp_ddrctl *)ddrctrl_base); + + /* SW self refresh entry prequested */ + mmio_setbits_32(ddrctrl_base + DDRCTRL_PWRCTL, DDRCTRL_PWRCTL_SELFREF_SW); +#if STM32MP_LPDDR4_TYPE + mmio_clrbits_32(ddrctrl_base + DDRCTRL_PWRCTL, DDRCTRL_PWRCTL_STAY_IN_SELFREF); +#endif /* STM32MP_LPDDR4_TYPE */ + + if (sr_entry_loop() != 0) { + return -1; + } + + ddr_activate_controller((struct stm32mp_ddrctl *)ddrctrl_base, true); + + /* Poll on ddrphy_initeng0_phyinlpx.phyinlp3 = 1 */ + ddr_wait_lp3_mode(true); + + if (standby) { + mmio_clrbits_32(stm32mp_pwr_base() + PWR_CR11, PWR_CR11_DDRRETDIS); + } + + mmio_clrsetbits_32(rcc_base + RCC_DDRCPCFGR, RCC_DDRCPCFGR_DDRCPLPEN, + RCC_DDRCPCFGR_DDRCPEN); + mmio_setbits_32(rcc_base + RCC_DDRPHYCCFGR, RCC_DDRPHYCCFGR_DDRPHYCEN); + mmio_setbits_32(rcc_base + RCC_DDRITFCFGR, RCC_DDRITFCFGR_DDRPHYDLP); + + return 0; +} + +static int sr_ssr_exit(void) +{ + uintptr_t ddrctrl_base = stm32mp_ddrctrl_base(); + uintptr_t rcc_base = stm32mp_rcc_base(); + + mmio_setbits_32(rcc_base + RCC_DDRCPCFGR, + RCC_DDRCPCFGR_DDRCPLPEN | RCC_DDRCPCFGR_DDRCPEN); + mmio_clrbits_32(rcc_base + RCC_DDRITFCFGR, RCC_DDRITFCFGR_DDRPHYDLP); + mmio_setbits_32(rcc_base + RCC_DDRPHYCCFGR, RCC_DDRPHYCCFGR_DDRPHYCEN); + + udelay(DDR_DELAY_1US); + + ddr_activate_controller((struct stm32mp_ddrctl *)ddrctrl_base, false); + + /* Poll on ddrphy_initeng0_phyinlpx.phyinlp3 = 0 */ + ddr_wait_lp3_mode(false); + + /* SW self refresh exit prequested */ + mmio_clrbits_32(ddrctrl_base + DDRCTRL_PWRCTL, DDRCTRL_PWRCTL_SELFREF_SW); + + if (ddr_sr_exit_loop() != 0) { + return -1; + } + + /* Re-enable DFI low-power interface */ + mmio_setbits_32(ddrctrl_base + DDRCTRL_DFILPCFG0, DDRCTRL_DFILPCFG0_DFI_LP_EN_SR); + + stm32mp_ddr_enable_axi_port((struct stm32mp_ddrctl *)ddrctrl_base); + + return 0; +} + +static int sr_hsr_set(void) +{ + uintptr_t ddrctrl_base = stm32mp_ddrctrl_base(); + + mmio_clrsetbits_32(stm32mp_rcc_base() + RCC_DDRITFCFGR, + RCC_DDRITFCFGR_DDRCKMOD_MASK, RCC_DDRITFCFGR_DDRCKMOD_HSR); + + /* + * manage quasi-dynamic registers modification + * hwlpctl.hw_lp_en : Group 2 + */ + if (stm32mp_ddr_sw_selfref_entry((struct stm32mp_ddrctl *)ddrctrl_base) != 0) { + panic(); + } + stm32mp_ddr_start_sw_done((struct stm32mp_ddrctl *)ddrctrl_base); + + mmio_write_32(ddrctrl_base + DDRCTRL_HWLPCTL, + DDRCTRL_HWLPCTL_HW_LP_EN | DDRCTRL_HWLPCTL_HW_LP_EXIT_IDLE_EN | + (HW_IDLE_PERIOD << DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_SHIFT)); + + stm32mp_ddr_wait_sw_done_ack((struct stm32mp_ddrctl *)ddrctrl_base); + stm32mp_ddr_sw_selfref_exit((struct stm32mp_ddrctl *)ddrctrl_base); + + return 0; +} + +static int sr_hsr_entry(void) +{ + mmio_write_32(stm32mp_rcc_base() + RCC_DDRCPCFGR, RCC_DDRCPCFGR_DDRCPLPEN); + + return sr_entry_loop(); /* read_data should be equal to 0x223 */ +} + +static int sr_hsr_exit(void) +{ + mmio_write_32(stm32mp_rcc_base() + RCC_DDRCPCFGR, + RCC_DDRCPCFGR_DDRCPLPEN | RCC_DDRCPCFGR_DDRCPEN); + + /* TODO: check if ddr_sr_exit_loop() is needed here */ + + return 0; +} + +static int sr_asr_set(void) +{ + mmio_write_32(stm32_ddrdbg_get_base() + DDRDBG_LP_DISABLE, 0U); + + return 0; +} + +static int sr_asr_entry(void) +{ + /* + * Automatically enter into self refresh when there is no ddr traffic + * for the delay programmed into SYSCONF_DDRC_AUTO_SR_DELAY register. + * Default value is 0x20 (unit: Multiples of 32 DFI clock cycles). + */ + return sr_entry_loop(); +} + +static int sr_asr_exit(void) +{ + return ddr_sr_exit_loop(); +} + +uint32_t ddr_get_io_calibration_val(void) +{ + /* TODO create related service */ + + return 0U; +} + +int ddr_sr_entry(bool standby) +{ + int ret = -EINVAL; + + switch (saved_ddr_sr_mode) { + case DDR_SSR_MODE: + ret = sr_ssr_entry(standby); + break; + case DDR_HSR_MODE: + ret = sr_hsr_entry(); + break; + case DDR_ASR_MODE: + ret = sr_asr_entry(); + break; + default: + break; + } + + return ret; +} + +int ddr_sr_exit(void) +{ + int ret = -EINVAL; + + switch (saved_ddr_sr_mode) { + case DDR_SSR_MODE: + ret = sr_ssr_exit(); + break; + case DDR_HSR_MODE: + ret = sr_hsr_exit(); + break; + case DDR_ASR_MODE: + ret = sr_asr_exit(); + break; + default: + break; + } + + return ret; +} + +enum stm32mp2_ddr_sr_mode ddr_read_sr_mode(void) +{ + uint32_t pwrctl = mmio_read_32(stm32mp_ddrctrl_base() + DDRCTRL_PWRCTL); + enum stm32mp2_ddr_sr_mode mode = DDR_SR_MODE_INVALID; + + switch (pwrctl & (DDRCTRL_PWRCTL_EN_DFI_DRAM_CLK_DISABLE | + DDRCTRL_PWRCTL_SELFREF_EN)) { + case 0U: + mode = DDR_SSR_MODE; + break; + case DDRCTRL_PWRCTL_EN_DFI_DRAM_CLK_DISABLE: + mode = DDR_HSR_MODE; + break; + case DDRCTRL_PWRCTL_EN_DFI_DRAM_CLK_DISABLE | DDRCTRL_PWRCTL_SELFREF_EN: + mode = DDR_ASR_MODE; + break; + default: + break; + } + + return mode; +} + +void ddr_set_sr_mode(enum stm32mp2_ddr_sr_mode mode) +{ + int ret = -EINVAL; + + if (mode == saved_ddr_sr_mode) { + return; + } + + switch (mode) { + case DDR_SSR_MODE: + ret = sr_ssr_set(); + break; + case DDR_HSR_MODE: + ret = sr_hsr_set(); + break; + case DDR_ASR_MODE: + ret = sr_asr_set(); + break; + default: + break; + } + + if (ret != 0) { + ERROR("Unknown Self Refresh mode\n"); + panic(); + } + + saved_ddr_sr_mode = mode; +} + +void ddr_save_sr_mode(void) +{ + saved_ddr_sr_mode = ddr_read_sr_mode(); +} + +void ddr_restore_sr_mode(void) +{ + ddr_set_sr_mode(saved_ddr_sr_mode); +} + void ddr_sub_system_clk_init(void) { mmio_write_32(stm32mp_rcc_base() + RCC_DDRCPCFGR, RCC_DDRCPCFGR_DDRCPEN | RCC_DDRCPCFGR_DDRCPLPEN); } + +void ddr_sub_system_clk_off(void) +{ + uintptr_t rcc_base = stm32mp_rcc_base(); + + /* Clear DDR IO retention */ + mmio_clrbits_32(stm32mp_pwr_base() + PWR_CR11, PWR_CR11_DDRRETDIS); + + /* Reset DDR sub system */ + mmio_write_32(rcc_base + RCC_DDRCPCFGR, RCC_DDRCPCFGR_DDRCPRST); + mmio_write_32(rcc_base + RCC_DDRITFCFGR, RCC_DDRITFCFGR_DDRRST); + mmio_write_32(rcc_base + RCC_DDRPHYCAPBCFGR, RCC_DDRPHYCAPBCFGR_DDRPHYCAPBRST); + mmio_write_32(rcc_base + RCC_DDRCAPBCFGR, RCC_DDRCAPBCFGR_DDRCAPBRST); + + /* Deactivate clocks and PLL2 */ + mmio_clrbits_32(rcc_base + RCC_DDRPHYCCFGR, RCC_DDRPHYCCFGR_DDRPHYCEN); + mmio_clrbits_32(rcc_base + RCC_PLL2CFGR1, RCC_PLL2CFGR1_PLLEN); +} diff --git a/drivers/st/ddr/stm32mp2_ram.c b/drivers/st/ddr/stm32mp2_ram.c new file mode 100644 index 000000000..95f05e7bc --- /dev/null +++ b/drivers/st/ddr/stm32mp2_ram.c @@ -0,0 +1,210 @@ +/* + * Copyright (C) 2021-2024, STMicroelectronics - All Rights Reserved + * + * SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause + */ + +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#include + +static struct stm32mp_ddr_priv ddr_priv_data; +static bool ddr_self_refresh; + +static int ddr_dt_get_ui_param(void *fdt, int node, struct stm32mp_ddr_config *config) +{ + int ret; + uint32_t size; + + size = sizeof(struct user_input_basic) / sizeof(int); + ret = fdt_read_uint32_array(fdt, node, "st,phy-basic", size, (uint32_t *)&config->uib); + + VERBOSE("%s: %s[0x%x] = %d\n", __func__, "st,phy-basic", size, ret); + if (ret != 0) { + ERROR("%s: can't read %s, error=%d\n", __func__, "st,phy-basic", ret); + return -EINVAL; + } + + size = sizeof(struct user_input_advanced) / sizeof(int); + ret = fdt_read_uint32_array(fdt, node, "st,phy-advanced", size, (uint32_t *)&config->uia); + + VERBOSE("%s: %s[0x%x] = %d\n", __func__, "st,phy-advanced", size, ret); + if (ret != 0) { + ERROR("%s: can't read %s, error=%d\n", __func__, "st,phy-advanced", ret); + return -EINVAL; + } + + size = sizeof(struct user_input_mode_register) / sizeof(int); + ret = fdt_read_uint32_array(fdt, node, "st,phy-mr", size, (uint32_t *)&config->uim); + + VERBOSE("%s: %s[0x%x] = %d\n", __func__, "st,phy-mr", size, ret); + if (ret != 0) { + ERROR("%s: can't read %s, error=%d\n", __func__, "st,phy-mr", ret); + return -EINVAL; + } + + size = sizeof(struct user_input_swizzle) / sizeof(int); + ret = fdt_read_uint32_array(fdt, node, "st,phy-swizzle", size, (uint32_t *)&config->uis); + + VERBOSE("%s: %s[0x%x] = %d\n", __func__, "st,phy-swizzle", size, ret); + if (ret != 0) { + ERROR("%s: can't read %s, error=%d\n", __func__, "st,phy-swizzle", ret); + return -EINVAL; + } + + return 0; +} + +static int stm32mp2_ddr_setup(void) +{ + struct stm32mp_ddr_priv *priv = &ddr_priv_data; + int ret; + struct stm32mp_ddr_config config; + int node; + uintptr_t uret; + void *fdt; + + const struct stm32mp_ddr_param param[] = { + CTL_PARAM(reg), + CTL_PARAM(timing), + CTL_PARAM(map), + CTL_PARAM(perf) + }; + + if (fdt_get_address(&fdt) == 0) { + return -ENOENT; + } + + node = fdt_node_offset_by_compatible(fdt, -1, DT_DDR_COMPAT); + if (node < 0) { + ERROR("%s: can't read DDR node in DT\n", __func__); + return -EINVAL; + } + + ret = stm32mp_ddr_dt_get_info(fdt, node, &config.info); + if (ret < 0) { + return ret; + } + + ret = stm32mp_ddr_dt_get_param(fdt, node, param, ARRAY_SIZE(param), (uintptr_t)&config); + if (ret < 0) { + return ret; + } + + ret = ddr_dt_get_ui_param(fdt, node, &config); + if (ret < 0) { + return ret; + } + + config.self_refresh = false; + + if (stm32mp_is_wakeup_from_standby()) { + config.self_refresh = true; + } + + /* Map dynamically RETRAM area to save or restore PHY retention registers */ + if (stm32mp_map_retram() != 0) { + panic(); + } + + stm32mp2_ddr_init(priv, &config); + + /* Unmap RETRAM, no more used until next DDR initialization call */ + if (stm32mp_unmap_retram() != 0) { + panic(); + } + + priv->info.size = config.info.size; + + VERBOSE("%s : ram size(%lx, %lx)\n", __func__, priv->info.base, priv->info.size); + + if (stm32mp_map_ddr_non_cacheable() != 0) { + panic(); + } + + if (config.self_refresh) { + uret = stm32mp_ddr_test_rw_access(); + if (uret != 0UL) { + ERROR("DDR rw test: can't access memory @ 0x%lx\n", uret); + panic(); + } + + /* TODO Restore area overwritten by training */ + //stm32_restore_ddr_training_area(); + } else { + size_t retsize; + + uret = stm32mp_ddr_test_data_bus(); + if (uret != 0UL) { + ERROR("DDR data bus test: can't access memory @ 0x%lx\n", uret); + panic(); + } + + uret = stm32mp_ddr_test_addr_bus(config.info.size); + if (uret != 0UL) { + ERROR("DDR addr bus test: can't access memory @ 0x%lx\n", uret); + panic(); + } + + retsize = stm32mp_ddr_check_size(); + if (retsize < config.info.size) { + ERROR("DDR size: 0x%zx does not match DT config: 0x%zx\n", + retsize, config.info.size); + panic(); + } + + INFO("Memory size = 0x%zx (%zu MB)\n", retsize, retsize / (1024U * 1024U)); + } + + /* + * Initialization sequence has configured DDR registers with settings. + * The Self Refresh (SR) mode corresponding to these settings has now + * to be set. + */ + ddr_set_sr_mode(ddr_read_sr_mode()); + + if (stm32mp_unmap_ddr() != 0) { + panic(); + } + + /* Save DDR self_refresh state */ + ddr_self_refresh = config.self_refresh; + + return 0; +} + +bool stm32mp2_ddr_is_restored(void) +{ + return ddr_self_refresh; +} + +int stm32mp2_ddr_probe(void) +{ + struct stm32mp_ddr_priv *priv = &ddr_priv_data; + + VERBOSE("STM32MP DDR probe\n"); + + priv->ctl = (struct stm32mp_ddrctl *)stm32mp_ddrctrl_base(); + priv->phy = (struct stm32mp_ddrphy *)stm32mp_ddrphyc_base(); + priv->pwr = stm32mp_pwr_base(); + priv->rcc = stm32mp_rcc_base(); + + priv->info.base = STM32MP_DDR_BASE; + priv->info.size = 0; + + return stm32mp2_ddr_setup(); +} diff --git a/drivers/st/ddr/stm32mp_ddr.c b/drivers/st/ddr/stm32mp_ddr.c index 26ad078ce..98968d572 100644 --- a/drivers/st/ddr/stm32mp_ddr.c +++ b/drivers/st/ddr/stm32mp_ddr.c @@ -44,9 +44,19 @@ void stm32mp_ddr_set_reg(const struct stm32mp_ddr_priv *priv, enum stm32mp_ddr_r ddr_registers[type].name, i); panic(); } else { +#if !STM32MP13 && !STM32MP15 + if (desc[i].qd) { + stm32mp_ddr_start_sw_done(priv->ctl); + } +#endif value = *((uint32_t *)((uintptr_t)param + desc[i].par_offset)); mmio_write_32(ptr, value); +#if !STM32MP13 && !STM32MP15 + if (desc[i].qd) { + stm32mp_ddr_wait_sw_done_ack(priv->ctl); + } +#endif } } } diff --git a/drivers/st/ddr/stm32mp_ddr_test.c b/drivers/st/ddr/stm32mp_ddr_test.c index 0f6aff1db..707a6ff08 100644 --- a/drivers/st/ddr/stm32mp_ddr_test.c +++ b/drivers/st/ddr/stm32mp_ddr_test.c @@ -1,5 +1,5 @@ /* - * Copyright (C) 2022-2023, STMicroelectronics - All Rights Reserved + * Copyright (C) 2022-2024, STMicroelectronics - All Rights Reserved * * SPDX-License-Identifier: BSD-3-Clause */ @@ -10,8 +10,31 @@ #include +#ifdef __aarch64__ +#define DDR_PATTERN 0xAAAAAAAAAAAAAAAAUL +#define DDR_ANTIPATTERN 0x5555555555555555UL +#else /* !__aarch64__ */ #define DDR_PATTERN 0xAAAAAAAAU #define DDR_ANTIPATTERN 0x55555555U +#endif /* __aarch64__ */ + +static void mmio_write_pattern(uintptr_t addr, u_register_t value) +{ +#ifdef __aarch64__ + mmio_write_64(addr, (uint64_t)value); +#else /* !__aarch64__ */ + mmio_write_32(addr, (uint32_t)value); +#endif /* __aarch64__ */ +} + +static u_register_t mmio_read_pattern(uintptr_t addr) +{ +#ifdef __aarch64__ + return (u_register_t)mmio_read_64(addr); +#else /* !__aarch64__ */ + return (u_register_t)mmio_read_32(addr); +#endif /* __aarch64__ */ +} /******************************************************************************* * This function tests a simple read/write access to the DDR. @@ -20,15 +43,15 @@ ******************************************************************************/ uintptr_t stm32mp_ddr_test_rw_access(void) { - uint32_t saved_value = mmio_read_32(STM32MP_DDR_BASE); + u_register_t saved_value = mmio_read_pattern(STM32MP_DDR_BASE); - mmio_write_32(STM32MP_DDR_BASE, DDR_PATTERN); + mmio_write_pattern(STM32MP_DDR_BASE, DDR_PATTERN); - if (mmio_read_32(STM32MP_DDR_BASE) != DDR_PATTERN) { + if (mmio_read_pattern(STM32MP_DDR_BASE) != DDR_PATTERN) { return STM32MP_DDR_BASE; } - mmio_write_32(STM32MP_DDR_BASE, saved_value); + mmio_write_pattern(STM32MP_DDR_BASE, saved_value); return 0UL; } @@ -43,12 +66,12 @@ uintptr_t stm32mp_ddr_test_rw_access(void) ******************************************************************************/ uintptr_t stm32mp_ddr_test_data_bus(void) { - uint32_t pattern; + u_register_t pattern; for (pattern = 1U; pattern != 0U; pattern <<= 1U) { - mmio_write_32(STM32MP_DDR_BASE, pattern); + mmio_write_pattern(STM32MP_DDR_BASE, pattern); - if (mmio_read_32(STM32MP_DDR_BASE) != pattern) { + if (mmio_read_pattern(STM32MP_DDR_BASE) != pattern) { return STM32MP_DDR_BASE; } } @@ -72,41 +95,41 @@ uintptr_t stm32mp_ddr_test_addr_bus(size_t size) size_t testoffset = 0U; /* Write the default pattern at each of the power-of-two offsets. */ - for (offset = sizeof(uint32_t); (offset & addressmask) != 0U; + for (offset = sizeof(u_register_t); (offset & addressmask) != 0U; offset <<= 1U) { - mmio_write_32(STM32MP_DDR_BASE + offset, DDR_PATTERN); + mmio_write_pattern(STM32MP_DDR_BASE + offset, DDR_PATTERN); } /* Check for address bits stuck high. */ - mmio_write_32(STM32MP_DDR_BASE + testoffset, DDR_ANTIPATTERN); + mmio_write_pattern(STM32MP_DDR_BASE + testoffset, DDR_ANTIPATTERN); - for (offset = sizeof(uint32_t); (offset & addressmask) != 0U; + for (offset = sizeof(u_register_t); (offset & addressmask) != 0U; offset <<= 1U) { - if (mmio_read_32(STM32MP_DDR_BASE + offset) != DDR_PATTERN) { + if (mmio_read_pattern(STM32MP_DDR_BASE + offset) != DDR_PATTERN) { return STM32MP_DDR_BASE + offset; } } - mmio_write_32(STM32MP_DDR_BASE + testoffset, DDR_PATTERN); + mmio_write_pattern(STM32MP_DDR_BASE + testoffset, DDR_PATTERN); /* Check for address bits stuck low or shorted. */ - for (testoffset = sizeof(uint32_t); (testoffset & addressmask) != 0U; + for (testoffset = sizeof(u_register_t); (testoffset & addressmask) != 0U; testoffset <<= 1U) { - mmio_write_32(STM32MP_DDR_BASE + testoffset, DDR_ANTIPATTERN); + mmio_write_pattern(STM32MP_DDR_BASE + testoffset, DDR_ANTIPATTERN); - if (mmio_read_32(STM32MP_DDR_BASE) != DDR_PATTERN) { + if (mmio_read_pattern(STM32MP_DDR_BASE) != DDR_PATTERN) { return STM32MP_DDR_BASE; } - for (offset = sizeof(uint32_t); (offset & addressmask) != 0U; - offset <<= 1) { - if ((mmio_read_32(STM32MP_DDR_BASE + offset) != DDR_PATTERN) && + for (offset = sizeof(u_register_t); (offset & addressmask) != 0U; + offset <<= 1U) { + if ((mmio_read_pattern(STM32MP_DDR_BASE + offset) != DDR_PATTERN) && (offset != testoffset)) { return STM32MP_DDR_BASE + offset; } } - mmio_write_32(STM32MP_DDR_BASE + testoffset, DDR_PATTERN); + mmio_write_pattern(STM32MP_DDR_BASE + testoffset, DDR_PATTERN); } return 0UL; @@ -121,15 +144,15 @@ uintptr_t stm32mp_ddr_test_addr_bus(size_t size) ******************************************************************************/ size_t stm32mp_ddr_check_size(void) { - size_t offset = sizeof(uint32_t); + size_t offset = sizeof(u_register_t); - mmio_write_32(STM32MP_DDR_BASE, DDR_PATTERN); + mmio_write_pattern(STM32MP_DDR_BASE, DDR_PATTERN); while (offset < STM32MP_DDR_MAX_SIZE) { - mmio_write_32(STM32MP_DDR_BASE + offset, DDR_ANTIPATTERN); + mmio_write_pattern(STM32MP_DDR_BASE + offset, DDR_ANTIPATTERN); dsb(); - if (mmio_read_32(STM32MP_DDR_BASE) != DDR_PATTERN) { + if (mmio_read_pattern(STM32MP_DDR_BASE) != DDR_PATTERN) { break; } diff --git a/include/drivers/st/stm32mp2_ddr.h b/include/drivers/st/stm32mp2_ddr.h new file mode 100644 index 000000000..6b0462c89 --- /dev/null +++ b/include/drivers/st/stm32mp2_ddr.h @@ -0,0 +1,147 @@ +/* + * Copyright (C) 2021-2024, STMicroelectronics - All Rights Reserved + * + * SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause + */ + +#ifndef STM32MP2_DDR_H +#define STM32MP2_DDR_H + +#include + +#include + +#include + +struct stm32mp2_ddrctrl_reg { + uint32_t mstr; + uint32_t mrctrl0; + uint32_t mrctrl1; + uint32_t mrctrl2; + uint32_t derateen; + uint32_t derateint; + uint32_t deratectl; + uint32_t pwrctl; + uint32_t pwrtmg; + uint32_t hwlpctl; + uint32_t rfshctl0; + uint32_t rfshctl1; + uint32_t rfshctl3; + uint32_t crcparctl0; + uint32_t crcparctl1; + uint32_t init0; + uint32_t init1; + uint32_t init2; + uint32_t init3; + uint32_t init4; + uint32_t init5; + uint32_t init6; + uint32_t init7; + uint32_t dimmctl; + uint32_t rankctl; + uint32_t rankctl1; + uint32_t zqctl0; + uint32_t zqctl1; + uint32_t zqctl2; + uint32_t dfitmg0; + uint32_t dfitmg1; + uint32_t dfilpcfg0; + uint32_t dfilpcfg1; + uint32_t dfiupd0; + uint32_t dfiupd1; + uint32_t dfiupd2; + uint32_t dfimisc; + uint32_t dfitmg2; + uint32_t dfitmg3; + uint32_t dbictl; + uint32_t dfiphymstr; + uint32_t dbg0; + uint32_t dbg1; + uint32_t dbgcmd; + uint32_t swctl; + uint32_t swctlstatic; + uint32_t poisoncfg; + uint32_t pccfg; +}; + +struct stm32mp2_ddrctrl_timing { + uint32_t rfshtmg; + uint32_t rfshtmg1; + uint32_t dramtmg0; + uint32_t dramtmg1; + uint32_t dramtmg2; + uint32_t dramtmg3; + uint32_t dramtmg4; + uint32_t dramtmg5; + uint32_t dramtmg6; + uint32_t dramtmg7; + uint32_t dramtmg8; + uint32_t dramtmg9; + uint32_t dramtmg10; + uint32_t dramtmg11; + uint32_t dramtmg12; + uint32_t dramtmg13; + uint32_t dramtmg14; + uint32_t dramtmg15; + uint32_t odtcfg; + uint32_t odtmap; +}; + +struct stm32mp2_ddrctrl_map { + uint32_t addrmap0; + uint32_t addrmap1; + uint32_t addrmap2; + uint32_t addrmap3; + uint32_t addrmap4; + uint32_t addrmap5; + uint32_t addrmap6; + uint32_t addrmap7; + uint32_t addrmap8; + uint32_t addrmap9; + uint32_t addrmap10; + uint32_t addrmap11; +}; + +struct stm32mp2_ddrctrl_perf { + uint32_t sched; + uint32_t sched1; + uint32_t perfhpr1; + uint32_t perflpr1; + uint32_t perfwr1; + uint32_t sched3; + uint32_t sched4; + uint32_t pcfgr_0; + uint32_t pcfgw_0; + uint32_t pctrl_0; + uint32_t pcfgqos0_0; + uint32_t pcfgqos1_0; + uint32_t pcfgwqos0_0; + uint32_t pcfgwqos1_0; +#if STM32MP_DDR_DUAL_AXI_PORT + uint32_t pcfgr_1; + uint32_t pcfgw_1; + uint32_t pctrl_1; + uint32_t pcfgqos0_1; + uint32_t pcfgqos1_1; + uint32_t pcfgwqos0_1; + uint32_t pcfgwqos1_1; +#endif /* STM32MP_DDR_DUAL_AXI_PORT */ +}; + +struct stm32mp_ddr_config { + struct stm32mp_ddr_info info; + struct stm32mp2_ddrctrl_reg c_reg; + struct stm32mp2_ddrctrl_timing c_timing; + struct stm32mp2_ddrctrl_map c_map; + struct stm32mp2_ddrctrl_perf c_perf; + bool self_refresh; + uint32_t zdata; + struct user_input_basic uib; + struct user_input_advanced uia; + struct user_input_mode_register uim; + struct user_input_swizzle uis; +}; + +void stm32mp2_ddr_init(struct stm32mp_ddr_priv *priv, struct stm32mp_ddr_config *config); + +#endif /* STM32MP2_DDR_H */ diff --git a/include/drivers/st/stm32mp2_ddr_helpers.h b/include/drivers/st/stm32mp2_ddr_helpers.h index 069fb83db..9329fff25 100644 --- a/include/drivers/st/stm32mp2_ddr_helpers.h +++ b/include/drivers/st/stm32mp2_ddr_helpers.h @@ -7,6 +7,29 @@ #ifndef STM32MP2_DDR_HELPERS_H #define STM32MP2_DDR_HELPERS_H +#include +#include + +#include + +enum stm32mp2_ddr_sr_mode { + DDR_SR_MODE_INVALID = 0, + DDR_SSR_MODE, + DDR_HSR_MODE, + DDR_ASR_MODE, +}; + +void ddr_activate_controller(struct stm32mp_ddrctl *ctl, bool sr_entry); +void ddr_wait_lp3_mode(bool state); +int ddr_sr_exit_loop(void); +uint32_t ddr_get_io_calibration_val(void); +int ddr_sr_entry(bool standby); +int ddr_sr_exit(void); +enum stm32mp2_ddr_sr_mode ddr_read_sr_mode(void); +void ddr_set_sr_mode(enum stm32mp2_ddr_sr_mode mode); +void ddr_save_sr_mode(void); +void ddr_restore_sr_mode(void); void ddr_sub_system_clk_init(void); +void ddr_sub_system_clk_off(void); #endif /* STM32MP2_DDR_HELPERS_H */ diff --git a/include/drivers/st/stm32mp2_ddr_regs.h b/include/drivers/st/stm32mp2_ddr_regs.h new file mode 100644 index 000000000..9370f1ca5 --- /dev/null +++ b/include/drivers/st/stm32mp2_ddr_regs.h @@ -0,0 +1,38 @@ +/* + * Copyright (c) 2021-2024, STMicroelectronics - All Rights Reserved + * + * SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause + */ + +#ifndef STM32MP2_DDR_REGS_H +#define STM32MP2_DDR_REGS_H + +#include +#include + +/* DDR Physical Interface Control (DDRPHYC) registers*/ +struct stm32mp_ddrphy { + uint32_t dummy; +} __packed; + +/* DDRPHY registers offsets */ +#define DDRPHY_INITENG0_P0_SEQ0BDISABLEFLAG6 U(0x240004) +#define DDRPHY_INITENG0_P0_PHYINLPX U(0x2400A0) +#define DDRPHY_DRTUB0_UCCLKHCLKENABLES U(0x300200) +#define DDRPHY_APBONLY0_MICROCONTMUXSEL U(0x340000) + +/* DDRPHY registers fields */ +#define DDRPHY_INITENG0_P0_PHYINLPX_PHYINLP3 BIT(0) +#define DDRPHY_DRTUB0_UCCLKHCLKENABLES_UCCLKEN BIT(0) +#define DDRPHY_DRTUB0_UCCLKHCLKENABLES_HCLKEN BIT(1) +#define DDRPHY_APBONLY0_MICROCONTMUXSEL_MICROCONTMUXSEL BIT(0) + +/* DDRDBG registers offsets */ +#define DDRDBG_LP_DISABLE U(0x0) +#define DDRDBG_BYPASS_PCLKEN U(0x4) + +/* DDRDBG registers fields */ +#define DDRDBG_LP_DISABLE_LPI_XPI_DISABLE BIT(0) +#define DDRDBG_LP_DISABLE_LPI_DDRC_DISABLE BIT(8) + +#endif /* STM32MP2_DDR_REGS_H */ diff --git a/include/drivers/st/stm32mp2_ram.h b/include/drivers/st/stm32mp2_ram.h new file mode 100644 index 000000000..b6fa9288a --- /dev/null +++ b/include/drivers/st/stm32mp2_ram.h @@ -0,0 +1,13 @@ +/* + * Copyright (c) 2024, STMicroelectronics - All Rights Reserved + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef STM32MP2_RAM_H +#define STM32MP2_RAM_H + +bool stm32mp2_ddr_is_restored(void); +int stm32mp2_ddr_probe(void); + +#endif /* STM32MP2_RAM_H */ diff --git a/include/drivers/st/stm32mp_ddr.h b/include/drivers/st/stm32mp_ddr.h index a02ba7279..57b06686d 100644 --- a/include/drivers/st/stm32mp_ddr.h +++ b/include/drivers/st/stm32mp_ddr.h @@ -28,6 +28,9 @@ enum stm32mp_ddr_reg_type { struct stm32mp_ddr_reg_desc { uint16_t offset; /* Offset for base address */ uint8_t par_offset; /* Offset for parameter array */ +#if !STM32MP13 && !STM32MP15 + bool qd; /* quasi-dynamic register if true */ +#endif }; struct stm32mp_ddr_reg_info { diff --git a/include/drivers/st/stm32mp_ddrctrl_regs.h b/include/drivers/st/stm32mp_ddrctrl_regs.h index be8f86d03..f9f46aa42 100644 --- a/include/drivers/st/stm32mp_ddrctrl_regs.h +++ b/include/drivers/st/stm32mp_ddrctrl_regs.h @@ -51,7 +51,8 @@ struct stm32mp_ddrctl { uint32_t init7; /* 0xec SDRAM Initialization 7 */ uint32_t dimmctl; /* 0xf0 DIMM Control */ uint32_t rankctl; /* 0xf4 Rank Control */ - uint8_t reserved0f4[0x100 - 0xf8]; + uint32_t rankctl1; /* 0xf8 Rank Control 1 */ + uint8_t reserved0fc[0x100 - 0xfc]; uint32_t dramtmg0; /* 0x100 SDRAM Timing 0 */ uint32_t dramtmg1; /* 0x104 SDRAM Timing 1 */ uint32_t dramtmg2; /* 0x108 SDRAM Timing 2 */ @@ -112,7 +113,9 @@ struct stm32mp_ddrctl { uint32_t perflpr1; /* 0x264 Low Priority Read CAM 1 */ uint32_t reserved268; uint32_t perfwr1; /* 0x26c Write CAM 1 */ - uint8_t reserved27c[0x300 - 0x270]; + uint32_t sched3; /* 0x270 Scheduler Control 3 */ + uint32_t sched4; /* 0x274 Scheduler Control 4 */ + uint8_t reserved278[0x300 - 0x278]; uint32_t dbg0; /* 0x300 Debug 0 */ uint32_t dbg1; /* 0x304 Debug 1 */ uint32_t dbgcam; /* 0x308 CAM Debug */ @@ -121,7 +124,8 @@ struct stm32mp_ddrctl { uint8_t reserved314[0x320 - 0x314]; uint32_t swctl; /* 0x320 Software Programming Control Enable */ uint32_t swstat; /* 0x324 Software Programming Control Status */ - uint8_t reserved328[0x36c - 0x328]; + uint32_t swctlstatic; /* 0x328 Statics Write Enable */ + uint8_t reserved32c[0x36c - 0x32c]; uint32_t poisoncfg; /* 0x36c AXI Poison Configuration Register */ uint32_t poisonstat; /* 0x370 AXI Poison Status Register */ uint8_t reserved374[0x3f0 - 0x374]; @@ -153,7 +157,7 @@ struct stm32mp_ddrctl { uint32_t pcfgqos1_1; /* 0x548 Read QoS Configuration 1 */ uint32_t pcfgwqos0_1; /* 0x54c Write QoS Configuration 0 */ uint32_t pcfgwqos1_1; /* 0x550 Write QoS Configuration 1 */ -#endif +#endif /* STM32MP_DDR_DUAL_AXI_PORT */ uint8_t reserved554[0xff0 - 0x554]; uint32_t umctl2_ver_number; /* 0xff0 UMCTL2 Version Number */ @@ -170,6 +174,7 @@ struct stm32mp_ddrctl { #define DDRCTRL_RFSHCTL3 0x060 #define DDRCTRL_RFSHTMG 0x064 #define DDRCTRL_INIT0 0x0D0 +#define DDRCTRL_DFILPCFG0 0x198 #define DDRCTRL_DFIMISC 0x1B0 #define DDRCTRL_DBG1 0x304 #define DDRCTRL_DBGCAM 0x308 @@ -181,7 +186,7 @@ struct stm32mp_ddrctl { #define DDRCTRL_PCTRL_0 0x490 #if STM32MP_DDR_DUAL_AXI_PORT #define DDRCTRL_PCTRL_1 0x540 -#endif +#endif /* STM32MP_DDR_DUAL_AXI_PORT */ /* DDR Controller Register fields */ #define DDRCTRL_MSTR_DDR3 BIT(0) @@ -201,6 +206,8 @@ struct stm32mp_ddrctl { #define DDRCTRL_STAT_SELFREF_TYPE_MASK GENMASK(5, 4) #define DDRCTRL_STAT_SELFREF_TYPE_ASR (BIT(4) | BIT(5)) #define DDRCTRL_STAT_SELFREF_TYPE_SR BIT(5) +#define DDRCTRL_STAT_SELFREF_STATE_MASK GENMASK(9, 8) +#define DDRCTRL_STAT_SELFREF_STATE_SRPD BIT(9) #define DDRCTRL_MRCTRL0_MR_TYPE_WRITE U(0) /* Only one rank supported */ @@ -217,6 +224,7 @@ struct stm32mp_ddrctl { #define DDRCTRL_PWRCTL_POWERDOWN_EN BIT(1) #define DDRCTRL_PWRCTL_EN_DFI_DRAM_CLK_DISABLE BIT(3) #define DDRCTRL_PWRCTL_SELFREF_SW BIT(5) +#define DDRCTRL_PWRCTL_STAY_IN_SELFREF BIT(6) #define DDRCTRL_PWRTMG_SELFREF_TO_X32_MASK GENMASK(23, 16) #define DDRCTRL_PWRTMG_SELFREF_TO_X32_0 BIT(16) @@ -225,6 +233,9 @@ struct stm32mp_ddrctl { #define DDRCTRL_RFSHCTL3_REFRESH_UPDATE_LEVEL BIT(1) #define DDRCTRL_HWLPCTL_HW_LP_EN BIT(0) +#define DDRCTRL_HWLPCTL_HW_LP_EXIT_IDLE_EN BIT(1) +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_MASK GENMASK(27, 16) +#define DDRCTRL_HWLPCTL_HW_LP_IDLE_X32_SHIFT 16 #define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_MASK GENMASK(27, 16) #define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_SHIFT 16 @@ -232,11 +243,16 @@ struct stm32mp_ddrctl { #define DDRCTRL_INIT0_SKIP_DRAM_INIT_MASK GENMASK(31, 30) #define DDRCTRL_INIT0_SKIP_DRAM_INIT_NORMAL BIT(30) +#define DDRCTRL_DFILPCFG0_DFI_LP_EN_SR BIT(8) + #define DDRCTRL_DFIMISC_DFI_INIT_COMPLETE_EN BIT(0) #define DDRCTRL_DFIMISC_DFI_INIT_START BIT(5) +#define DDRCTRL_DFIMISC_DFI_FREQUENCY GENMASK(12, 8) #define DDRCTRL_DFISTAT_DFI_INIT_COMPLETE BIT(0) +#define DDRCTRL_DFISTAT_DFI_LP_ACK BIT(1) +#define DDRCTRL_DBG1_DIS_DQ BIT(0) #define DDRCTRL_DBG1_DIS_HIF BIT(1) #define DDRCTRL_DBGCAM_WR_DATA_PIPELINE_EMPTY BIT(29) diff --git a/plat/st/stm32mp2/plat_ddr.c b/plat/st/stm32mp2/plat_ddr.c index b6650625d..5302e45b6 100644 --- a/plat/st/stm32mp2/plat_ddr.c +++ b/plat/st/stm32mp2/plat_ddr.c @@ -9,11 +9,13 @@ #include #include + #include #include #include #include + #include #if STM32MP_DDR3_TYPE diff --git a/plat/st/stm32mp2/platform.mk b/plat/st/stm32mp2/platform.mk index 7002e5e86..c12e51204 100644 --- a/plat/st/stm32mp2/platform.mk +++ b/plat/st/stm32mp2/platform.mk @@ -42,6 +42,7 @@ DDR_TYPE := lpddr4 endif # DDR features +STM32MP_DDR_DUAL_AXI_PORT := 1 STM32MP_DDR_FIP_IO_STORAGE := 1 # Device tree @@ -71,6 +72,7 @@ endif # Enable flags for C files $(eval $(call assert_booleans,\ $(sort \ + STM32MP_DDR_DUAL_AXI_PORT \ STM32MP_DDR_FIP_IO_STORAGE \ STM32MP_DDR3_TYPE \ STM32MP_DDR4_TYPE \ @@ -92,6 +94,7 @@ $(eval $(call add_defines,\ PLAT_PARTITION_MAX_ENTRIES \ PLAT_TBBR_IMG_DEF \ STM32_TF_A_COPIES \ + STM32MP_DDR_DUAL_AXI_PORT \ STM32MP_DDR_FIP_IO_STORAGE \ STM32MP_DDR3_TYPE \ STM32MP_DDR4_TYPE \ @@ -105,6 +108,8 @@ TF_CFLAGS += -mbranch-protection=none # Include paths and source files PLAT_INCLUDES += -Iplat/st/stm32mp2/include/ +PLAT_INCLUDES += -Idrivers/st/ddr/phy/phyinit/include/ +PLAT_INCLUDES += -Idrivers/st/ddr/phy/firmware/include/ PLAT_BL_COMMON_SOURCES += lib/cpus/${ARCH}/cortex_a35.S PLAT_BL_COMMON_SOURCES += drivers/st/uart/${ARCH}/stm32_console.S @@ -137,7 +142,30 @@ ifeq (${STM32MP_USB_PROGRAMMER},1) BL2_SOURCES += plat/st/stm32mp2/stm32mp2_usb_dfu.c endif -BL2_SOURCES += drivers/st/ddr/stm32mp2_ddr_helpers.c +BL2_SOURCES += drivers/st/ddr/stm32mp2_ddr.c \ + drivers/st/ddr/stm32mp2_ddr_helpers.c \ + drivers/st/ddr/stm32mp2_ram.c + +BL2_SOURCES += drivers/st/ddr/phy/phyinit/src/ddrphy_phyinit_c_initphyconfig.c \ + drivers/st/ddr/phy/phyinit/src/ddrphy_phyinit_calcmb.c \ + drivers/st/ddr/phy/phyinit/src/ddrphy_phyinit_i_loadpieimage.c \ + drivers/st/ddr/phy/phyinit/src/ddrphy_phyinit_initstruct.c \ + drivers/st/ddr/phy/phyinit/src/ddrphy_phyinit_isdbytedisabled.c \ + drivers/st/ddr/phy/phyinit/src/ddrphy_phyinit_loadpieprodcode.c \ + drivers/st/ddr/phy/phyinit/src/ddrphy_phyinit_mapdrvstren.c \ + drivers/st/ddr/phy/phyinit/src/ddrphy_phyinit_progcsrskiptrain.c \ + drivers/st/ddr/phy/phyinit/src/ddrphy_phyinit_reginterface.c \ + drivers/st/ddr/phy/phyinit/src/ddrphy_phyinit_restore_sequence.c \ + drivers/st/ddr/phy/phyinit/src/ddrphy_phyinit_sequence.c \ + drivers/st/ddr/phy/phyinit/src/ddrphy_phyinit_softsetmb.c \ + drivers/st/ddr/phy/phyinit/usercustom/ddrphy_phyinit_usercustom_custompretrain.c \ + drivers/st/ddr/phy/phyinit/usercustom/ddrphy_phyinit_usercustom_saveretregs.c + +BL2_SOURCES += drivers/st/ddr/phy/phyinit/src/ddrphy_phyinit_d_loadimem.c \ + drivers/st/ddr/phy/phyinit/src/ddrphy_phyinit_f_loaddmem.c \ + drivers/st/ddr/phy/phyinit/src/ddrphy_phyinit_g_execfw.c \ + drivers/st/ddr/phy/phyinit/src/ddrphy_phyinit_writeoutmem.c \ + drivers/st/ddr/phy/phyinit/usercustom/ddrphy_phyinit_usercustom_g_waitfwdone.c # BL31 sources BL31_SOURCES += ${FDT_WRAPPERS_SOURCES} diff --git a/plat/st/stm32mp2/stm32mp2_def.h b/plat/st/stm32mp2/stm32mp2_def.h index 9838b55f6..73116db32 100644 --- a/plat/st/stm32mp2/stm32mp2_def.h +++ b/plat/st/stm32mp2/stm32mp2_def.h @@ -153,6 +153,8 @@ enum ddr_type { #if STM32MP_DDR_FIP_IO_STORAGE #define STM32MP_DDR_FW_BASE SRAM1_BASE +#define STM32MP_DDR_FW_DMEM_OFFSET U(0x400) +#define STM32MP_DDR_FW_IMEM_OFFSET U(0x800) #define STM32MP_DDR_FW_MAX_SIZE U(0x8800) #endif