Djam/arm-trusted-firmware
1
0
Fork 0
mirror of https://github.com/ARM-software/arm-trusted-firmware.git synced 2025-04-16 09:34:18 +00:00
Code Issues Projects Releases Packages Wiki Activity Actions

refactor(cpus): convert Cortex-A73 to use the errata framework

Browse source 
This involves replacing:
 * the reset_func with the standard cpu_reset_func_{start,end} to apply
   errata automatically
 * the <cpu>_errata_report with the errata_report_shim to report errata
   automatically
...and for each erratum:
 * the prologue with the workaround_<type>_start to do the checks and
   framework registration automatically
 * the epilogue with the workaround_<type>_end
 * the checker function with the check_erratum_<type> to make it more
   descriptive

It is important to note that the errata workaround and checking
sequences remain unchanged and preserve their git blame. Testing was
conducted by:

 * Manual comparison of disassembly of converted functions with non-
   converted functions.

	aarch64-none-elf-objdump -D <TF-A with
	conversion>/build/../release/bl31/bl31.elf
	vs
	aarch64-none-elf-objdump -D <TF-A clean
	repo>/build/fvp/release/bl31/bl31.elf

 * Build for release with all errata flags enabled and compare
   the disassembly of converted functions with non-converted
   functions.
	CROSS_COMPILE=aarch64-none-elf- make PLAT=fvp DEBUG=0 \
	HW_ASSISTED_COHERENCY=0 BL33=<tf-a-tests>/build/fvp/debug/tftf.bin \
	all fip ERRATA_A73_852427=1 \
	ERRATA_A73_855423=1 \
	WORKAROUND_CVE_2017_5715=1 \
	WORKAROUND_CVE_2018_3639=1 \
	WORKAROUND_CVE_2022_23960=1

 * Build for debug with all errata enabled and step through ArmDS
   at reset to ensure all functions are entered.

Change-Id: I63e5b2cc42e1e12daee0b727770cbc19ba729ff7
Signed-off-by: Sona Mathew <SonaRebecca.Mathew@arm.com>
This commit is contained in:
Sona Mathew 2023-06-19 18:52:45 -05:00
parent e2da5e0ed7
commit 7711223d00
1 changed files with 44 additions and 128 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

164
lib/cpus/aarch64/cortex_a73.S
View file

@ -40,63 +40,30 @@ func check_smccc_arch_workaround_3
ret
endfunc check_smccc_arch_workaround_3
/* ---------------------------------------------------
* Errata Workaround for Cortex A73 Errata #852427.
* This applies only to revision r0p0 of Cortex A73.
* Inputs:
* x0: variant[4:7] and revision[0:3] of current cpu.
* Shall clobber: x0-x17
* ---------------------------------------------------
*/
func errata_a73_852427_wa
/*
* Compare x0 against revision r0p0
*/
mov x17, x30
bl check_errata_852427
cbz x0, 1f
workaround_reset_start cortex_a73, ERRATUM(852427), ERRATA_A73_852427
mrs x1, CORTEX_A73_DIAGNOSTIC_REGISTER
orr x1, x1, #(1 << 12)
msr CORTEX_A73_DIAGNOSTIC_REGISTER, x1
isb
1:
ret x17
endfunc errata_a73_852427_wa
workaround_reset_end cortex_a73, ERRATUM(852427)
func check_errata_852427
mov x1, #0x00
b cpu_rev_var_ls
endfunc check_errata_852427
check_erratum_ls cortex_a73, ERRATUM(852427), CPU_REV(0, 0)
/* ---------------------------------------------------
* Errata Workaround for Cortex A73 Errata #855423.
* This applies only to revision <= r0p1 of Cortex A73.
* Inputs:
* x0: variant[4:7] and revision[0:3] of current cpu.
* Shall clobber: x0-x17
* ---------------------------------------------------
*/
func errata_a73_855423_wa
/*
* Compare x0 against revision r0p1
*/
mov x17, x30
bl check_errata_855423
cbz x0, 1f
workaround_reset_start cortex_a73, ERRATUM(855423), ERRATA_A73_855423
mrs x1, CORTEX_A73_IMP_DEF_REG2
orr x1, x1, #(1 << 7)
msr CORTEX_A73_IMP_DEF_REG2, x1
isb
1:
ret x17
endfunc errata_a73_855423_wa
workaround_reset_end cortex_a73, ERRATUM(855423)
func check_errata_855423
mov x1, #0x01
b cpu_rev_var_ls
endfunc check_errata_855423
check_erratum_ls cortex_a73, ERRATUM(855423), CPU_REV(0, 1)
func check_errata_cve_2017_5715
workaround_reset_start cortex_a73, CVE(2017, 5715), WORKAROUND_CVE_2017_5715
#if IMAGE_BL31
adr x0, wa_cve_2017_5715_bpiall_vbar
msr vbar_el3, x0
#endif /* IMAGE_BL31 */
workaround_reset_end cortex_a73, CVE(2017, 5715)
check_erratum_custom_start cortex_a73, CVE(2017, 5715)
cpu_check_csv2 x0, 1f
#if WORKAROUND_CVE_2017_5715
mov x0, #ERRATA_APPLIES
@ -107,18 +74,29 @@ func check_errata_cve_2017_5715
1:
mov x0, #ERRATA_NOT_APPLIES
ret
endfunc check_errata_cve_2017_5715
check_erratum_custom_end cortex_a73, CVE(2017, 5715)
func check_errata_cve_2018_3639
#if WORKAROUND_CVE_2018_3639
mov x0, #ERRATA_APPLIES
#else
mov x0, #ERRATA_MISSING
#endif
ret
endfunc check_errata_cve_2018_3639
workaround_reset_start cortex_a73, CVE(2018, 3639), WORKAROUND_CVE_2018_3639
mrs x0, CORTEX_A73_IMP_DEF_REG1
orr x0, x0, #CORTEX_A73_IMP_DEF_REG1_DISABLE_LOAD_PASS_STORE
msr CORTEX_A73_IMP_DEF_REG1, x0
workaround_reset_end cortex_a73, CVE(2018, 3639)
func check_errata_cve_2022_23960
check_erratum_chosen cortex_a73, CVE(2018, 3639), WORKAROUND_CVE_2018_3639
workaround_reset_start cortex_a73, CVE(2022, 23960), WORKAROUND_CVE_2022_23960
#if IMAGE_BL31
/* Skip installing vector table again for CVE_2022_23960 */
adr x0, wa_cve_2017_5715_bpiall_vbar
mrs x1, vbar_el3
cmp x0, x1
b.eq 1f
msr vbar_el3, x0
1:
#endif /* IMAGE_BL31 */
workaround_reset_end cortex_a73, CVE(2022, 23960)
check_erratum_custom_start cortex_a73, CVE(2022, 23960)
#if WORKAROUND_CVE_2017_5715 || WORKAROUND_CVE_2022_23960
cpu_check_csv2 x0, 1f
mov x0, #ERRATA_APPLIES
@ -133,51 +111,14 @@ func check_errata_cve_2022_23960
#endif /* WORKAROUND_CVE_2017_5715 || WORKAROUND_CVE_2022_23960 */
mov x0, #ERRATA_MISSING
ret
endfunc check_errata_cve_2022_23960
check_erratum_custom_end cortex_a73, CVE(2022, 23960)
/* -------------------------------------------------
* The CPU Ops reset function for Cortex-A73.
* -------------------------------------------------
*/
func cortex_a73_reset_func
mov x19, x30
bl cpu_get_rev_var
mov x18, x0
#if ERRATA_A73_852427
mov x0, x18
bl errata_a73_852427_wa
#endif
#if ERRATA_A73_855423
mov x0, x18
bl errata_a73_855423_wa
#endif
#if IMAGE_BL31 && (WORKAROUND_CVE_2017_5715 || WORKAROUND_CVE_2022_23960)
cpu_check_csv2 x0, 1f
adr x0, wa_cve_2017_5715_bpiall_vbar
msr vbar_el3, x0
isb
/* Skip installing vector table again for CVE_2022_23960 */
b 2f
1:
#if WORKAROUND_CVE_2022_23960
adr x0, wa_cve_2017_5715_bpiall_vbar
msr vbar_el3, x0
isb
#endif
2:
#endif /* IMAGE_BL31 && (WORKAROUND_CVE_2017_5715 || WORKAROUND_CVE_2022_23960) */
#if WORKAROUND_CVE_2018_3639
mrs x0, CORTEX_A73_IMP_DEF_REG1
orr x0, x0, #CORTEX_A73_IMP_DEF_REG1_DISABLE_LOAD_PASS_STORE
msr CORTEX_A73_IMP_DEF_REG1, x0
isb
#endif
cpu_reset_func_start cortex_a73
/* ---------------------------------------------
* Enable the SMP bit.
* Clobbers : x0
@ -186,9 +127,7 @@ func cortex_a73_reset_func
mrs x0, CORTEX_A73_CPUECTLR_EL1
orr x0, x0, #CORTEX_A73_CPUECTLR_SMP_BIT
msr CORTEX_A73_CPUECTLR_EL1, x0
isb
ret x19
endfunc cortex_a73_reset_func
cpu_reset_func_end cortex_a73
func cortex_a73_core_pwr_dwn
mov x18, x30
@ -252,30 +191,7 @@ func cortex_a73_cluster_pwr_dwn
endfunc cortex_a73_cluster_pwr_dwn
#if REPORT_ERRATA
/*
* Errata printing function for Cortex A75. Must follow AAPCS.
*/
func cortex_a73_errata_report
stp x8, x30, [sp, #-16]!
bl cpu_get_rev_var
mov x8, x0
/*
* Report all errata. The revision-variant information is passed to
* checking functions of each errata.
*/
report_errata ERRATA_A73_852427, cortex_a73, 852427
report_errata ERRATA_A73_855423, cortex_a73, 855423
report_errata WORKAROUND_CVE_2017_5715, cortex_a73, cve_2017_5715
report_errata WORKAROUND_CVE_2018_3639, cortex_a73, cve_2018_3639
report_errata WORKAROUND_CVE_2022_23960, cortex_a73, cve_2022_23960
ldp x8, x30, [sp], #16
ret
endfunc cortex_a73_errata_report
#endif
errata_report_shim cortex_a73
/* ---------------------------------------------
* This function provides cortex_a73 specific
@ -299,7 +215,7 @@ endfunc cortex_a73_cpu_reg_dump
declare_cpu_ops_wa cortex_a73, CORTEX_A73_MIDR, \
cortex_a73_reset_func, \
check_errata_cve_2017_5715, \
check_erratum_cortex_a73_5715, \
CPU_NO_EXTRA2_FUNC, \
check_smccc_arch_workaround_3, \
cortex_a73_core_pwr_dwn, \