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fix(cpus): workaround for Cortex-A78C erratum 2683027

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Cortex-A78C erratum 2683027 is a cat B erratum that applies to
revisions r0p1 - r0p2 and is still open. The workaround is to
execute a specific code sequence in EL3 during reset.

SDEN can be found here:
https://developer.arm.com/documentation/SDEN-2004089/latest

Change-Id: I2bf9e675f48b62b4cd203100f7df40f4846aafa8
Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>
This commit is contained in:
Bipin Ravi 2023-12-20 15:40:44 -06:00
parent a65c5ba351
commit 68cac6a0f2
4 changed files with 28 additions and 6 deletions
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4
docs/design/cpu-specific-build-macros.rst
View file

@ -384,6 +384,10 @@ For Cortex-A78C, the following errata build flags are defined :
Cortex-A78C CPU. This needs to be enabled for revisions r0p1 and r0p2. This Cortex-A78C CPU. This needs to be enabled for revisions r0p1 and r0p2. This
erratum is still open. erratum is still open.
- ``ERRATA_A78C_2683027`` : This applies errata 2683027 workaround to
Cortex-A78C CPU. This needs to be enabled for revisions r0p1 and r0p2. This
erratum is still open.
- ``ERRATA_A78C_2712575`` : This applies erratum 2712575 workaround to - ``ERRATA_A78C_2712575`` : This applies erratum 2712575 workaround to
Cortex-A78C CPU, this erratum affects system configurations that do not use Cortex-A78C CPU, this erratum affects system configurations that do not use
an ARM interconnect IP. This needs to be enabled for revisions r0p1 and r0p2 an ARM interconnect IP. This needs to be enabled for revisions r0p1 and r0p2

15
lib/cpus/aarch64/cortex_a78c.S
View file

@ -1,5 +1,5 @@
/* /*
* Copyright (c) 2021-2023, Arm Limited. All rights reserved. * Copyright (c) 2021-2024, Arm Limited. All rights reserved.
* *
* SPDX-License-Identifier: BSD-3-Clause * SPDX-License-Identifier: BSD-3-Clause
*/ */
@ -72,6 +72,19 @@ workaround_reset_end cortex_a78c, ERRATUM(2395411)
check_erratum_range cortex_a78c, ERRATUM(2395411), CPU_REV(0, 1), CPU_REV(0, 2) check_erratum_range cortex_a78c, ERRATUM(2395411), CPU_REV(0, 1), CPU_REV(0, 2)
workaround_reset_start cortex_a78c, ERRATUM(2683027), ERRATA_A78C_2683027
ldr x0, =0x3
msr CORTEX_A78C_IMP_CPUPSELR_EL3, x0
ldr x0, =0xEE010F10
msr CORTEX_A78C_IMP_CPUPOR_EL3, x0
ldr x0, =0xFF1F0FFE
msr CORTEX_A78C_IMP_CPUPMR_EL3, x0
ldr x0, =0x100000004003FF
msr CORTEX_A78C_IMP_CPUPCR_EL3, x0
workaround_reset_end cortex_a78c, ERRATUM(2683027)
check_erratum_range cortex_a78c, ERRATUM(2683027), CPU_REV(0, 1), CPU_REV(0, 2)
workaround_reset_start cortex_a78c, ERRATUM(2743232), ERRATA_A78C_2743232 workaround_reset_start cortex_a78c, ERRATUM(2743232), ERRATA_A78C_2743232
/* Set CPUACTLR5_EL1[56:55] to 2'b01 */ /* Set CPUACTLR5_EL1[56:55] to 2'b01 */
sysreg_bit_set CORTEX_A78C_ACTLR5_EL1, BIT(55) sysreg_bit_set CORTEX_A78C_ACTLR5_EL1, BIT(55)

4
lib/cpus/cpu-ops.mk
View file

@ -388,6 +388,10 @@ CPU_FLAG_LIST += ERRATA_A78C_2376749
# to revisions r0p1 and r0p2 of the A78C cpu. It is still open. # to revisions r0p1 and r0p2 of the A78C cpu. It is still open.
CPU_FLAG_LIST += ERRATA_A78C_2395411 CPU_FLAG_LIST += ERRATA_A78C_2395411
# Flag to apply erratum 2683027 workaround during reset. This erratum applies
# to revisions r0p1 and r0p2 of the A78C cpu. It is still open.
CPU_FLAG_LIST += ERRATA_A78C_2683027
# Flag to apply erratum 2712575 workaround for non-arm interconnect ip. This # Flag to apply erratum 2712575 workaround for non-arm interconnect ip. This
# erratum applies to revisions r0p1 and r0p2 of the A78C cpu. # erratum applies to revisions r0p1 and r0p2 of the A78C cpu.
# It is still open. # It is still open.

11
services/std_svc/errata_abi/errata_abi_main.c
View file

@ -237,12 +237,13 @@ struct em_cpu_list cpu_list[] = {
[3] = {2242638, 0x01, 0x02, ERRATA_A78C_2242638}, [3] = {2242638, 0x01, 0x02, ERRATA_A78C_2242638},
[4] = {2376749, 0x01, 0x02, ERRATA_A78C_2376749}, [4] = {2376749, 0x01, 0x02, ERRATA_A78C_2376749},
[5] = {2395411, 0x01, 0x02, ERRATA_A78C_2395411}, [5] = {2395411, 0x01, 0x02, ERRATA_A78C_2395411},
[6] = {2712575, 0x01, 0x02, ERRATA_A78C_2712575, \ [6] = {2683027, 0x01, 0x02, ERRATA_A78C_2683027},
[7] = {2712575, 0x01, 0x02, ERRATA_A78C_2712575, \
ERRATA_NON_ARM_INTERCONNECT}, ERRATA_NON_ARM_INTERCONNECT},
[7] = {2743232, 0x01, 0x02, ERRATA_A78C_2743232}, [8] = {2743232, 0x01, 0x02, ERRATA_A78C_2743232},
[8] = {2772121, 0x00, 0x02, ERRATA_A78C_2772121}, [9] = {2772121, 0x00, 0x02, ERRATA_A78C_2772121},
[9] = {2779484, 0x01, 0x02, ERRATA_A78C_2779484}, [10] = {2779484, 0x01, 0x02, ERRATA_A78C_2779484},
[10 ... ERRATA_LIST_END] = UNDEF_ERRATA, [11 ... ERRATA_LIST_END] = UNDEF_ERRATA,
} }
}, },
#endif /* CORTEX_A78C_H_INC */ #endif /* CORTEX_A78C_H_INC */