From 68cac6a0f273dbe4f44563b467c996fafef07016 Mon Sep 17 00:00:00 2001
From: Bipin Ravi <bipin.ravi@arm.com>
Date: Wed, 20 Dec 2023 15:40:44 -0600
Subject: [PATCH] fix(cpus): workaround for Cortex-A78C erratum 2683027

Cortex-A78C erratum 2683027 is a cat B erratum that applies to
revisions r0p1 - r0p2 and is still open. The workaround is to
execute a specific code sequence in EL3 during reset.

SDEN can be found here:
https://developer.arm.com/documentation/SDEN-2004089/latest

Change-Id: I2bf9e675f48b62b4cd203100f7df40f4846aafa8
Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>
---
 docs/design/cpu-specific-build-macros.rst     |  4 ++++
 lib/cpus/aarch64/cortex_a78c.S                | 15 ++++++++++++++-
 lib/cpus/cpu-ops.mk                           |  4 ++++
 services/std_svc/errata_abi/errata_abi_main.c | 11 ++++++-----
 4 files changed, 28 insertions(+), 6 deletions(-)

diff --git a/docs/design/cpu-specific-build-macros.rst b/docs/design/cpu-specific-build-macros.rst
index 287d32b6c..3485dc910 100644
--- a/docs/design/cpu-specific-build-macros.rst
+++ b/docs/design/cpu-specific-build-macros.rst
@@ -384,6 +384,10 @@ For Cortex-A78C, the following errata build flags are defined :
   Cortex-A78C CPU. This needs to be enabled for revisions r0p1 and r0p2. This
   erratum is still open.
 
+- ``ERRATA_A78C_2683027`` : This applies errata 2683027 workaround to
+  Cortex-A78C CPU. This needs to be enabled for revisions r0p1 and r0p2. This
+  erratum is still open.
+
 - ``ERRATA_A78C_2712575`` : This applies erratum 2712575 workaround to
   Cortex-A78C CPU, this erratum affects system configurations that do not use
   an ARM interconnect IP. This needs to be enabled for revisions r0p1 and r0p2
diff --git a/lib/cpus/aarch64/cortex_a78c.S b/lib/cpus/aarch64/cortex_a78c.S
index 2e6e8b6a9..0dc34f7ac 100644
--- a/lib/cpus/aarch64/cortex_a78c.S
+++ b/lib/cpus/aarch64/cortex_a78c.S
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2021-2023, Arm Limited. All rights reserved.
+ * Copyright (c) 2021-2024, Arm Limited. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -72,6 +72,19 @@ workaround_reset_end cortex_a78c, ERRATUM(2395411)
 
 check_erratum_range cortex_a78c, ERRATUM(2395411), CPU_REV(0, 1), CPU_REV(0, 2)
 
+workaround_reset_start cortex_a78c, ERRATUM(2683027), ERRATA_A78C_2683027
+	ldr	x0, =0x3
+	msr	CORTEX_A78C_IMP_CPUPSELR_EL3, x0
+	ldr	x0, =0xEE010F10
+	msr	CORTEX_A78C_IMP_CPUPOR_EL3, x0
+	ldr	x0, =0xFF1F0FFE
+	msr	CORTEX_A78C_IMP_CPUPMR_EL3, x0
+	ldr	x0, =0x100000004003FF
+	msr	CORTEX_A78C_IMP_CPUPCR_EL3, x0
+workaround_reset_end cortex_a78c, ERRATUM(2683027)
+
+check_erratum_range cortex_a78c, ERRATUM(2683027), CPU_REV(0, 1), CPU_REV(0, 2)
+
 workaround_reset_start cortex_a78c, ERRATUM(2743232), ERRATA_A78C_2743232
 	/* Set CPUACTLR5_EL1[56:55] to 2'b01 */
 	sysreg_bit_set CORTEX_A78C_ACTLR5_EL1, BIT(55)
diff --git a/lib/cpus/cpu-ops.mk b/lib/cpus/cpu-ops.mk
index f83fe1931..a99c08295 100644
--- a/lib/cpus/cpu-ops.mk
+++ b/lib/cpus/cpu-ops.mk
@@ -388,6 +388,10 @@ CPU_FLAG_LIST += ERRATA_A78C_2376749
 # to revisions r0p1 and r0p2 of the A78C cpu. It is still open.
 CPU_FLAG_LIST += ERRATA_A78C_2395411
 
+# Flag to apply erratum 2683027 workaround during reset. This erratum applies
+# to revisions r0p1 and r0p2 of the A78C cpu. It is still open.
+CPU_FLAG_LIST += ERRATA_A78C_2683027
+
 # Flag to apply erratum 2712575 workaround for non-arm interconnect ip. This
 # erratum applies to revisions r0p1 and r0p2 of the A78C cpu.
 # It is still open.
diff --git a/services/std_svc/errata_abi/errata_abi_main.c b/services/std_svc/errata_abi/errata_abi_main.c
index 18c0c88b1..f1342ad13 100644
--- a/services/std_svc/errata_abi/errata_abi_main.c
+++ b/services/std_svc/errata_abi/errata_abi_main.c
@@ -237,12 +237,13 @@ struct em_cpu_list cpu_list[] = {
 		[3] = {2242638, 0x01, 0x02, ERRATA_A78C_2242638},
 		[4] = {2376749, 0x01, 0x02, ERRATA_A78C_2376749},
 		[5] = {2395411, 0x01, 0x02, ERRATA_A78C_2395411},
-		[6] = {2712575, 0x01, 0x02, ERRATA_A78C_2712575, \
+		[6] = {2683027, 0x01, 0x02, ERRATA_A78C_2683027},
+		[7] = {2712575, 0x01, 0x02, ERRATA_A78C_2712575, \
 			ERRATA_NON_ARM_INTERCONNECT},
-		[7] = {2743232, 0x01, 0x02, ERRATA_A78C_2743232},
-		[8] = {2772121, 0x00, 0x02, ERRATA_A78C_2772121},
-		[9] = {2779484, 0x01, 0x02, ERRATA_A78C_2779484},
-		[10 ... ERRATA_LIST_END] = UNDEF_ERRATA,
+		[8] = {2743232, 0x01, 0x02, ERRATA_A78C_2743232},
+		[9] = {2772121, 0x00, 0x02, ERRATA_A78C_2772121},
+		[10] = {2779484, 0x01, 0x02, ERRATA_A78C_2779484},
+		[11 ... ERRATA_LIST_END] = UNDEF_ERRATA,
 	}
 },
 #endif /* CORTEX_A78C_H_INC */