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feat(rdv3): add carveout for BL32 image
Add and map the carveout for loading Hafnium as BL32 image. Also define PLAT_ARM_SP_MAX_SIZE as 3 MB for secure partitions. Signed-off-by: Rohit Mathew <rohit.mathew@arm.com> Signed-off-by: Nishant Sharma <nishant.sharma@arm.com> Signed-off-by: Rakshit Goyal <rakshit.goyal@arm.com> Change-Id: I2845eb6807a127c9f6b92de2dabc9a58d25bd4d4
This commit is contained in:
Rohit Mathew
Rakshit Goyal
parent
4593b93239
commit
6823f5f520
5 changed files with 60 additions and 6 deletions
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@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2024, Arm Limited and Contributors. All rights reserved.
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* Copyright (c) 2024-2025, Arm Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*
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@ -111,6 +111,14 @@
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ARM_REALM_SIZE, \
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MT_MEMORY | MT_RW | MT_REALM)
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#if SPD_spmd && SPMD_SPM_AT_SEL2
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#define NRD_CSS_SPM_CORE_REGION_MMAP \
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MAP_REGION_FLAT( \
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BL32_BASE, \
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BL32_LIMIT - BL32_BASE, \
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MT_MEMORY | MT_RW | MT_SECURE)
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#endif
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#if RESET_TO_BL31
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/*******************************************************************************
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* BL31 specific defines.
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@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2024, Arm Limited and Contributors. All rights reserved.
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* Copyright (c) 2024-2025, Arm Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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@ -177,6 +177,9 @@
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* ---------------------------------------------------------------------
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* 0x80000000 |2GB - |L1 GPT |NS |NS DRAM |
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* 0xF3FFFFFF |192MB | | | |
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* --------------------------------------------------------------------|
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* 0xF4000000 |9692KB |L1 GPT |SECURE |BL32 |
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* 0xFB200000 | | | | |
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* ---------------------------------------------------------------------
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* 0x80000000 |26MB |L1 GPT |REALM |RMM |
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* 0x37FFFFFF | | | |TF-A SHARED |
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@ -514,6 +517,14 @@
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ARM_DRAM1_SIZE, \
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GPT_GPI_NS)
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#if SPD_spmd && SPMD_SPM_AT_SEL2
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#define NRD_PAS_BL32 \
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GPT_MAP_REGION_GRANULE( \
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PLAT_ARM_SPMC_BASE, \
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PLAT_ARM_SPMC_SIZE, \
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GPT_GPI_SECURE)
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#endif
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#define NRD_PAS_RMM \
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GPT_MAP_REGION_GRANULE( \
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ARM_REALM_BASE, \
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@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2024, Arm Limited and Contributors. All rights reserved.
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* Copyright (c) 2024-2025, Arm Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*
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@ -608,9 +608,13 @@
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* - L1 GPT DRAM: Reserved for L1 GPT if RME is enabled
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* - TF-A <-> RMM SHARED: Area shared for communication between TF-A and RMM
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* - REALM DRAM: Reserved for Realm world if RME is enabled
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* - BL32: Carveout for BL32 image if BL32 is present
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*
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* DRAM layout
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* +------------------+
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* | |
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* | BL32 |
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* +------------------+
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* | REALM (RMM) |
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* | (32MB - 4KB) |
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* +------------------+
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@ -695,6 +699,14 @@
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#define RMM_SHARED_BASE (ARM_EL3_RMM_SHARED_BASE)
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#define RMM_SHARED_SIZE (ARM_EL3_RMM_SHARED_SIZE)
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/*******************************************************************************
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* S-EL2 SPMC region defines.
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******************************************************************************/
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/* BL32 (1500KB) + PLAT_ARM_SP_MAX_SIZE (3MB) + SP HEAP (5MB) */
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/* 9692KB */
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#define PLAT_ARM_SPMC_SIZE (UL(1500 * 1024) + UL(0x300000) + UL(0x500000))
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#define PLAT_ARM_SPMC_BASE (RMM_BASE - PLAT_ARM_SPMC_SIZE)
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/*******************************************************************************
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* NRD_CSS_CARVEOUT_RESERVED region specific defines.
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******************************************************************************/
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@ -705,11 +717,22 @@
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#define NRD_CSS_CARVEOUT_RESERVED_SIZE (NRD_CSS_DRAM1_CARVEOUT_SIZE - \
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(ARM_EL3_RMM_SHARED_SIZE + \
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ARM_REALM_SIZE + \
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ARM_L1_GPT_SIZE))
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ARM_L1_GPT_SIZE + \
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PLAT_ARM_SPMC_SIZE))
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#define NRD_CSS_CARVEOUT_RESERVED_END (NRD_CSS_CARVEOUT_RESERVED_BASE +\
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NRD_CSS_CARVEOUT_RESERVED_SIZE - 1U)
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/*******************************************************************************
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* BL32 specific defines for EL3 runtime in AArch64 mode
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******************************************************************************/
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#if SPD_spmd && SPMD_SPM_AT_SEL2
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# define BL32_BASE PLAT_ARM_SPMC_BASE
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# define BL32_LIMIT (PLAT_ARM_SPMC_BASE + \
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PLAT_ARM_SPMC_SIZE)
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# endif
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/*******************************************************************************
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* NS RAM specific defines specific defines.
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******************************************************************************/
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@ -721,6 +744,12 @@
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#define ARM_NS_DRAM1_END (ARM_NS_DRAM1_BASE + \
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ARM_NS_DRAM1_SIZE - 1U)
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/*******************************************************************************
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* Secure Partition specific defines.
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******************************************************************************/
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#define PLAT_ARM_SP_MAX_SIZE U(0x300000) /* 3MB */
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/*******************************************************************************
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* MMU mapping
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******************************************************************************/
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@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2024, Arm Limited and Contributors. All rights reserved.
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* Copyright (c) 2024-2025, Arm Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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@ -39,6 +39,9 @@ const mmap_region_t plat_arm_mmap[] = {
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NRD_ROS_PLATFORM_PERIPH_MMAP,
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NRD_ROS_SYSTEM_PERIPH_MMAP,
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NRD_CSS_NS_DRAM1_MMAP,
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#if SPD_spmd && SPMD_SPM_AT_SEL2
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NRD_CSS_SPM_CORE_REGION_MMAP,
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#endif
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#if TRUSTED_BOARD_BOOT && !RESET_TO_BL2
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NRD_CSS_BL1_RW_MMAP,
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#endif
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@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2024, Arm Limited and Contributors. All rights reserved.
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* Copyright (c) 2024-2025, Arm Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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@ -59,6 +59,9 @@ static pas_region_t pas_regions[] = {
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NRD_PAS_SCP_MCP_RSE_SHARED_SRAM,
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NRD_PAS_GIC,
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NRD_PAS_NS_DRAM,
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#if SPD_spmd && SPMD_SPM_AT_SEL2
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NRD_PAS_BL32,
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#endif
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NRD_PAS_RMM,
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NRD_PAS_L1GPT,
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NRD_PAS_CMN,
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