feat(rdv3): add carveout for BL32 image

Add and map the carveout for loading Hafnium as BL32 image. Also define
PLAT_ARM_SP_MAX_SIZE as 3 MB for secure partitions.

Signed-off-by: Rohit Mathew <rohit.mathew@arm.com>
Signed-off-by: Nishant Sharma <nishant.sharma@arm.com>
Signed-off-by: Rakshit Goyal <rakshit.goyal@arm.com>
Change-Id: I2845eb6807a127c9f6b92de2dabc9a58d25bd4d4

plat/arm/board/neoverse_rd/common/include/nrd3/nrd_css_fw_def3.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2024, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2024-2025, Arm Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  *
@@ -111,6 +111,14 @@
 			ARM_REALM_SIZE,					\
 			MT_MEMORY | MT_RW | MT_REALM)
 
+#if SPD_spmd && SPMD_SPM_AT_SEL2
+#define NRD_CSS_SPM_CORE_REGION_MMAP						\
+		MAP_REGION_FLAT(					\
+			BL32_BASE,					\
+			BL32_LIMIT - BL32_BASE,				\
+			MT_MEMORY | MT_RW | MT_SECURE)
+#endif
+
 #if RESET_TO_BL31
 /*******************************************************************************
  * BL31 specific defines.

plat/arm/board/neoverse_rd/common/include/nrd3/nrd_pas_def3.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2024, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2024-2025, Arm Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -177,6 +177,9 @@
  * ---------------------------------------------------------------------
  * 0x80000000       |2GB -   |L1 GPT |NS     |NS DRAM                  |
  * 0xF3FFFFFF       |192MB   |       |       |                         |
+ * --------------------------------------------------------------------|
+ * 0xF4000000       |9692KB  |L1 GPT |SECURE |BL32                     |
+ * 0xFB200000       |        |       |       |                         |
  * ---------------------------------------------------------------------
  * 0x80000000       |26MB    |L1 GPT |REALM  |RMM                      |
  * 0x37FFFFFF       |        |       |       |TF-A SHARED              |
@@ -514,6 +517,14 @@
 			ARM_DRAM1_SIZE,					\
 			GPT_GPI_NS)
 
+#if SPD_spmd && SPMD_SPM_AT_SEL2
+#define NRD_PAS_BL32							\
+		GPT_MAP_REGION_GRANULE(					\
+			PLAT_ARM_SPMC_BASE,				\
+			PLAT_ARM_SPMC_SIZE,				\
+			GPT_GPI_SECURE)
+#endif
+
 #define NRD_PAS_RMM							\
 		GPT_MAP_REGION_GRANULE(					\
 			ARM_REALM_BASE,					\

plat/arm/board/neoverse_rd/common/include/nrd3/nrd_plat_arm_def3.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2024, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2024-2025, Arm Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  *
@@ -608,9 +608,13 @@
  *   - L1 GPT DRAM: Reserved for L1 GPT if RME is enabled
  *   - TF-A <-> RMM SHARED: Area shared for communication between TF-A and RMM
  *   - REALM DRAM: Reserved for Realm world if RME is enabled
+ *   - BL32: Carveout for BL32 image if BL32 is present
  *
  *                    DRAM layout
  *               +------------------+
+ *               |                  |
+ *               |        BL32      |
+ *               +------------------+
  *               |   REALM (RMM)    |
  *               |   (32MB - 4KB)   |
  *               +------------------+
@@ -695,6 +699,14 @@
 #define RMM_SHARED_BASE			(ARM_EL3_RMM_SHARED_BASE)
 #define RMM_SHARED_SIZE			(ARM_EL3_RMM_SHARED_SIZE)
 
+/*******************************************************************************
+ * S-EL2 SPMC region defines.
+ ******************************************************************************/
+/* BL32 (1500KB) +  PLAT_ARM_SP_MAX_SIZE (3MB) + SP HEAP (5MB) */
+/* 9692KB */
+#define PLAT_ARM_SPMC_SIZE	(UL(1500 * 1024) + UL(0x300000) + UL(0x500000))
+#define PLAT_ARM_SPMC_BASE	(RMM_BASE - PLAT_ARM_SPMC_SIZE)
+
 /*******************************************************************************
  * NRD_CSS_CARVEOUT_RESERVED region specific defines.
  ******************************************************************************/
@@ -705,11 +717,22 @@
 #define NRD_CSS_CARVEOUT_RESERVED_SIZE	(NRD_CSS_DRAM1_CARVEOUT_SIZE -	\
 					(ARM_EL3_RMM_SHARED_SIZE +	\
 					 ARM_REALM_SIZE +		\
-					 ARM_L1_GPT_SIZE))
+					 ARM_L1_GPT_SIZE +		\
+					 PLAT_ARM_SPMC_SIZE))
 
 #define NRD_CSS_CARVEOUT_RESERVED_END	(NRD_CSS_CARVEOUT_RESERVED_BASE +\
 					 NRD_CSS_CARVEOUT_RESERVED_SIZE - 1U)
 
+/*******************************************************************************
+ * BL32 specific defines for EL3 runtime in AArch64 mode
+ ******************************************************************************/
+
+#if SPD_spmd && SPMD_SPM_AT_SEL2
+#  define BL32_BASE			PLAT_ARM_SPMC_BASE
+#  define BL32_LIMIT			(PLAT_ARM_SPMC_BASE +		\
+					 PLAT_ARM_SPMC_SIZE)
+# endif
+
 /*******************************************************************************
  * NS RAM specific defines specific defines.
  ******************************************************************************/
@@ -721,6 +744,12 @@
 #define ARM_NS_DRAM1_END		(ARM_NS_DRAM1_BASE +		\
 					 ARM_NS_DRAM1_SIZE - 1U)
 
+/*******************************************************************************
+ * Secure Partition specific defines.
+ ******************************************************************************/
+
+#define PLAT_ARM_SP_MAX_SIZE		U(0x300000) /* 3MB */
+
 /*******************************************************************************
  * MMU mapping
  ******************************************************************************/

plat/arm/board/neoverse_rd/common/nrd_plat3.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2024, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2024-2025, Arm Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -39,6 +39,9 @@ const mmap_region_t plat_arm_mmap[] = {
 	NRD_ROS_PLATFORM_PERIPH_MMAP,
 	NRD_ROS_SYSTEM_PERIPH_MMAP,
 	NRD_CSS_NS_DRAM1_MMAP,
+#if SPD_spmd && SPMD_SPM_AT_SEL2
+	NRD_CSS_SPM_CORE_REGION_MMAP,
+#endif
 #if TRUSTED_BOARD_BOOT && !RESET_TO_BL2
 	NRD_CSS_BL1_RW_MMAP,
 #endif

plat/arm/board/neoverse_rd/platform/rdv3/rdv3_bl2_setup.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2024, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2024-2025, Arm Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -59,6 +59,9 @@ static pas_region_t pas_regions[] = {
 	NRD_PAS_SCP_MCP_RSE_SHARED_SRAM,
 	NRD_PAS_GIC,
 	NRD_PAS_NS_DRAM,
+#if SPD_spmd && SPMD_SPM_AT_SEL2
+	NRD_PAS_BL32,
+#endif
 	NRD_PAS_RMM,
 	NRD_PAS_L1GPT,
 	NRD_PAS_CMN,