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Merge pull request #788 from jeenu-arm/cpuops-framework
Add provision to extend CPU operations at more levels
This commit is contained in:
danh-arm
GitHub
commit
67748e4827
16 changed files with 257 additions and 144 deletions
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@ -1127,7 +1127,8 @@ can be found in the [cpu-specific-build-macros.md][CPUBM] file.
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The CPU specific operations framework depends on the `cpu_ops` structure which
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needs to be exported for each type of CPU in the platform. It is defined in
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`include/lib/cpus/aarch64/cpu_macros.S` and has the following fields : `midr`,
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`reset_func()`, `core_pwr_dwn()`, `cluster_pwr_dwn()` and `cpu_reg_dump()`.
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`reset_func()`, `cpu_pwr_down_ops` (array of power down functions) and
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`cpu_reg_dump()`.
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The CPU specific files in `lib/cpus` export a `cpu_ops` data structure with
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suitable handlers for that CPU. For example, `lib/cpus/aarch64/cortex_a53.S`
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@ -1161,15 +1162,15 @@ During the BL31 initialization sequence, the pointer to the matching `cpu_ops`
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entry is stored in per-CPU data by `init_cpu_ops()` so that it can be quickly
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retrieved during power down sequences.
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The PSCI service, upon receiving a power down request, determines the highest
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power level at which to execute power down sequence for a particular CPU and
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invokes the corresponding 'prepare' power down handler in the CPU specific
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operations framework. For example, when a CPU executes a power down for power
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level 0, the `prepare_core_pwr_dwn()` retrieves the `cpu_ops` pointer from the
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per-CPU data and the corresponding `core_pwr_dwn()` is invoked. Similarly when
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a CPU executes power down at power level 1, the `prepare_cluster_pwr_dwn()`
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retrieves the `cpu_ops` pointer and the corresponding `cluster_pwr_dwn()` is
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invoked.
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Various CPU drivers register handlers to perform power down at certain power
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levels for that specific CPU. The PSCI service, upon receiving a power down
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request, determines the highest power level at which to execute power down
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sequence for a particular CPU. It uses the `prepare_cpu_pwr_dwn()` function to
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pick the right power down handler for the requested level. The function
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retrieves `cpu_ops` pointer member of per-CPU data, and from that, further
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retrieves `cpu_pwr_down_ops` array, and indexes into the required level. If the
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requested power level is higher than what a CPU driver supports, the handler
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registered for highest level is invoked.
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At runtime the platform hooks for power down are invoked by the PSCI service to
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perform platform specific operations during a power down sequence, for example
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@ -35,6 +35,15 @@
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#define CPU_IMPL_PN_MASK (MIDR_IMPL_MASK << MIDR_IMPL_SHIFT) | \
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(MIDR_PN_MASK << MIDR_PN_SHIFT)
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/* The number of CPU operations allowed */
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#define CPU_MAX_PWR_DWN_OPS 2
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/* Special constant to specify that CPU has no reset function */
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#define CPU_NO_RESET_FUNC 0
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/* Word size for 32-bit CPUs */
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#define CPU_WORD_SIZE 4
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/*
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* Define the offsets to the fields in cpu_ops structure.
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*/
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@ -47,33 +56,86 @@ CPU_RESET_FUNC: /* cpu_ops reset_func */
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.space 4
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#endif
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#if IMAGE_BL32 /* The power down core and cluster is needed only in BL32 */
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CPU_PWR_DWN_CORE: /* cpu_ops core_pwr_dwn */
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.space 4
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CPU_PWR_DWN_CLUSTER: /* cpu_ops cluster_pwr_dwn */
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.space 4
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CPU_PWR_DWN_OPS: /* cpu_ops power down functions */
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.space (4 * CPU_MAX_PWR_DWN_OPS)
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#endif
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CPU_OPS_SIZE = .
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/*
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* Convenience macro to declare cpu_ops structure.
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* Make sure the structure fields are as per the offsets
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* defined above.
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* Write given expressions as words
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*
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* _count:
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* Write at least _count words. If the given number of expressions
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* is less than _count, repeat the last expression to fill _count
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* words in total
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* _rest:
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* Optional list of expressions. _this is for parameter extraction
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* only, and has no significance to the caller
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*
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* Invoked as:
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* fill_constants 2, foo, bar, blah, ...
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*/
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.macro declare_cpu_ops _name:req, _midr:req, _noresetfunc = 0
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.macro fill_constants _count:req, _this, _rest:vararg
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.ifgt \_count
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/* Write the current expression */
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.ifb \_this
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.error "Nothing to fill"
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.endif
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.word \_this
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/* Invoke recursively for remaining expressions */
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.ifnb \_rest
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fill_constants \_count-1, \_rest
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.else
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fill_constants \_count-1, \_this
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.endif
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.endif
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.endm
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/*
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* Declare CPU operations
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*
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* _name:
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* Name of the CPU for which operations are being specified
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* _midr:
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* Numeric value expected to read from CPU's MIDR
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* _resetfunc:
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* Reset function for the CPU. If there's no CPU reset function,
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* specify CPU_NO_RESET_FUNC
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* _power_down_ops:
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* Comma-separated list of functions to perform power-down
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* operatios on the CPU. At least one, and up to
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* CPU_MAX_PWR_DWN_OPS number of functions may be specified.
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* Starting at power level 0, these functions shall handle power
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* down at subsequent power levels. If there aren't exactly
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* CPU_MAX_PWR_DWN_OPS functions, the last specified one will be
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* used to handle power down at subsequent levels
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*/
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.macro declare_cpu_ops _name:req, _midr:req, _resetfunc:req, \
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_power_down_ops:vararg
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.section cpu_ops, "a"
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.align 2
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.type cpu_ops_\_name, %object
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.word \_midr
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#if IMAGE_BL1 || IMAGE_BL32
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.if \_noresetfunc
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.word 0
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.else
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.word \_name\()_reset_func
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.endif
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.word \_resetfunc
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#endif
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#if IMAGE_BL32
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.word \_name\()_core_pwr_dwn
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.word \_name\()_cluster_pwr_dwn
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1:
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/* Insert list of functions */
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fill_constants CPU_MAX_PWR_DWN_OPS, \_power_down_ops
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2:
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/*
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* Error if no or more than CPU_MAX_PWR_DWN_OPS were specified in the
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* list
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*/
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.ifeq 2b - 1b
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.error "At least one power down function must be specified"
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.else
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.iflt 2b - 1b - (CPU_MAX_PWR_DWN_OPS * CPU_WORD_SIZE)
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.error "More than CPU_MAX_PWR_DWN_OPS functions specified"
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.endif
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.endif
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#endif
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.endm
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@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2014-2015, ARM Limited and Contributors. All rights reserved.
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* Copyright (c) 2014-2016, ARM Limited and Contributors. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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@ -35,6 +35,15 @@
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#define CPU_IMPL_PN_MASK (MIDR_IMPL_MASK << MIDR_IMPL_SHIFT) | \
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(MIDR_PN_MASK << MIDR_PN_SHIFT)
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/* The number of CPU operations allowed */
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#define CPU_MAX_PWR_DWN_OPS 2
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/* Special constant to specify that CPU has no reset function */
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#define CPU_NO_RESET_FUNC 0
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/* Word size for 64-bit CPUs */
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#define CPU_WORD_SIZE 8
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/*
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* Define the offsets to the fields in cpu_ops structure.
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*/
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@ -47,10 +56,8 @@ CPU_RESET_FUNC: /* cpu_ops reset_func */
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.space 8
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#endif
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#if IMAGE_BL31 /* The power down core and cluster is needed only in BL31 */
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CPU_PWR_DWN_CORE: /* cpu_ops core_pwr_dwn */
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.space 8
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CPU_PWR_DWN_CLUSTER: /* cpu_ops cluster_pwr_dwn */
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.space 8
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CPU_PWR_DWN_OPS: /* cpu_ops power down functions */
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.space (8 * CPU_MAX_PWR_DWN_OPS)
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#endif
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#if (IMAGE_BL31 && CRASH_REPORTING)
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CPU_REG_DUMP: /* cpu specific register dump for crash reporting */
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@ -59,24 +66,80 @@ CPU_REG_DUMP: /* cpu specific register dump for crash reporting */
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CPU_OPS_SIZE = .
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/*
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* Convenience macro to declare cpu_ops structure.
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* Make sure the structure fields are as per the offsets
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* defined above.
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* Write given expressions as quad words
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*
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* _count:
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* Write at least _count quad words. If the given number of
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* expressions is less than _count, repeat the last expression to
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* fill _count quad words in total
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* _rest:
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* Optional list of expressions. _this is for parameter extraction
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* only, and has no significance to the caller
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*
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* Invoked as:
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* fill_constants 2, foo, bar, blah, ...
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*/
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.macro declare_cpu_ops _name:req, _midr:req, _noresetfunc = 0
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.section cpu_ops, "a"; .align 3
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.macro fill_constants _count:req, _this, _rest:vararg
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.ifgt \_count
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/* Write the current expression */
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.ifb \_this
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.error "Nothing to fill"
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.endif
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.quad \_this
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/* Invoke recursively for remaining expressions */
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.ifnb \_rest
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fill_constants \_count-1, \_rest
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.else
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fill_constants \_count-1, \_this
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.endif
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.endif
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.endm
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/*
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* Declare CPU operations
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*
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* _name:
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* Name of the CPU for which operations are being specified
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* _midr:
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* Numeric value expected to read from CPU's MIDR
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* _resetfunc:
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* Reset function for the CPU. If there's no CPU reset function,
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* specify CPU_NO_RESET_FUNC
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* _power_down_ops:
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* Comma-separated list of functions to perform power-down
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* operatios on the CPU. At least one, and up to
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* CPU_MAX_PWR_DWN_OPS number of functions may be specified.
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* Starting at power level 0, these functions shall handle power
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* down at subsequent power levels. If there aren't exactly
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* CPU_MAX_PWR_DWN_OPS functions, the last specified one will be
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* used to handle power down at subsequent levels
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*/
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.macro declare_cpu_ops _name:req, _midr:req, _resetfunc:req, \
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_power_down_ops:vararg
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.section cpu_ops, "a"
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.align 3
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.type cpu_ops_\_name, %object
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.quad \_midr
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#if IMAGE_BL1 || IMAGE_BL31
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.if \_noresetfunc
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.quad 0
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.else
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.quad \_name\()_reset_func
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.endif
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.quad \_resetfunc
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#endif
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#if IMAGE_BL31
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.quad \_name\()_core_pwr_dwn
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.quad \_name\()_cluster_pwr_dwn
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1:
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/* Insert list of functions */
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fill_constants CPU_MAX_PWR_DWN_OPS, \_power_down_ops
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2:
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/*
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* Error if no or more than CPU_MAX_PWR_DWN_OPS were specified in the
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* list
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*/
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.ifeq 2b - 1b
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.error "At least one power down function must be specified"
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.else
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.iflt 2b - 1b - (CPU_MAX_PWR_DWN_OPS * CPU_WORD_SIZE)
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.error "More than CPU_MAX_PWR_DWN_OPS functions specified"
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.endif
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.endif
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#endif
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#if (IMAGE_BL31 && CRASH_REPORTING)
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.quad \_name\()_cpu_reg_dump
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@ -65,4 +65,6 @@ func aem_generic_cluster_pwr_dwn
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endfunc aem_generic_cluster_pwr_dwn
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/* cpu_ops for Base AEM FVP */
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declare_cpu_ops aem_generic, BASE_AEM_MIDR, 1
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declare_cpu_ops aem_generic, BASE_AEM_MIDR, CPU_NO_RESET_FUNC, \
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aem_generic_core_pwr_dwn, \
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aem_generic_cluster_pwr_dwn
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@ -141,4 +141,7 @@ func cortex_a32_cluster_pwr_dwn
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b cortex_a32_disable_smp
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endfunc cortex_a32_cluster_pwr_dwn
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declare_cpu_ops cortex_a32, CORTEX_A32_MIDR
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declare_cpu_ops cortex_a32, CORTEX_A32_MIDR, \
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cortex_a32_reset_func, \
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cortex_a32_core_pwr_dwn, \
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cortex_a32_cluster_pwr_dwn
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@ -70,50 +70,39 @@ endfunc reset_handler
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#if IMAGE_BL32 /* The power down core and cluster is needed only in BL32 */
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/*
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* The prepare core power down function for all platforms. After
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* the cpu_ops pointer is retrieved from cpu_data, the corresponding
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* pwr_dwn_core in the cpu_ops is invoked. Follows AAPCS.
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* void prepare_cpu_pwr_dwn(unsigned int power_level)
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*
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* Prepare CPU power down function for all platforms. The function takes
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* a domain level to be powered down as its parameter. After the cpu_ops
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* pointer is retrieved from cpu_data, the handler for requested power
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* level is called.
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*/
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.globl prepare_core_pwr_dwn
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func prepare_core_pwr_dwn
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/* r12 is pushed to meet the 8 byte stack alignment requirement */
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push {r12, lr}
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bl _cpu_data
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pop {r12, lr}
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ldr r1, [r0, #CPU_DATA_CPU_OPS_PTR]
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#if ASM_ASSERTION
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cmp r1, #0
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ASM_ASSERT(ne)
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#endif
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/* Get the cpu_ops core_pwr_dwn handler */
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ldr r0, [r1, #CPU_PWR_DWN_CORE]
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bx r0
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endfunc prepare_core_pwr_dwn
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.globl prepare_cpu_pwr_dwn
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func prepare_cpu_pwr_dwn
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/*
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* The prepare cluster power down function for all platforms. After
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* the cpu_ops pointer is retrieved from cpu_data, the corresponding
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* pwr_dwn_cluster in the cpu_ops is invoked. Follows AAPCS.
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* If the given power level exceeds CPU_MAX_PWR_DWN_OPS, we call the
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* power down handler for the last power level
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*/
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.globl prepare_cluster_pwr_dwn
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func prepare_cluster_pwr_dwn
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/* r12 is pushed to meet the 8 byte stack alignment requirement */
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push {r12, lr}
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bl _cpu_data
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pop {r12, lr}
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mov r2, #(CPU_MAX_PWR_DWN_OPS - 1)
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cmp r0, r2
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movhi r0, r2
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ldr r1, [r0, #CPU_DATA_CPU_OPS_PTR]
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push {r0, lr}
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bl _cpu_data
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pop {r2, lr}
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ldr r0, [r0, #CPU_DATA_CPU_OPS_PTR]
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#if ASM_ASSERTION
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cmp r1, #0
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cmp r0, #0
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ASM_ASSERT(ne)
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#endif
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/* Get the cpu_ops cluster_pwr_dwn handler */
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ldr r0, [r1, #CPU_PWR_DWN_CLUSTER]
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bx r0
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endfunc prepare_cluster_pwr_dwn
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/* Get the appropriate power down handler */
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mov r1, #CPU_PWR_DWN_OPS
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add r1, r1, r2, lsl #2
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ldr r1, [r0, r1]
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bx r1
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endfunc prepare_cpu_pwr_dwn
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/*
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* Initializes the cpu_ops_ptr if not already initialized
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@ -90,7 +90,11 @@ endfunc aem_generic_cpu_reg_dump
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/* cpu_ops for Base AEM FVP */
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declare_cpu_ops aem_generic, BASE_AEM_MIDR, 1
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declare_cpu_ops aem_generic, BASE_AEM_MIDR, CPU_NO_RESET_FUNC, \
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aem_generic_core_pwr_dwn, \
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aem_generic_cluster_pwr_dwn
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/* cpu_ops for Foundation FVP */
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declare_cpu_ops aem_generic, FOUNDATION_AEM_MIDR, 1
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declare_cpu_ops aem_generic, FOUNDATION_AEM_MIDR, CPU_NO_RESET_FUNC, \
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aem_generic_core_pwr_dwn, \
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aem_generic_cluster_pwr_dwn
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|
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@ -157,4 +157,7 @@ func cortex_a35_cpu_reg_dump
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ret
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endfunc cortex_a35_cpu_reg_dump
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declare_cpu_ops cortex_a35, CORTEX_A35_MIDR
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declare_cpu_ops cortex_a35, CORTEX_A35_MIDR, \
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cortex_a35_reset_func, \
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cortex_a35_core_pwr_dwn, \
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cortex_a35_cluster_pwr_dwn
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|
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@ -244,4 +244,7 @@ func cortex_a53_cpu_reg_dump
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ret
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endfunc cortex_a53_cpu_reg_dump
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declare_cpu_ops cortex_a53, CORTEX_A53_MIDR
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declare_cpu_ops cortex_a53, CORTEX_A53_MIDR, \
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cortex_a53_reset_func, \
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cortex_a53_core_pwr_dwn, \
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cortex_a53_cluster_pwr_dwn
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|
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@ -488,4 +488,7 @@ func cortex_a57_cpu_reg_dump
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endfunc cortex_a57_cpu_reg_dump
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declare_cpu_ops cortex_a57, CORTEX_A57_MIDR
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declare_cpu_ops cortex_a57, CORTEX_A57_MIDR, \
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cortex_a57_reset_func, \
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cortex_a57_core_pwr_dwn, \
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cortex_a57_cluster_pwr_dwn
|
||||
|
|
|
|||
|
|
@ -242,4 +242,7 @@ func cortex_a72_cpu_reg_dump
|
|||
endfunc cortex_a72_cpu_reg_dump
|
||||
|
||||
|
||||
declare_cpu_ops cortex_a72, CORTEX_A72_MIDR
|
||||
declare_cpu_ops cortex_a72, CORTEX_A72_MIDR, \
|
||||
cortex_a72_reset_func, \
|
||||
cortex_a72_core_pwr_dwn, \
|
||||
cortex_a72_cluster_pwr_dwn
|
||||
|
|
|
|||
|
|
@ -153,4 +153,7 @@ func cortex_a73_cpu_reg_dump
|
|||
ret
|
||||
endfunc cortex_a73_cpu_reg_dump
|
||||
|
||||
declare_cpu_ops cortex_a73, CORTEX_A73_MIDR
|
||||
declare_cpu_ops cortex_a73, CORTEX_A73_MIDR, \
|
||||
cortex_a73_reset_func, \
|
||||
cortex_a73_core_pwr_dwn, \
|
||||
cortex_a73_cluster_pwr_dwn
|
||||
|
|
|
|||
|
|
@ -74,31 +74,23 @@ endfunc reset_handler
|
|||
|
||||
#if IMAGE_BL31 /* The power down core and cluster is needed only in BL31 */
|
||||
/*
|
||||
* The prepare core power down function for all platforms. After
|
||||
* the cpu_ops pointer is retrieved from cpu_data, the corresponding
|
||||
* pwr_dwn_core in the cpu_ops is invoked.
|
||||
* void prepare_cpu_pwr_dwn(unsigned int power_level)
|
||||
*
|
||||
* Prepare CPU power down function for all platforms. The function takes
|
||||
* a domain level to be powered down as its parameter. After the cpu_ops
|
||||
* pointer is retrieved from cpu_data, the handler for requested power
|
||||
* level is called.
|
||||
*/
|
||||
.globl prepare_core_pwr_dwn
|
||||
func prepare_core_pwr_dwn
|
||||
mrs x1, tpidr_el3
|
||||
ldr x0, [x1, #CPU_DATA_CPU_OPS_PTR]
|
||||
#if ASM_ASSERTION
|
||||
cmp x0, #0
|
||||
ASM_ASSERT(ne)
|
||||
#endif
|
||||
|
||||
/* Get the cpu_ops core_pwr_dwn handler */
|
||||
ldr x1, [x0, #CPU_PWR_DWN_CORE]
|
||||
br x1
|
||||
endfunc prepare_core_pwr_dwn
|
||||
|
||||
.globl prepare_cpu_pwr_dwn
|
||||
func prepare_cpu_pwr_dwn
|
||||
/*
|
||||
* The prepare cluster power down function for all platforms. After
|
||||
* the cpu_ops pointer is retrieved from cpu_data, the corresponding
|
||||
* pwr_dwn_cluster in the cpu_ops is invoked.
|
||||
* If the given power level exceeds CPU_MAX_PWR_DWN_OPS, we call the
|
||||
* power down handler for the last power level
|
||||
*/
|
||||
.globl prepare_cluster_pwr_dwn
|
||||
func prepare_cluster_pwr_dwn
|
||||
mov_imm x2, (CPU_MAX_PWR_DWN_OPS - 1)
|
||||
cmp x0, x2
|
||||
csel x2, x2, x0, hi
|
||||
|
||||
mrs x1, tpidr_el3
|
||||
ldr x0, [x1, #CPU_DATA_CPU_OPS_PTR]
|
||||
#if ASM_ASSERTION
|
||||
|
|
@ -106,10 +98,12 @@ func prepare_cluster_pwr_dwn
|
|||
ASM_ASSERT(ne)
|
||||
#endif
|
||||
|
||||
/* Get the cpu_ops cluster_pwr_dwn handler */
|
||||
ldr x1, [x0, #CPU_PWR_DWN_CLUSTER]
|
||||
/* Get the appropriate power down handler */
|
||||
mov x1, #CPU_PWR_DWN_OPS
|
||||
add x1, x1, x2, lsl #3
|
||||
ldr x1, [x0, x1]
|
||||
br x1
|
||||
endfunc prepare_cluster_pwr_dwn
|
||||
endfunc prepare_cpu_pwr_dwn
|
||||
|
||||
|
||||
/*
|
||||
|
|
|
|||
|
|
@ -163,4 +163,7 @@ func denver_cpu_reg_dump
|
|||
ret
|
||||
endfunc denver_cpu_reg_dump
|
||||
|
||||
declare_cpu_ops denver, DENVER_1_0_MIDR
|
||||
declare_cpu_ops denver, DENVER_1_0_MIDR, \
|
||||
denver_reset_func, \
|
||||
denver_core_pwr_dwn, \
|
||||
denver_cluster_pwr_dwn
|
||||
|
|
|
|||
|
|
@ -65,22 +65,13 @@ func psci_do_pwrdown_cache_maintenance
|
|||
bl do_stack_maintenance
|
||||
|
||||
/* ---------------------------------------------
|
||||
* Determine how many levels of cache will be
|
||||
* subject to cache maintenance. Power level
|
||||
* 0 implies that only the cpu is being powered
|
||||
* down. Only the L1 data cache needs to be
|
||||
* flushed to the PoU in this case. For a higher
|
||||
* power level we are assuming that a flush
|
||||
* of L1 data and L2 unified cache is enough.
|
||||
* This information should be provided by the
|
||||
* platform.
|
||||
* Invoke CPU-specifc power down operations for
|
||||
* the appropriate level
|
||||
* ---------------------------------------------
|
||||
*/
|
||||
cmp r4, #PSCI_CPU_PWR_LVL
|
||||
pop {r4,lr}
|
||||
|
||||
beq prepare_core_pwr_dwn
|
||||
b prepare_cluster_pwr_dwn
|
||||
mov r0, r4
|
||||
pop {r4, lr}
|
||||
b prepare_cpu_pwr_dwn
|
||||
endfunc psci_do_pwrdown_cache_maintenance
|
||||
|
||||
|
||||
|
|
|
|||
|
|
@ -59,24 +59,11 @@ func psci_do_pwrdown_cache_maintenance
|
|||
stp x19, x20, [sp,#-16]!
|
||||
|
||||
/* ---------------------------------------------
|
||||
* Determine to how many levels of cache will be
|
||||
* subject to cache maintenance. Power level
|
||||
* 0 implies that only the cpu is being powered
|
||||
* down. Only the L1 data cache needs to be
|
||||
* flushed to the PoU in this case. For a higher
|
||||
* power level we are assuming that a flush
|
||||
* of L1 data and L2 unified cache is enough.
|
||||
* This information should be provided by the
|
||||
* platform.
|
||||
* Invoke CPU-specific power down operations for
|
||||
* the appropriate level
|
||||
* ---------------------------------------------
|
||||
*/
|
||||
cmp w0, #PSCI_CPU_PWR_LVL
|
||||
b.eq do_core_pwr_dwn
|
||||
bl prepare_cluster_pwr_dwn
|
||||
b do_stack_maintenance
|
||||
|
||||
do_core_pwr_dwn:
|
||||
bl prepare_core_pwr_dwn
|
||||
bl prepare_cpu_pwr_dwn
|
||||
|
||||
/* ---------------------------------------------
|
||||
* Do stack maintenance by flushing the used
|
||||
|
|
@ -84,7 +71,6 @@ do_core_pwr_dwn:
|
|||
* remainder.
|
||||
* ---------------------------------------------
|
||||
*/
|
||||
do_stack_maintenance:
|
||||
bl plat_get_my_stack
|
||||
|
||||
/* ---------------------------------------------
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue