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5dd9dbb5bf
Various CPU drivers in ARM Trusted Firmware register functions to handle
power-down operations. At present, separate functions are registered to
power down individual cores and clusters.
This scheme operates on the basis of core and cluster, and doesn't cater
for extending the hierarchy for power-down operations. For example,
future CPUs might support multiple threads which might need powering
down individually.
This patch therefore reworks the CPU operations framework to allow for
registering power down handlers on specific level basis. Henceforth:
- Generic code invokes CPU power down operations by the level
required.
- CPU drivers explicitly mention CPU_NO_RESET_FUNC when the CPU has no
reset function.
- CPU drivers register power down handlers as a list: a mandatory
handler for level 0, and optional handlers for higher levels.
All existing CPU drivers are adapted to the new CPU operations framework
without needing any functional changes within.
Also update firmware design guide.
Change-Id: I1826842d37a9e60a9e85fdcee7b4b8f6bc1ad043
Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
172 lines
5.7 KiB
ArmAsm
172 lines
5.7 KiB
ArmAsm
/*
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* Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* Redistributions of source code must retain the above copyright notice, this
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* list of conditions and the following disclaimer.
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*
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* Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* Neither the name of ARM nor the names of its contributors may be used
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* to endorse or promote products derived from this software without specific
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* prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <asm_macros.S>
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#include <platform_def.h>
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#include <psci.h>
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.globl psci_do_pwrdown_cache_maintenance
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.globl psci_do_pwrup_cache_maintenance
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.globl psci_power_down_wfi
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/* -----------------------------------------------------------------------
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* void psci_do_pwrdown_cache_maintenance(unsigned int power level);
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*
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* This function performs cache maintenance for the specified power
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* level. The levels of cache affected are determined by the power
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* level which is passed as the argument i.e. level 0 results
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* in a flush of the L1 cache. Both the L1 and L2 caches are flushed
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* for a higher power level.
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*
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* Additionally, this function also ensures that stack memory is correctly
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* flushed out to avoid coherency issues due to a change in its memory
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* attributes after the data cache is disabled.
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* -----------------------------------------------------------------------
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*/
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func psci_do_pwrdown_cache_maintenance
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push {r4, lr}
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/* ----------------------------------------------
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* Turn OFF cache and do stack maintenance
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* prior to cpu operations . This sequence is
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* different from AArch64 because in AArch32 the
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* assembler routines for cpu operations utilize
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* the stack whereas in AArch64 it doesn't.
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* ----------------------------------------------
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*/
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mov r4, r0
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bl do_stack_maintenance
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/* ---------------------------------------------
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* Invoke CPU-specifc power down operations for
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* the appropriate level
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* ---------------------------------------------
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*/
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mov r0, r4
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pop {r4, lr}
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b prepare_cpu_pwr_dwn
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endfunc psci_do_pwrdown_cache_maintenance
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/* -----------------------------------------------------------------------
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* void psci_do_pwrup_cache_maintenance(void);
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*
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* This function performs cache maintenance after this cpu is powered up.
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* Currently, this involves managing the used stack memory before turning
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* on the data cache.
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* -----------------------------------------------------------------------
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*/
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func psci_do_pwrup_cache_maintenance
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/* r12 is pushed to meet the 8 byte stack alignment requirement */
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push {r12, lr}
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/* ---------------------------------------------
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* Ensure any inflight stack writes have made it
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* to main memory.
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* ---------------------------------------------
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*/
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dmb st
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/* ---------------------------------------------
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* Calculate and store the size of the used
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* stack memory in r1. Calculate and store the
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* stack base address in r0.
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* ---------------------------------------------
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*/
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bl plat_get_my_stack
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mov r1, sp
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sub r1, r0, r1
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mov r0, sp
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bl inv_dcache_range
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/* ---------------------------------------------
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* Enable the data cache.
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* ---------------------------------------------
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*/
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ldcopr r0, SCTLR
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orr r0, r0, #SCTLR_C_BIT
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stcopr r0, SCTLR
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isb
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pop {r12, pc}
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endfunc psci_do_pwrup_cache_maintenance
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/* ---------------------------------------------
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* void do_stack_maintenance(void)
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* Do stack maintenance by flushing the used
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* stack to the main memory and invalidating the
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* remainder.
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* ---------------------------------------------
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*/
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func do_stack_maintenance
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push {r4, lr}
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bl plat_get_my_stack
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/* Turn off the D-cache */
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ldcopr r1, SCTLR
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bic r1, #SCTLR_C_BIT
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stcopr r1, SCTLR
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isb
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/* ---------------------------------------------
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* Calculate and store the size of the used
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* stack memory in r1.
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* ---------------------------------------------
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*/
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mov r4, r0
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mov r1, sp
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sub r1, r0, r1
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mov r0, sp
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bl flush_dcache_range
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/* ---------------------------------------------
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* Calculate and store the size of the unused
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* stack memory in r1. Calculate and store the
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* stack base address in r0.
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* ---------------------------------------------
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*/
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sub r0, r4, #PLATFORM_STACK_SIZE
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sub r1, sp, r0
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bl inv_dcache_range
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pop {r4, pc}
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endfunc do_stack_maintenance
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/* -----------------------------------------------------------------------
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* This function is called to indicate to the power controller that it
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* is safe to power down this cpu. It should not exit the wfi and will
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* be released from reset upon power up.
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* -----------------------------------------------------------------------
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*/
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func psci_power_down_wfi
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dsb sy // ensure write buffer empty
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wfi
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no_ret plat_panic_handler
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endfunc psci_power_down_wfi
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