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feat(stm32mp1-fdts): remove PLL1 settings

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TF-A BL2 always boot at 650MHz using an algorithm to calculate PLL1
settings, without reading DT. Remove the corresponding nodes.

Change-Id: I0003337d8d37df7b2a70a84b5475f4278c4c4669
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com>
This commit is contained in:
Gabriel Fernandez 2023-02-01 14:25:25 +01:00 • committed by Yann Gautier
parent ae1e503763
commit 66d7c8bf8e
8 changed files with 0 additions and 151 deletions
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19
fdts/stm32mp135f-dk.dts
View file

@ -216,12 +216,6 @@
>;
st,pll_vco {
pll1_vco_1300Mhz: pll1-vco-1300Mhz {
src = < CLK_PLL12_HSE >;
divmn = < 2 80 >;
frac = < 0x800 >;
};
pll2_vco_1066Mhz: pll2-vco-1066Mhz {
src = <CLK_PLL12_HSE>;
divmn = <2 65>;
@ -240,19 +234,6 @@
};
};
/* VCO = 1300.0 MHz => P = 650 (CPU) */
pll1:st,pll@0 {
compatible = "st,stm32mp1-pll";
reg = <0>;
st,pll = < &pll1_cfg1 >;
pll1_cfg1: pll1_cfg1 {
st,pll_vco = < &pll1_vco_1300Mhz >;
st,pll_div_pqr = < 0 1 1 >;
};
};
/* VCO = 1066.0 MHz => P = 266 (AXI), Q = 266, R = 533 (DDR) */
pll2:st,pll@1 {
compatible = "st,stm32mp1-pll";

19
fdts/stm32mp157a-avenger96.dts
View file

@ -230,12 +230,6 @@
>;
st,pll_vco {
pll1_vco_1300Mhz: pll1-vco-1300Mhz {
src = < CLK_PLL12_HSE >;
divmn = < 2 80 >;
frac = < 0x800 >;
};
pll2_vco_1066Mhz: pll2-vco-1066Mhz {
src = <CLK_PLL12_HSE>;
divmn = <2 65>;
@ -254,19 +248,6 @@
};
};
/* VCO = 1300.0 MHz => P = 650 (CPU) */
pll1: st,pll@0 {
compatible = "st,stm32mp1-pll";
reg = <0>;
st,pll = < &pll1_cfg1 >;
pll1_cfg1: pll1_cfg1 {
st,pll_vco = < &pll1_vco_1300Mhz >;
st,pll_div_pqr = < 0 0 0 >;
};
};
/* VCO = 1066.0 MHz => P = 266 (AXI), Q = 533 (GPU), R = 533 (DDR) */
pll2: st,pll@1 {
compatible = "st,stm32mp1-pll";

19
fdts/stm32mp157c-ed1.dts
View file

@ -249,12 +249,6 @@
>;
st,pll_vco {
pll1_vco_1300Mhz: pll1-vco-1300Mhz {
src = < CLK_PLL12_HSE >;
divmn = < 2 80 >;
frac = < 0x800 >;
};
pll2_vco_1066Mhz: pll2-vco-1066Mhz {
src = <CLK_PLL12_HSE>;
divmn = <2 65>;
@ -273,19 +267,6 @@
};
};
/* VCO = 1300.0 MHz => P = 650 (CPU) */
pll1: st,pll@0 {
compatible = "st,stm32mp1-pll";
reg = <0>;
st,pll = < &pll1_cfg1 >;
pll1_cfg1: pll1_cfg1 {
st,pll_vco = < &pll1_vco_1300Mhz >;
st,pll_div_pqr = < 0 0 0 >;
};
};
/* VCO = 1066.0 MHz => P = 266 (AXI), Q = 533 (GPU), R = 533 (DDR) */
pll2: st,pll@1 {
compatible = "st,stm32mp1-pll";

19
fdts/stm32mp157c-odyssey-som.dtsi
View file

@ -262,12 +262,6 @@
>;
st,pll_vco {
pll1_vco_1300Mhz: pll1-vco-1300Mhz {
src = < CLK_PLL12_HSE >;
divmn = < 2 80 >;
frac = < 0x800 >;
};
pll2_vco_1066Mhz: pll2-vco-1066Mhz {
src = <CLK_PLL12_HSE>;
divmn = <2 65>;
@ -286,19 +280,6 @@
};
};
/* VCO = 1300.0 MHz => P = 650 (CPU) */
pll1: st,pll@0 {
compatible = "st,stm32mp1-pll";
reg = <0>;
st,pll = < &pll1_cfg1 >;
pll1_cfg1: pll1_cfg1 {
st,pll_vco = < &pll1_vco_1300Mhz >;
st,pll_div_pqr = < 0 0 0 >;
};
};
/* VCO = 1066.0 MHz => P = 266 (AXI), Q = 533 (GPU), R = 533 (DDR) */
pll2: st,pll@1 {
compatible = "st,stm32mp1-pll";

18
fdts/stm32mp15xx-dhcom-som.dtsi
View file

@ -248,12 +248,6 @@
>;
st,pll_vco {
pll1_vco_1300Mhz: pll1-vco-1300Mhz {
src = < CLK_PLL12_HSE >;
divmn = < 2 80 >;
frac = < 0x800 >;
};
pll2_vco_1066Mhz: pll2-vco-1066Mhz {
src = <CLK_PLL12_HSE>;
divmn = <2 65>;
@ -272,18 +266,6 @@
};
};
/* VCO = 1300.0 MHz => P = 650 (CPU) */
pll1: st,pll@0 {
compatible = "st,stm32mp1-pll";
reg = <0>;
st,pll = < &pll1_cfg1 >;
pll1_cfg1: pll1_cfg1 {
st,pll_vco = < &pll1_vco_1300Mhz >;
st,pll_div_pqr = < 0 0 0 >;
};
};
/* VCO = 1066.0 MHz => P = 266 (AXI), Q = 533 (GPU), R = 533 (DDR) */
pll2: st,pll@1 {
compatible = "st,stm32mp1-pll";

19
fdts/stm32mp15xx-dhcor-som.dtsi
View file

@ -243,12 +243,6 @@
>;
st,pll_vco {
pll1_vco_1300Mhz: pll1-vco-1300Mhz {
src = < CLK_PLL12_HSE >;
divmn = < 2 80 >;
frac = < 0x800 >;
};
pll2_vco_1066Mhz: pll2-vco-1066Mhz {
src = <CLK_PLL12_HSE>;
divmn = <2 65>;
@ -267,19 +261,6 @@
};
};
/* VCO = 1300.0 MHz => P = 650 (CPU) */
pll1: st,pll@0 {
compatible = "st,stm32mp1-pll";
reg = <0>;
st,pll = < &pll1_cfg1 >;
pll1_cfg1: pll1_cfg1 {
st,pll_vco = < &pll1_vco_1300Mhz >;
st,pll_div_pqr = < 0 0 0 >;
};
};
/* VCO = 1066.0 MHz => P = 266 (AXI), Q = 533 (GPU), R = 533 (DDR) */
pll2: st,pll@1 {
compatible = "st,stm32mp1-pll";

19
fdts/stm32mp15xx-dkx.dtsi
View file

@ -253,12 +253,6 @@
>;
st,pll_vco {
pll1_vco_1300Mhz: pll1-vco-1300Mhz {
src = < CLK_PLL12_HSE >;
divmn = < 2 80 >;
frac = < 0x800 >;
};
pll2_vco_1066Mhz: pll2-vco-1066Mhz {
src = <CLK_PLL12_HSE>;
divmn = <2 65>;
@ -277,19 +271,6 @@
};
};
/* VCO = 1300.0 MHz => P = 650 (CPU) */
pll1: st,pll@0 {
compatible = "st,stm32mp1-pll";
reg = <0>;
st,pll = < &pll1_cfg1 >;
pll1_cfg1: pll1_cfg1 {
st,pll_vco = < &pll1_vco_1300Mhz >;
st,pll_div_pqr = < 0 0 0 >;
};
};
/* VCO = 1066.0 MHz => P = 266 (AXI), Q = 533 (GPU), R = 533 (DDR) */
pll2: st,pll@1 {
compatible = "st,stm32mp1-pll";

19
fdts/stm32mp15xx-osd32.dtsi
View file

@ -240,12 +240,6 @@
>;
st,pll_vco {
pll1_vco_1300Mhz: pll1-vco-1300Mhz {
src = < CLK_PLL12_HSE >;
divmn = < 2 80 >;
frac = < 0x800 >;
};
pll2_vco_1066Mhz: pll2-vco-1066Mhz {
src = <CLK_PLL12_HSE>;
divmn = <2 65>;
@ -264,19 +258,6 @@
};
};
/* VCO = 1300.0 MHz => P = 650 (CPU) */
pll1: st,pll@0 {
compatible = "st,stm32mp1-pll";
reg = <0>;
st,pll = < &pll1_cfg1 >;
pll1_cfg1: pll1_cfg1 {
st,pll_vco = < &pll1_vco_1300Mhz >;
st,pll_div_pqr = < 0 0 0 >;
};
};
/* VCO = 1066.0 MHz => P = 266 (AXI), Q = 533 (GPU), R = 533 (DDR) */
pll2: st,pll@1 {
compatible = "st,stm32mp1-pll";