diff --git a/fdts/stm32mp135f-dk.dts b/fdts/stm32mp135f-dk.dts index 7a7d461b7..9a3a59435 100644 --- a/fdts/stm32mp135f-dk.dts +++ b/fdts/stm32mp135f-dk.dts @@ -216,12 +216,6 @@ >; st,pll_vco { - pll1_vco_1300Mhz: pll1-vco-1300Mhz { - src = < CLK_PLL12_HSE >; - divmn = < 2 80 >; - frac = < 0x800 >; - }; - pll2_vco_1066Mhz: pll2-vco-1066Mhz { src = ; divmn = <2 65>; @@ -240,19 +234,6 @@ }; }; - /* VCO = 1300.0 MHz => P = 650 (CPU) */ - pll1:st,pll@0 { - compatible = "st,stm32mp1-pll"; - reg = <0>; - - st,pll = < &pll1_cfg1 >; - - pll1_cfg1: pll1_cfg1 { - st,pll_vco = < &pll1_vco_1300Mhz >; - st,pll_div_pqr = < 0 1 1 >; - }; - }; - /* VCO = 1066.0 MHz => P = 266 (AXI), Q = 266, R = 533 (DDR) */ pll2:st,pll@1 { compatible = "st,stm32mp1-pll"; diff --git a/fdts/stm32mp157a-avenger96.dts b/fdts/stm32mp157a-avenger96.dts index a382431a6..7135970c0 100644 --- a/fdts/stm32mp157a-avenger96.dts +++ b/fdts/stm32mp157a-avenger96.dts @@ -230,12 +230,6 @@ >; st,pll_vco { - pll1_vco_1300Mhz: pll1-vco-1300Mhz { - src = < CLK_PLL12_HSE >; - divmn = < 2 80 >; - frac = < 0x800 >; - }; - pll2_vco_1066Mhz: pll2-vco-1066Mhz { src = ; divmn = <2 65>; @@ -254,19 +248,6 @@ }; }; - /* VCO = 1300.0 MHz => P = 650 (CPU) */ - pll1: st,pll@0 { - compatible = "st,stm32mp1-pll"; - reg = <0>; - - st,pll = < &pll1_cfg1 >; - - pll1_cfg1: pll1_cfg1 { - st,pll_vco = < &pll1_vco_1300Mhz >; - st,pll_div_pqr = < 0 0 0 >; - }; - }; - /* VCO = 1066.0 MHz => P = 266 (AXI), Q = 533 (GPU), R = 533 (DDR) */ pll2: st,pll@1 { compatible = "st,stm32mp1-pll"; diff --git a/fdts/stm32mp157c-ed1.dts b/fdts/stm32mp157c-ed1.dts index 86f47aec6..fe5f464be 100644 --- a/fdts/stm32mp157c-ed1.dts +++ b/fdts/stm32mp157c-ed1.dts @@ -249,12 +249,6 @@ >; st,pll_vco { - pll1_vco_1300Mhz: pll1-vco-1300Mhz { - src = < CLK_PLL12_HSE >; - divmn = < 2 80 >; - frac = < 0x800 >; - }; - pll2_vco_1066Mhz: pll2-vco-1066Mhz { src = ; divmn = <2 65>; @@ -273,19 +267,6 @@ }; }; - /* VCO = 1300.0 MHz => P = 650 (CPU) */ - pll1: st,pll@0 { - compatible = "st,stm32mp1-pll"; - reg = <0>; - - st,pll = < &pll1_cfg1 >; - - pll1_cfg1: pll1_cfg1 { - st,pll_vco = < &pll1_vco_1300Mhz >; - st,pll_div_pqr = < 0 0 0 >; - }; - }; - /* VCO = 1066.0 MHz => P = 266 (AXI), Q = 533 (GPU), R = 533 (DDR) */ pll2: st,pll@1 { compatible = "st,stm32mp1-pll"; diff --git a/fdts/stm32mp157c-odyssey-som.dtsi b/fdts/stm32mp157c-odyssey-som.dtsi index 512d83c82..e5d41fc79 100644 --- a/fdts/stm32mp157c-odyssey-som.dtsi +++ b/fdts/stm32mp157c-odyssey-som.dtsi @@ -262,12 +262,6 @@ >; st,pll_vco { - pll1_vco_1300Mhz: pll1-vco-1300Mhz { - src = < CLK_PLL12_HSE >; - divmn = < 2 80 >; - frac = < 0x800 >; - }; - pll2_vco_1066Mhz: pll2-vco-1066Mhz { src = ; divmn = <2 65>; @@ -286,19 +280,6 @@ }; }; - /* VCO = 1300.0 MHz => P = 650 (CPU) */ - pll1: st,pll@0 { - compatible = "st,stm32mp1-pll"; - reg = <0>; - - st,pll = < &pll1_cfg1 >; - - pll1_cfg1: pll1_cfg1 { - st,pll_vco = < &pll1_vco_1300Mhz >; - st,pll_div_pqr = < 0 0 0 >; - }; - }; - /* VCO = 1066.0 MHz => P = 266 (AXI), Q = 533 (GPU), R = 533 (DDR) */ pll2: st,pll@1 { compatible = "st,stm32mp1-pll"; diff --git a/fdts/stm32mp15xx-dhcom-som.dtsi b/fdts/stm32mp15xx-dhcom-som.dtsi index 998247b2a..12846db8b 100644 --- a/fdts/stm32mp15xx-dhcom-som.dtsi +++ b/fdts/stm32mp15xx-dhcom-som.dtsi @@ -248,12 +248,6 @@ >; st,pll_vco { - pll1_vco_1300Mhz: pll1-vco-1300Mhz { - src = < CLK_PLL12_HSE >; - divmn = < 2 80 >; - frac = < 0x800 >; - }; - pll2_vco_1066Mhz: pll2-vco-1066Mhz { src = ; divmn = <2 65>; @@ -272,18 +266,6 @@ }; }; - /* VCO = 1300.0 MHz => P = 650 (CPU) */ - pll1: st,pll@0 { - compatible = "st,stm32mp1-pll"; - reg = <0>; - - st,pll = < &pll1_cfg1 >; - - pll1_cfg1: pll1_cfg1 { - st,pll_vco = < &pll1_vco_1300Mhz >; - st,pll_div_pqr = < 0 0 0 >; - }; - }; /* VCO = 1066.0 MHz => P = 266 (AXI), Q = 533 (GPU), R = 533 (DDR) */ pll2: st,pll@1 { compatible = "st,stm32mp1-pll"; diff --git a/fdts/stm32mp15xx-dhcor-som.dtsi b/fdts/stm32mp15xx-dhcor-som.dtsi index 783d4452a..2ebfb2de8 100644 --- a/fdts/stm32mp15xx-dhcor-som.dtsi +++ b/fdts/stm32mp15xx-dhcor-som.dtsi @@ -243,12 +243,6 @@ >; st,pll_vco { - pll1_vco_1300Mhz: pll1-vco-1300Mhz { - src = < CLK_PLL12_HSE >; - divmn = < 2 80 >; - frac = < 0x800 >; - }; - pll2_vco_1066Mhz: pll2-vco-1066Mhz { src = ; divmn = <2 65>; @@ -267,19 +261,6 @@ }; }; - /* VCO = 1300.0 MHz => P = 650 (CPU) */ - pll1: st,pll@0 { - compatible = "st,stm32mp1-pll"; - reg = <0>; - - st,pll = < &pll1_cfg1 >; - - pll1_cfg1: pll1_cfg1 { - st,pll_vco = < &pll1_vco_1300Mhz >; - st,pll_div_pqr = < 0 0 0 >; - }; - }; - /* VCO = 1066.0 MHz => P = 266 (AXI), Q = 533 (GPU), R = 533 (DDR) */ pll2: st,pll@1 { compatible = "st,stm32mp1-pll"; diff --git a/fdts/stm32mp15xx-dkx.dtsi b/fdts/stm32mp15xx-dkx.dtsi index a56b237b9..3115a00dd 100644 --- a/fdts/stm32mp15xx-dkx.dtsi +++ b/fdts/stm32mp15xx-dkx.dtsi @@ -253,12 +253,6 @@ >; st,pll_vco { - pll1_vco_1300Mhz: pll1-vco-1300Mhz { - src = < CLK_PLL12_HSE >; - divmn = < 2 80 >; - frac = < 0x800 >; - }; - pll2_vco_1066Mhz: pll2-vco-1066Mhz { src = ; divmn = <2 65>; @@ -277,19 +271,6 @@ }; }; - /* VCO = 1300.0 MHz => P = 650 (CPU) */ - pll1: st,pll@0 { - compatible = "st,stm32mp1-pll"; - reg = <0>; - - st,pll = < &pll1_cfg1 >; - - pll1_cfg1: pll1_cfg1 { - st,pll_vco = < &pll1_vco_1300Mhz >; - st,pll_div_pqr = < 0 0 0 >; - }; - }; - /* VCO = 1066.0 MHz => P = 266 (AXI), Q = 533 (GPU), R = 533 (DDR) */ pll2: st,pll@1 { compatible = "st,stm32mp1-pll"; diff --git a/fdts/stm32mp15xx-osd32.dtsi b/fdts/stm32mp15xx-osd32.dtsi index 404708e14..6e27b413f 100644 --- a/fdts/stm32mp15xx-osd32.dtsi +++ b/fdts/stm32mp15xx-osd32.dtsi @@ -240,12 +240,6 @@ >; st,pll_vco { - pll1_vco_1300Mhz: pll1-vco-1300Mhz { - src = < CLK_PLL12_HSE >; - divmn = < 2 80 >; - frac = < 0x800 >; - }; - pll2_vco_1066Mhz: pll2-vco-1066Mhz { src = ; divmn = <2 65>; @@ -264,19 +258,6 @@ }; }; - /* VCO = 1300.0 MHz => P = 650 (CPU) */ - pll1: st,pll@0 { - compatible = "st,stm32mp1-pll"; - reg = <0>; - - st,pll = < &pll1_cfg1 >; - - pll1_cfg1: pll1_cfg1 { - st,pll_vco = < &pll1_vco_1300Mhz >; - st,pll_div_pqr = < 0 0 0 >; - }; - }; - /* VCO = 1066.0 MHz => P = 266 (AXI), Q = 533 (GPU), R = 533 (DDR) */ pll2: st,pll@1 { compatible = "st,stm32mp1-pll";