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fix(gpt): use DC CIGDPAPA when MTE2 is implemented
Use cache clean and invalidate of data and allocation tags by PA to PoPA maintenance instruction (dc cigdpapa) in the GPT library upon changing the PAS for a memory region. This is required to flush allocation tags when MTE2 (and above) is implemented. Signed-off-by: Olivier Deprez <olivier.deprez@arm.com> Change-Id: I4b70afb297f693b1d446839607922c47111ce063
This commit is contained in:
Olivier Deprez
parent
eb88986558
commit
62d6465213
3 changed files with 93 additions and 38 deletions
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@ -241,6 +241,7 @@ DEFINE_SYSOP_PARAM_FUNC(xpaci)
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void flush_dcache_range(uintptr_t addr, size_t size);
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void flush_dcache_to_popa_range(uintptr_t addr, size_t size);
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void flush_dcache_to_popa_range_mte2(uintptr_t addr, size_t size);
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void clean_dcache_range(uintptr_t addr, size_t size);
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void inv_dcache_range(uintptr_t addr, size_t size);
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bool is_dcache_enabled(void);
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@ -9,6 +9,7 @@
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.globl flush_dcache_range
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.globl flush_dcache_to_popa_range
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.globl flush_dcache_to_popa_range_mte2
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.globl clean_dcache_range
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.globl inv_dcache_range
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.globl dcsw_op_louis
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@ -17,6 +18,20 @@
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.globl dcsw_op_level2
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.globl dcsw_op_level3
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/* Opcodes for data cache maintenance by PA instructions. */
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/*
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* sys #6, c7, c14, #1, x0
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* DC CIPAPA, X0
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*/
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#define dc_cipapa_x0 0xd50e7e20
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/*
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* sys #6, c7, c14, #3, x0
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* DC CIDGPAPA, X0
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*/
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#define dc_cigdpapa_x0 0xd50e7ea0
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/*
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* This macro can be used for implementing various data cache operations `op`
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*/
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@ -37,6 +52,24 @@ exit_loop_\op:
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ret
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.endm
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/* op: the hexadecimal instruction opcode for the cache operation */
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.macro do_dcache_maintenance_instr op
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/* Exit early if size is zero */
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cbz x1, exit_loop_\op
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dcache_line_size x2, x3
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sub x3, x2, #1
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bic x0, x0, x3
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add x1, x1, x0
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loop_\op:
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.inst \op
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add x0, x0, x2
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cmp x0, x1
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b.lo loop_\op
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dsb osh
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exit_loop_\op:
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ret
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.endm
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.macro check_plat_can_cmo
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#if CONDITIONAL_CMO
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mov x3, x30
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@ -49,10 +82,11 @@ exit_loop_\op:
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mov x0, x2
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#endif
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.endm
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/* ------------------------------------------
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* Clean+Invalidate from base address till
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* size. 'x0' = addr, 'x1' = size
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* ------------------------------------------
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/* -------------------------------------------
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* DCache Clean+Invalidate by MVA from base
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* address till size. 'x0' = addr, 'x1' = size
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* -------------------------------------------
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*/
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func flush_dcache_range
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check_plat_can_cmo
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@ -60,8 +94,8 @@ func flush_dcache_range
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endfunc flush_dcache_range
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/* ------------------------------------------
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* Clean from base address till size.
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* 'x0' = addr, 'x1' = size
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* DCache Clean by MVA from base address till
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* size. 'x0' = addr, 'x1' = size
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* ------------------------------------------
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*/
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func clean_dcache_range
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@ -70,8 +104,8 @@ func clean_dcache_range
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endfunc clean_dcache_range
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/* ------------------------------------------
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* Invalidate from base address till
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* size. 'x0' = addr, 'x1' = size
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* DCache Invalidate by MVA from base address
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* till size. 'x0' = addr, 'x1' = size
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* ------------------------------------------
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*/
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func inv_dcache_range
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@ -79,37 +113,36 @@ func inv_dcache_range
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do_dcache_maintenance_by_mva ivac
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endfunc inv_dcache_range
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/*
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* On implementations with FEAT_MTE2,
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* Root firmware must issue DC_CIGDPAPA instead of DC_CIPAPA ,
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* in order to additionally clean and invalidate Allocation Tags
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* associated with the affected locations.
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*
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* ------------------------------------------
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* Clean+Invalidate by PA to POPA
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* from base address till size.
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* DCache Clean+Invalidate by PA to POPA from
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* base address till size.
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* 'x0' = addr, 'x1' = size
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* ------------------------------------------
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*/
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func flush_dcache_to_popa_range
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/* Exit early if size is zero */
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cbz x1, exit_loop_dc_cipapa
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check_plat_can_cmo
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dcache_line_size x2, x3
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sub x3, x2, #1
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bic x0, x0, x3
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add x1, x1, x0
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loop_dc_cipapa:
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sys #6, c7, c14, #1, x0 /* DC CIPAPA,<Xt> */
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add x0, x0, x2
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cmp x0, x1
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b.lo loop_dc_cipapa
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dsb osh
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exit_loop_dc_cipapa:
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ret
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/* dc cipapa, x0 */
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do_dcache_maintenance_instr dc_cipapa_x0
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endfunc flush_dcache_to_popa_range
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/*
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* ------------------------------------------
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* Clean+Invalidate by PA to POPA (MTE2)
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* from base address till size.
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* 'x0' = addr, 'x1' = size
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* ------------------------------------------
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* On implementations with FEAT_MTE2, Root firmware must issue
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* DC_CIGDPAPA instead of DC_CIPAPA, in order to additionally
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* clean and invalidate Allocation Tags associated with the
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* affected locations.
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*/
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func flush_dcache_to_popa_range_mte2
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check_plat_can_cmo
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/* dc cigdpapa, x0 */
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do_dcache_maintenance_instr dc_cigdpapa_x0
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endfunc flush_dcache_to_popa_range_mte2
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/* ---------------------------------------------------------------
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* Data cache operations by set/way to the level specified
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*
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@ -11,6 +11,7 @@
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#include <stdint.h>
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#include <arch.h>
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#include <arch_features.h>
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#include <arch_helpers.h>
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#include <common/debug.h>
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#include "gpt_rme_private.h"
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@ -1095,8 +1096,13 @@ int gpt_delegate_pas(uint64_t base, size_t size, unsigned int src_sec_state)
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* states, remove any data speculatively fetched into the target
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* physical address space. Issue DC CIPAPA over address range
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*/
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flush_dcache_to_popa_range(nse | base,
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GPT_PGS_ACTUAL_SIZE(gpt_config.p));
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if (is_feat_mte2_supported()) {
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flush_dcache_to_popa_range_mte2(nse | base,
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GPT_PGS_ACTUAL_SIZE(gpt_config.p));
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} else {
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flush_dcache_to_popa_range(nse | base,
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GPT_PGS_ACTUAL_SIZE(gpt_config.p));
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}
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write_gpt(&gpi_info.gpt_l1_desc, gpi_info.gpt_l1_addr,
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gpi_info.gpi_shift, gpi_info.idx, target_pas);
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@ -1107,8 +1113,13 @@ int gpt_delegate_pas(uint64_t base, size_t size, unsigned int src_sec_state)
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nse = (uint64_t)GPT_NSE_NS << GPT_NSE_SHIFT;
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flush_dcache_to_popa_range(nse | base,
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GPT_PGS_ACTUAL_SIZE(gpt_config.p));
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if (is_feat_mte2_supported()) {
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flush_dcache_to_popa_range_mte2(nse | base,
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GPT_PGS_ACTUAL_SIZE(gpt_config.p));
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} else {
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flush_dcache_to_popa_range(nse | base,
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GPT_PGS_ACTUAL_SIZE(gpt_config.p));
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}
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/* Unlock access to the L1 tables. */
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spin_unlock(&gpt_lock);
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@ -1225,8 +1236,13 @@ int gpt_undelegate_pas(uint64_t base, size_t size, unsigned int src_sec_state)
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}
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/* Ensure that the scrubbed data has made it past the PoPA */
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flush_dcache_to_popa_range(nse | base,
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GPT_PGS_ACTUAL_SIZE(gpt_config.p));
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if (is_feat_mte2_supported()) {
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flush_dcache_to_popa_range_mte2(nse | base,
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GPT_PGS_ACTUAL_SIZE(gpt_config.p));
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} else {
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flush_dcache_to_popa_range(nse | base,
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GPT_PGS_ACTUAL_SIZE(gpt_config.p));
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}
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/*
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* Remove any data loaded speculatively
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@ -1234,8 +1250,13 @@ int gpt_undelegate_pas(uint64_t base, size_t size, unsigned int src_sec_state)
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*/
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nse = (uint64_t)GPT_NSE_NS << GPT_NSE_SHIFT;
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flush_dcache_to_popa_range(nse | base,
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GPT_PGS_ACTUAL_SIZE(gpt_config.p));
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if (is_feat_mte2_supported()) {
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flush_dcache_to_popa_range_mte2(nse | base,
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GPT_PGS_ACTUAL_SIZE(gpt_config.p));
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} else {
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flush_dcache_to_popa_range(nse | base,
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GPT_PGS_ACTUAL_SIZE(gpt_config.p));
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}
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/* Clear existing GPI encoding and transition granule. */
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write_gpt(&gpi_info.gpt_l1_desc, gpi_info.gpt_l1_addr,
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