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refactor(cpufeat): align FEAT_SEL2 to new feature handling

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In ARMv8.4, the EL2 exception level got added to the secure world.
Adapt and rename the existing is_armv8_4_sel2_present() function, to
align its handling with the other CPU features.

Change-Id: If11e1942fdeb63c63f36ab9e89be810347d1a952
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
This commit is contained in:
Andre Przywara 2023-02-22 16:53:50 +00:00
parent d5384b69d1
commit 623f6140fc
5 changed files with 20 additions and 16 deletions
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13
common/feat_detect.c
View file

@ -90,16 +90,6 @@ static void read_feat_dit(void)
#endif
}
/***********************************
* Feature : FEAT_SEL2 (Secure EL2)
**********************************/
static void read_feat_sel2(void)
{
#if (ENABLE_FEAT_SEL2 == FEAT_STATE_ALWAYS)
feat_detect_panic(is_armv8_4_sel2_present(), "SEL2");
#endif
}
/************************************************
* Feature : FEAT_MTE (Memory Tagging Extension)
***********************************************/
@ -213,7 +203,8 @@ void detect_arch_features(void)
"MPAM", 1, 17);
check_feature(CTX_INCLUDE_NEVE_REGS, read_feat_nv_id_field(),
"NV2", 2, 2);
read_feat_sel2();
check_feature(ENABLE_FEAT_SEL2, read_feat_sel2_id_field(),
"SEL2", 1, 1);
check_feature(ENABLE_TRF_FOR_NS, read_feat_trf_id_field(),
"TRF", 1, 1);

18
include/arch/aarch64/arch_features.h
View file

@ -113,10 +113,22 @@ static inline unsigned int get_armv8_5_mte_support(void)
ID_AA64PFR1_EL1_MTE_MASK);
}
static inline bool is_armv8_4_sel2_present(void)
static inline unsigned int read_feat_sel2_id_field(void)
{
return ((read_id_aa64pfr0_el1() >> ID_AA64PFR0_SEL2_SHIFT) &
ID_AA64PFR0_SEL2_MASK) == 1ULL;
return ISOLATE_FIELD(read_id_aa64pfr0_el1(), ID_AA64PFR0_SEL2);
}
static inline bool is_feat_sel2_supported(void)
{
if (ENABLE_FEAT_SEL2 == FEAT_STATE_DISABLED) {
return false;
}
if (ENABLE_FEAT_SEL2 == FEAT_STATE_ALWAYS) {
return true;
}
return read_feat_sel2_id_field() != 0U;
}
static inline unsigned int read_feat_twed_id_field(void)

2
lib/el3_runtime/aarch64/context_mgmt.c
View file

@ -134,7 +134,7 @@ static void setup_secure_context(cpu_context_t *ctx, const struct entry_point_in
#endif /* CTX_INCLUDE_MTE_REGS */
/* Enable S-EL2 if the next EL is EL2 and S-EL2 is present */
if ((GET_EL(ep->spsr) == MODE_EL2) && is_armv8_4_sel2_present()) {
if ((GET_EL(ep->spsr) == MODE_EL2) && is_feat_sel2_supported()) {
if (GET_RW(ep->spsr) != MODE_RW_64) {
ERROR("S-EL2 can not be used in AArch32\n.");
panic();

1
plat/arm/board/fvp/platform.mk
View file

@ -474,6 +474,7 @@ CTX_INCLUDE_NEVE_REGS := 2
ENABLE_FEAT_CSV2_2 := 2
ENABLE_FEAT_ECV := 2
ENABLE_FEAT_PAN := 2
ENABLE_FEAT_SEL2 := 2
ENABLE_FEAT_TWED := 2
ENABLE_FEAT_VHE := 2
ENABLE_MPAM_FOR_LOWER_ELS := 2

2
services/std_svc/spmd/spmd_main.c
View file

@ -399,7 +399,7 @@ static int spmd_spmc_init(void *pm_addr)
* Check if S-EL2 is supported on this system if S-EL2
* is required for SPM
*/
if (!is_armv8_4_sel2_present()) {
if (!is_feat_sel2_supported()) {
WARN("SPM Core run time S-EL2 is not supported.\n");
return -EINVAL;
}