Merge changes I6ac59693,Ib0e4e5cf into integration

* changes:
  refactor(tc): reorder config variable defines
  refactor(tc): move DTB to start of DRAM
This commit is contained in:
Manish V Badarkhe 2024-02-28 15:17:59 +01:00 committed by TrustedFirmware Code Review
commit 61ee40b1c9
3 changed files with 42 additions and 56 deletions

View file

@ -1,10 +1,11 @@
/*
* Copyright (c) 2020-2021, Arm Limited. All rights reserved.
* Copyright (c) 2020-2024, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <common/tbbr/tbbr_img_def.h>
#include <platform_def.h>
/dts-v1/;
@ -25,8 +26,8 @@
};
hw-config {
load-address = <0x0 0x83000000>;
max-size = <0x8000>;
load-address = <0x0 PLAT_HW_CONFIG_DTB_BASE>;
max-size = <PLAT_HW_CONFIG_DTB_SIZE>;
id = <HW_CONFIG_ID>;
};
};

View file

@ -28,6 +28,11 @@
* - Region to load secure partitions
*
*
* 0x8000_0000 ------------------ TC_NS_DRAM1_BASE
* | DTB |
* | (32K) |
* 0x8000_8000 ------------------
* | ... |
* 0xf8a0_0000 ------------------ TC_NS_FWU_BASE
* | FWU shmem |
* | (4MB) |
@ -79,7 +84,7 @@
TC_TZC_DRAM1_SIZE, \
MT_MEMORY | MT_RW | MT_SECURE)
#define PLAT_HW_CONFIG_DTB_BASE ULL(0x83000000)
#define PLAT_HW_CONFIG_DTB_BASE TC_NS_DRAM1_BASE
#define PLAT_HW_CONFIG_DTB_SIZE ULL(0x8000)
#define PLAT_DTB_DRAM_NS MAP_REGION_FLAT( \

View file

@ -13,6 +13,38 @@ TC_SCMI_PD_CTRL_EN := 1
# IOMMU: Enable the use of system or individual MMUs
TC_IOMMU_EN := 1
# System setup
CSS_USE_SCMI_SDS_DRIVER := 1
HW_ASSISTED_COHERENCY := 1
USE_COHERENT_MEM := 0
GIC_ENABLE_V4_EXTN := 1
GICV3_SUPPORT_GIC600 := 1
override NEED_BL2U := no
override ARM_PLAT_MT := 1
# CPU setup
ARM_ARCH_MINOR := 7
BRANCH_PROTECTION := 1
ENABLE_FEAT_MPAM := 1 # default is 2, optimise
ENABLE_SVE_FOR_NS := 2 # to show we use it
ENABLE_SVE_FOR_SWD := 1
ENABLE_TRBE_FOR_NS := 1
ENABLE_SYS_REG_TRACE_FOR_NS := 1
ENABLE_FEAT_AMU := 1
ENABLE_AMU_FCONF := 1
ENABLE_AMU_AUXILIARY_COUNTERS := 1
ENABLE_MPMM := 1
ENABLE_MPMM_FCONF := 1
CTX_INCLUDE_AARCH32_REGS := 0
ifeq (${SPD},spmd)
SPMD_SPM_AT_SEL2 := 1
ENABLE_FEAT_MTE := 1
CTX_INCLUDE_PAUTH_REGS := 1
endif
ifneq ($(shell expr $(TARGET_PLATFORM) \<= 1), 0)
$(warning Platform ${PLAT}$(TARGET_PLATFORM) is deprecated. \
Some of the features might not work as expected)
@ -36,41 +68,6 @@ $(eval $(call add_defines, \
CSS_LOAD_SCP_IMAGES := 1
CSS_USE_SCMI_SDS_DRIVER := 1
ENABLE_FEAT_RAS := 1
SDEI_SUPPORT := 0
EL3_EXCEPTION_HANDLING := 0
HANDLE_EA_EL3_FIRST_NS := 0
# System coherency is managed in hardware
HW_ASSISTED_COHERENCY := 1
# When building for systems with hardware-assisted coherency, there's no need to
# use USE_COHERENT_MEM. Require that USE_COHERENT_MEM must be set to 0 too.
USE_COHERENT_MEM := 0
GIC_ENABLE_V4_EXTN := 1
# GIC-600 configuration
GICV3_SUPPORT_GIC600 := 1
# Enable SVE
ENABLE_SVE_FOR_NS := 2
ENABLE_SVE_FOR_SWD := 1
# enable trace buffer control registers access to NS by default
ENABLE_TRBE_FOR_NS := 1
# enable trace system registers access to NS by default
ENABLE_SYS_REG_TRACE_FOR_NS := 1
# enable trace filter control registers access to NS by default
ENABLE_TRF_FOR_NS := 1
# Include GICv3 driver files
include drivers/arm/gic/v3/gicv3.mk
@ -78,10 +75,6 @@ ENT_GIC_SOURCES := ${GICV3_SOURCES} \
plat/common/plat_gicv3.c \
plat/arm/common/arm_gicv3.c
override NEED_BL2U := no
override ARM_PLAT_MT := 1
TC_BASE = plat/arm/board/tc
PLAT_INCLUDES += -I${TC_BASE}/include/ \
@ -174,19 +167,6 @@ $(eval TC_HW_CONFIG := ${BUILD_PLAT}/$(patsubst %.dts,%.dtb,$(TC_HW_CONFIG_DTS))
# Add the HW_CONFIG to FIP and specify the same to certtool
$(eval $(call TOOL_ADD_PAYLOAD,${TC_HW_CONFIG},--hw-config,${TC_HW_CONFIG}))
override CTX_INCLUDE_AARCH32_REGS := 0
override CTX_INCLUDE_PAUTH_REGS := 1
override ENABLE_SPE_FOR_NS := 0
override ENABLE_FEAT_AMU := 1
ENABLE_AMU_AUXILIARY_COUNTERS := 1
ENABLE_AMU_FCONF := 1
ENABLE_MPMM := 1
ENABLE_MPMM_FCONF := 1
# Include Measured Boot makefile before any Crypto library makefile.
# Crypto library makefile may need default definitions of Measured Boot build
# flags present in Measured Boot makefile.