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feat(st-clock): add STM32MP2 clock driver
This driver manages the clocks on STM32MP2 platforms. It uses a dedicated RCC (Reset and Clock Control) peripheral. Change-Id: I6ba2173e73222269a2dfca4c6897229276a150c0 Signed-off-by: Yann Gautier <yann.gautier@st.com> Signed-off-by: Gabriel Fernandez <gabriel.fernandez@st.com>
This commit is contained in:
Gabriel Fernandez
Yann Gautier
parent
85229098ab
commit
615f31fe40
5 changed files with 2422 additions and 17 deletions
2357
drivers/st/clk/clk-stm32mp2.c
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2357
drivers/st/clk/clk-stm32mp2.c
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@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2023, STMicroelectronics - All Rights Reserved
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* Copyright (c) 2023-2024, STMicroelectronics - All Rights Reserved
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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@ -426,7 +426,7 @@
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#define RCC_USB2CFGR U(0x7FC)
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#define RCC_USB2PHY1CFGR U(0x800)
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#define RCC_USB2PHY2CFGR U(0x804)
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#define RCC_USB3DRDCFGR U(0x808)
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#define RCC_USB3DRCFGR U(0x808)
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#define RCC_USB3PCIEPHYCFGR U(0x80C)
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#define RCC_PCIECFGR U(0x810)
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#define RCC_USBTCCFGR U(0x814)
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@ -459,7 +459,6 @@
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#define RCC_IWDG5CFGR U(0x898)
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#define RCC_WWDG1CFGR U(0x89C)
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#define RCC_WWDG2CFGR U(0x8A0)
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#define RCC_BUSPERFMCFGR U(0x8A4)
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#define RCC_VREFCFGR U(0x8A8)
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#define RCC_TMPSENSCFGR U(0x8AC)
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#define RCC_CRCCFGR U(0x8B4)
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@ -2352,11 +2351,13 @@
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/* RCC_C1SREQSETR register fields */
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#define RCC_C1SREQSETR_STPREQ_P0 BIT(0)
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#define RCC_C1SREQSETR_STPREQ_P1 BIT(1)
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#define RCC_C1SREQSETR_STPREQ_MASK GENMASK_32(1, 0)
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#define RCC_C1SREQSETR_ESLPREQ BIT(16)
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/* RCC_C1SREQCLRR register fields */
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#define RCC_C1SREQCLRR_STPREQ_P0 BIT(0)
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#define RCC_C1SREQCLRR_STPREQ_P1 BIT(1)
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#define RCC_C1SREQCLRR_STPREQ_MASK GENMASK_32(1, 0)
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#define RCC_C1SREQCLRR_ESLPREQ BIT(16)
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/* RCC_CPUBOOTCR register fields */
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@ -2401,12 +2402,12 @@
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#define RCC_BDCR_LSEDRV_WIDTH 2
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/* RCC_D3DCR register fields */
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#define RCC_D3DCR_CSION BIT(0)
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#define RCC_D3DCR_CSIKERON BIT(1)
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#define RCC_D3DCR_CSIRDY BIT(2)
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#define RCC_D3DCR_MSION BIT(0)
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#define RCC_D3DCR_MSIKERON BIT(1)
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#define RCC_D3DCR_MSIRDY BIT(2)
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#define RCC_D3DCR_D3PERCKSEL_MASK GENMASK_32(17, 16)
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#define RCC_D3DCR_D3PERCKSEL_SHIFT 16
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#define RCC_D3DCR_CSIRDY_BIT 2
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#define RCC_D3DCR_MSIRDY_BIT 2
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/* RCC_D3DSR register fields */
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#define RCC_D3DSR_D3STATE_MASK GENMASK_32(1, 0)
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@ -3458,11 +3459,11 @@
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#define RCC_USB2PHYxCFGR_USB2PHY1STPEN BIT(4)
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#define RCC_USB2PHYxCFGR_USB2PHY1CKREFSEL BIT(15)
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/* RCC_USB3DRDCFGR register fields */
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#define RCC_USB3DRDCFGR_USB3DRDRST BIT(0)
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#define RCC_USB3DRDCFGR_USB3DRDEN BIT(1)
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#define RCC_USB3DRDCFGR_USB3DRDLPEN BIT(2)
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#define RCC_USB3DRDCFGR_USB3DRDSTPEN BIT(4)
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/* RCC_USB3DRCFGR register fields */
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#define RCC_USB3DRCFGR_USB3DRRST BIT(0)
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#define RCC_USB3DRCFGR_USB3DREN BIT(1)
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#define RCC_USB3DRCFGR_USB3DRLPEN BIT(2)
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#define RCC_USB3DRCFGR_USB3DRSTPEN BIT(4)
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/* RCC_USB3PCIEPHYCFGR register fields */
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#define RCC_USB3PCIEPHYCFGR_USB3PCIEPHYRST BIT(0)
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@ -3647,11 +3648,6 @@
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#define RCC_WWDG2CFGR_WWDG2LPEN BIT(2)
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#define RCC_WWDG2CFGR_WWDG2AMEN BIT(3)
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/* RCC_BUSPERFMCFGR register fields */
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#define RCC_BUSPERFMCFGR_BUSPERFMRST BIT(0)
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#define RCC_BUSPERFMCFGR_BUSPERFMEN BIT(1)
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#define RCC_BUSPERFMCFGR_BUSPERFMLPEN BIT(2)
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/* RCC_VREFCFGR register fields */
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#define RCC_VREFCFGR_VREFRST BIT(0)
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#define RCC_VREFCFGR_VREFEN BIT(1)
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44
include/drivers/st/stm32mp2_clk.h
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44
include/drivers/st/stm32mp2_clk.h
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@ -0,0 +1,44 @@
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/*
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* Copyright (C) 2024, STMicroelectronics - All Rights Reserved
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef STM32MP2_CLK_H
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#define STM32MP2_CLK_H
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#include <platform_def.h>
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enum stm32mp_osc_id {
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_HSI,
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_HSE,
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_CSI,
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_LSI,
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_LSE,
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_I2S_CKIN,
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_SPDIF_SYMB,
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NB_OSC,
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_UNKNOWN_OSC_ID = 0xFF
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};
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extern const char *stm32mp_osc_node_label[NB_OSC];
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enum pll_cfg {
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FBDIV,
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REFDIV,
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POSTDIV1,
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POSTDIV2,
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PLLCFG_NB
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};
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enum pll_csg {
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DIVVAL,
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SPREAD,
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DOWNSPREAD,
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PLLCSG_NB
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};
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int stm32mp2_clk_init(void);
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int stm32mp2_pll1_disable(void);
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#endif /* STM32MP2_CLK_H */
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@ -53,6 +53,9 @@ PLAT_BL_COMMON_SOURCES += plat/st/stm32mp2/${ARCH}/stm32mp2_helper.S
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PLAT_BL_COMMON_SOURCES += drivers/st/bsec/bsec3.c
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PLAT_BL_COMMON_SOURCES += drivers/st/clk/clk-stm32-core.c \
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drivers/st/clk/clk-stm32mp2.c
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BL2_SOURCES += plat/st/stm32mp2/plat_bl2_mem_params_desc.c
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BL2_SOURCES += plat/st/stm32mp2/bl2_plat_setup.c
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@ -292,6 +292,11 @@ static inline uintptr_t tamp_bkpr(uint32_t idx)
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#define STGEN_BASE U(0x48080000)
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#define SYSCFG_BASE U(0x44230000)
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/*******************************************************************************
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* STM32MP CA35SSC
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******************************************************************************/
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#define A35SSC_BASE U(0x48800000)
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/*******************************************************************************
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* REGULATORS
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******************************************************************************/
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