Merge changes from topic "imx8mq_build_fix" into integration

* changes:
  fix(imx8m): fix imx8mq build break
  fix(imx8mq): fix imx8mq build break due to hab

plat/imx/common/include/imx_sip_svc.h

@@ -72,6 +72,8 @@ static inline int dram_dvfs_handler(uint32_t smc_fid, void *handle,
 	SMC_RET1(handle, SMC_UNK);
 }
 #endif
+int imx_hab_handler(uint32_t smc_fid, u_register_t x1,
+	u_register_t x2, u_register_t x3, u_register_t x4);
 #endif
 #if defined(PLAT_imx8mm) || defined(PLAT_imx8mn) || defined(PLAT_imx8mp)
 int dram_dvfs_handler(uint32_t smc_fid, void *handle,

plat/imx/imx8m/imx8mq/imx8mq_bl31_setup.c

@@ -52,6 +52,8 @@ static const mmap_region_t imx_mmap[] = {
 	MAP_REGION_FLAT(IMX_GIC_BASE, IMX_GIC_SIZE, MT_DEVICE | MT_RW), /* GIC map */
 	MAP_REGION_FLAT(IMX_DDRPHY_BASE, IMX_DDR_IPS_SIZE, MT_DEVICE | MT_RW), /* DDRMIX map */
 	MAP_REGION_FLAT(IMX_DRAM_BASE, IMX_DRAM_SIZE, MT_MEMORY | MT_RW | MT_NS),
+	MAP_REGION_FLAT(IMX_CAAM_RAM_BASE, IMX_CAAM_RAM_SIZE, MT_MEMORY | MT_RW), /* CAMM RAM */
+	MAP_REGION_FLAT(IMX_NS_OCRAM_BASE, IMX_NS_OCRAM_SIZE, MT_MEMORY | MT_RW), /* NS OCRAM */
 	{0},
 };
 
@@ -207,13 +209,19 @@ void bl31_plat_arch_setup(void)
 				MT_MEMORY | MT_RW | MT_SECURE),
 		MAP_REGION_FLAT(BL_CODE_BASE, BL_CODE_END - BL_CODE_BASE,
 				MT_MEMORY | MT_RO | MT_SECURE),
+#if SEPARATE_NOBITS_REGION
+		MAP_REGION_FLAT(BL_NOBITS_BASE, BL_NOBITS_END - BL_NOBITS_BASE,
+				MT_RW_DATA | MT_SECURE),
+#endif
 #if USE_COHERENT_MEM
 		MAP_REGION_FLAT(BL_COHERENT_RAM_BASE,
 				BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE,
 				MT_DEVICE | MT_RW | MT_SECURE),
 #endif
+#if defined(SPD_opteed) || defined(SPD_trusty)
 		/* Map TEE memory */
 		MAP_REGION_FLAT(BL32_BASE, BL32_SIZE, MT_MEMORY | MT_RW),
+#endif
 		{0},
 	};
 

plat/imx/imx8m/imx8mq/include/platform_def.h

@@ -10,7 +10,7 @@
 #define PLATFORM_LINKER_FORMAT		"elf64-littleaarch64"
 #define PLATFORM_LINKER_ARCH		aarch64
 
-#define PLATFORM_STACK_SIZE		0x800
+#define PLATFORM_STACK_SIZE		0xb00
 #define CACHE_WRITEBACK_GRANULE		64
 
 #define PLAT_PRIMARY_CPU		U(0x0)
@@ -37,6 +37,12 @@
 #define BL31_SIZE			SZ_64K
 #define BL31_LIMIT			(BL31_BASE + BL31_SIZE)
 
+#define OCRAM_S_BASE			U(0x180000)
+#define OCRAM_S_SIZE			SZ_32K
+#define OCRAM_S_LIMIT			(OCRAM_S_BASE + OCRAM_S_SIZE)
+#define BL31_NOBITS_BASE		OCRAM_S_BASE
+#define BL31_NOBITS_LIMIT		(BL31_NOBITS_BASE + SZ_32K)
+
 /* non-secure uboot base */
 #ifndef PLAT_NS_IMAGE_OFFSET
 #define PLAT_NS_IMAGE_OFFSET		U(0x40200000)
@@ -54,7 +60,7 @@
 #define MAX_XLAT_TABLES			5
 #define MAX_MMAP_REGIONS		15
 #else
-#define MAX_XLAT_TABLES			4
+#define MAX_XLAT_TABLES			3
 #define MAX_MMAP_REGIONS		14
 #endif
 
@@ -93,7 +99,10 @@
 #define IMX_DDR_IPS_SIZE		U(0x1800000)
 #define IMX_DRAM_BASE			U(0x40000000)
 #define IMX_DRAM_SIZE			U(0xc0000000)
-
+#define IMX_NS_OCRAM_BASE		U(0x900000)
+#define IMX_NS_OCRAM_SIZE		U(0x20000)
+#define IMX_CAAM_RAM_BASE		U(0x100000)
+#define IMX_CAAM_RAM_SIZE		U(0x10000)
 #define IMX_ROM_BASE			U(0x00000000)
 #define IMX_ROM_SIZE			U(0x20000)
 
@@ -141,10 +150,6 @@
 #define GPR_TZASC_EN			BIT(0)
 #define GPR_TZASC_EN_LOCK		BIT(16)
 
-#define OCRAM_S_BASE			U(0x00180000)
-#define OCRAM_S_SIZE			U(0x8000)
-#define OCRAM_S_LIMIT			(OCRAM_S_BASE + OCRAM_S_SIZE)
-
 #define COUNTER_FREQUENCY		8333333 /* 25MHz / 3 */
 
 #define IMX_WDOG_B_RESET

plat/imx/imx8m/imx8mq/platform.mk

@@ -29,6 +29,7 @@ BL31_SOURCES		+=	plat/imx/common/imx8_helpers.S			\
 				plat/imx/imx8m/imx8mq/imx8mq_bl31_setup.c	\
 				plat/imx/imx8m/imx8mq/imx8mq_psci.c		\
 				plat/imx/imx8m/gpc_common.c			\
+				plat/imx/imx8m/imx_hab.c			\
 				plat/imx/imx8m/imx_aipstz.c			\
 				plat/imx/imx8m/imx8m_caam.c			\
 				plat/imx/imx8m/imx8m_ccm.c			\
@@ -63,6 +64,8 @@ ifeq (${IMX_DRAM_RETENTION},1)
 BL31_SOURCES		+=	${IMX_DRAM_SOURCES}
 endif
 
+SEPARATE_NOBITS_REGION  :=        1
+
 ifneq (${PRELOADED_BL33_BASE},)
 $(eval $(call add_define_val,PLAT_NS_IMAGE_OFFSET,${PRELOADED_BL33_BASE}))
 endif