mirror of
https://github.com/ARM-software/arm-trusted-firmware.git
synced 2025-04-08 13:53:54 +00:00
1b65be5943
Fix the build break for i.MX8MQ to make it boot with basic function enabled. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Change-Id: I2ff7976e3fb7960d6876d26fe0b4a78e51219ae2
272 lines
7.2 KiB
C
272 lines
7.2 KiB
C
/*
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* Copyright (c) 2018-2023, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <assert.h>
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#include <stdbool.h>
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#include <platform_def.h>
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#include <arch_helpers.h>
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#include <common/bl_common.h>
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#include <common/debug.h>
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#include <context.h>
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#include <drivers/arm/tzc380.h>
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#include <drivers/console.h>
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#include <drivers/generic_delay_timer.h>
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#include <lib/el3_runtime/context_mgmt.h>
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#include <lib/mmio.h>
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#include <lib/xlat_tables/xlat_tables_v2.h>
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#include <plat/common/platform.h>
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#include <dram.h>
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#include <gpc.h>
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#include <imx_aipstz.h>
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#include <imx_uart.h>
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#include <imx8m_caam.h>
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#include <imx8m_ccm.h>
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#include <plat_imx8.h>
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#define TRUSTY_PARAMS_LEN_BYTES (4096*2)
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/*
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* Avoid the pointer dereference of the canonical mmio_read_8() implementation.
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* This prevents the compiler from mis-interpreting the MMIO access as an
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* illegal memory access to a very low address (the IMX ROM is mapped at 0).
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*/
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static uint8_t mmio_read_8_ldrb(uintptr_t address)
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{
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uint8_t reg;
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__asm__ volatile ("ldrb %w0, [%1]" : "=r" (reg) : "r" (address));
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return reg;
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}
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static const mmap_region_t imx_mmap[] = {
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MAP_REGION_FLAT(GPV_BASE, GPV_SIZE, MT_DEVICE | MT_RW), /* GPV map */
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MAP_REGION_FLAT(IMX_ROM_BASE, IMX_ROM_SIZE, MT_MEMORY | MT_RO), /* ROM map */
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MAP_REGION_FLAT(IMX_AIPS_BASE, IMX_AIPS_SIZE, MT_DEVICE | MT_RW), /* AIPS map */
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MAP_REGION_FLAT(IMX_GIC_BASE, IMX_GIC_SIZE, MT_DEVICE | MT_RW), /* GIC map */
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MAP_REGION_FLAT(IMX_DDRPHY_BASE, IMX_DDR_IPS_SIZE, MT_DEVICE | MT_RW), /* DDRMIX map */
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MAP_REGION_FLAT(IMX_DRAM_BASE, IMX_DRAM_SIZE, MT_MEMORY | MT_RW | MT_NS),
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MAP_REGION_FLAT(IMX_CAAM_RAM_BASE, IMX_CAAM_RAM_SIZE, MT_MEMORY | MT_RW), /* CAMM RAM */
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MAP_REGION_FLAT(IMX_NS_OCRAM_BASE, IMX_NS_OCRAM_SIZE, MT_MEMORY | MT_RW), /* NS OCRAM */
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{0},
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};
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static const struct aipstz_cfg aipstz[] = {
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{AIPSTZ1_BASE, 0x77777777, 0x77777777, .opacr = {0x0, 0x0, 0x0, 0x0, 0x0}, },
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{AIPSTZ2_BASE, 0x77777777, 0x77777777, .opacr = {0x0, 0x0, 0x0, 0x0, 0x0}, },
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{AIPSTZ3_BASE, 0x77777777, 0x77777777, .opacr = {0x0, 0x0, 0x0, 0x0, 0x0}, },
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{AIPSTZ4_BASE, 0x77777777, 0x77777777, .opacr = {0x0, 0x0, 0x0, 0x0, 0x0}, },
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{0},
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};
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static entry_point_info_t bl32_image_ep_info;
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static entry_point_info_t bl33_image_ep_info;
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static uint32_t imx_soc_revision;
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int imx_soc_info_handler(uint32_t smc_fid, u_register_t x1, u_register_t x2,
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u_register_t x3)
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{
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return imx_soc_revision;
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}
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#define ANAMIX_DIGPROG 0x6c
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#define ROM_SOC_INFO_A0 0x800
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#define ROM_SOC_INFO_B0 0x83C
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#define OCOTP_SOC_INFO_B1 0x40
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static void imx8mq_soc_info_init(void)
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{
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uint32_t rom_version;
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uint32_t ocotp_val;
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imx_soc_revision = mmio_read_32(IMX_ANAMIX_BASE + ANAMIX_DIGPROG);
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rom_version = mmio_read_8_ldrb(IMX_ROM_BASE + ROM_SOC_INFO_A0);
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if (rom_version == 0x10)
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return;
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rom_version = mmio_read_8_ldrb(IMX_ROM_BASE + ROM_SOC_INFO_B0);
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if (rom_version == 0x20) {
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imx_soc_revision &= ~0xff;
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imx_soc_revision |= rom_version;
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return;
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}
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/* 0xff0055aa is magic number for B1 */
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ocotp_val = mmio_read_32(IMX_OCOTP_BASE + OCOTP_SOC_INFO_B1);
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if (ocotp_val == 0xff0055aa) {
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imx_soc_revision &= ~0xff;
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if (rom_version == 0x22) {
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imx_soc_revision |= 0x22;
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} else {
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imx_soc_revision |= 0x21;
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}
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return;
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}
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}
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/* get SPSR for BL33 entry */
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static uint32_t get_spsr_for_bl33_entry(void)
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{
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unsigned long el_status;
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unsigned long mode;
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uint32_t spsr;
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/* figure out what mode we enter the non-secure world */
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el_status = read_id_aa64pfr0_el1() >> ID_AA64PFR0_EL2_SHIFT;
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el_status &= ID_AA64PFR0_ELX_MASK;
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mode = (el_status) ? MODE_EL2 : MODE_EL1;
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spsr = SPSR_64(mode, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS);
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return spsr;
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}
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static void bl31_tz380_setup(void)
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{
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unsigned int val;
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val = mmio_read_32(IMX_IOMUX_GPR_BASE + IOMUXC_GPR10);
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if ((val & GPR_TZASC_EN) != GPR_TZASC_EN)
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return;
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tzc380_init(IMX_TZASC_BASE);
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/*
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* Need to substact offset 0x40000000 from CPU address when
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* programming tzasc region for i.mx8mq. Enable 1G-5G S/NS RW
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*/
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tzc380_configure_region(0, 0x00000000, TZC_ATTR_REGION_SIZE(TZC_REGION_SIZE_4G) |
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TZC_ATTR_REGION_EN_MASK | TZC_ATTR_SP_ALL);
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}
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void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
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u_register_t arg2, u_register_t arg3)
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{
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unsigned int console_base = IMX_BOOT_UART_BASE;
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static console_t console;
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int i;
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/* enable CSU NS access permission */
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for (i = 0; i < 64; i++) {
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mmio_write_32(IMX_CSU_BASE + i * 4, 0xffffffff);
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}
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imx_aipstz_init(aipstz);
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if (console_base == 0U) {
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console_base = imx8m_uart_get_base();
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}
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console_imx_uart_register(console_base, IMX_BOOT_UART_CLK_IN_HZ,
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IMX_CONSOLE_BAUDRATE, &console);
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/* This console is only used for boot stage */
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console_set_scope(&console, CONSOLE_FLAG_BOOT);
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imx8m_caam_init();
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/*
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* tell BL3-1 where the non-secure software image is located
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* and the entry state information.
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*/
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bl33_image_ep_info.pc = PLAT_NS_IMAGE_OFFSET;
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bl33_image_ep_info.spsr = get_spsr_for_bl33_entry();
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SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE);
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#if defined(SPD_opteed) || defined(SPD_trusty)
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/* Populate entry point information for BL32 */
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SET_PARAM_HEAD(&bl32_image_ep_info, PARAM_EP, VERSION_1, 0);
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SET_SECURITY_STATE(bl32_image_ep_info.h.attr, SECURE);
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bl32_image_ep_info.pc = BL32_BASE;
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bl32_image_ep_info.spsr = 0;
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/* Pass TEE base and size to bl33 */
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bl33_image_ep_info.args.arg1 = BL32_BASE;
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bl33_image_ep_info.args.arg2 = BL32_SIZE;
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#ifdef SPD_trusty
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bl32_image_ep_info.args.arg0 = BL32_SIZE;
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bl32_image_ep_info.args.arg1 = BL32_BASE;
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#else
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/* Make sure memory is clean */
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mmio_write_32(BL32_FDT_OVERLAY_ADDR, 0);
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bl33_image_ep_info.args.arg3 = BL32_FDT_OVERLAY_ADDR;
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bl32_image_ep_info.args.arg3 = BL32_FDT_OVERLAY_ADDR;
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#endif
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#endif
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bl31_tz380_setup();
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}
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void bl31_plat_arch_setup(void)
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{
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const mmap_region_t bl_regions[] = {
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MAP_REGION_FLAT(BL31_START, BL31_SIZE,
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MT_MEMORY | MT_RW | MT_SECURE),
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MAP_REGION_FLAT(BL_CODE_BASE, BL_CODE_END - BL_CODE_BASE,
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MT_MEMORY | MT_RO | MT_SECURE),
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#if SEPARATE_NOBITS_REGION
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MAP_REGION_FLAT(BL_NOBITS_BASE, BL_NOBITS_END - BL_NOBITS_BASE,
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MT_RW_DATA | MT_SECURE),
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#endif
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#if USE_COHERENT_MEM
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MAP_REGION_FLAT(BL_COHERENT_RAM_BASE,
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BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE,
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MT_DEVICE | MT_RW | MT_SECURE),
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#endif
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#if defined(SPD_opteed) || defined(SPD_trusty)
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/* Map TEE memory */
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MAP_REGION_FLAT(BL32_BASE, BL32_SIZE, MT_MEMORY | MT_RW),
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#endif
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{0},
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};
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setup_page_tables(bl_regions, imx_mmap);
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/* enable the MMU */
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enable_mmu_el3(0);
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}
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void bl31_platform_setup(void)
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{
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generic_delay_timer_init();
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/* init the GICv3 cpu and distributor interface */
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plat_gic_driver_init();
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plat_gic_init();
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/* determine SOC revision for erratas */
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imx8mq_soc_info_init();
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/* gpc init */
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imx_gpc_init();
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dram_info_init(SAVED_DRAM_TIMING_BASE);
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}
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entry_point_info_t *bl31_plat_get_next_image_ep_info(unsigned int type)
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{
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if (type == NON_SECURE)
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return &bl33_image_ep_info;
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if (type == SECURE)
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return &bl32_image_ep_info;
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return NULL;
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}
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unsigned int plat_get_syscnt_freq2(void)
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{
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return COUNTER_FREQUENCY;
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}
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#ifdef SPD_trusty
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void plat_trusty_set_boot_args(aapcs64_params_t *args)
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{
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args->arg0 = BL32_SIZE;
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args->arg1 = BL32_BASE;
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args->arg2 = TRUSTY_PARAMS_LEN_BYTES;
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}
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#endif
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