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fix(security): add CVE-2024-7881 mitigation to Cortex-X925

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This patch mitigates CVE-2024-7881 [1] by setting CPUACTLR6_EL1[41] to 1
for Cortex-X925 CPU.

[1]: https://developer.arm.com/Arm%20Security%20Center/Arm%20CPU%20Vulnerability%20CVE-2024-7881

Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Change-Id: I53e72e4dbc8937cea3c344a5ba04664c50a0792a
This commit is contained in:
Arvind Ram Prakash 2024-09-06 12:19:59 -05:00
parent 6ce6acac91
commit 520c2207b9
2 changed files with 18 additions and 2 deletions
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7
include/lib/cpus/aarch64/cortex_x925.h
View file

@ -1,5 +1,5 @@
/* /*
* Copyright (c) 2023-2024, Arm Limited. All rights reserved. * Copyright (c) 2023-2025, Arm Limited. All rights reserved.
* *
* SPDX-License-Identifier: BSD-3-Clause * SPDX-License-Identifier: BSD-3-Clause
*/ */
@ -21,4 +21,9 @@
#define CORTEX_X925_CPUPWRCTLR_EL1 S3_0_C15_C2_7 #define CORTEX_X925_CPUPWRCTLR_EL1 S3_0_C15_C2_7
#define CORTEX_X925_CPUPWRCTLR_EL1_CORE_PWRDN_BIT U(1) #define CORTEX_X925_CPUPWRCTLR_EL1_CORE_PWRDN_BIT U(1)
/*******************************************************************************
* CPU Auxiliary control register 6 specific definitions
******************************************************************************/
#define CORTEX_X925_CPUACTLR6_EL1 S3_0_C15_C8_1
#endif /* CORTEX_X925_H */ #endif /* CORTEX_X925_H */

13
lib/cpus/aarch64/cortex_x925.S
View file

@ -1,5 +1,5 @@
/* /*
* Copyright (c) 2023-2024, Arm Limited. All rights reserved. * Copyright (c) 2023-2025, Arm Limited. All rights reserved.
* *
* SPDX-License-Identifier: BSD-3-Clause * SPDX-License-Identifier: BSD-3-Clause
*/ */
@ -28,6 +28,17 @@ workaround_reset_end cortex_x925, CVE(2024, 5660)
check_erratum_ls cortex_x925, CVE(2024, 5660), CPU_REV(0, 1) check_erratum_ls cortex_x925, CVE(2024, 5660), CPU_REV(0, 1)
workaround_reset_start cortex_x925, CVE(2024, 7881), WORKAROUND_CVE_2024_7881
/* ---------------------------------
* Sets BIT41 of CPUACTLR6_EL1 which
* disables L1 Data cache prefetcher
* ---------------------------------
*/
sysreg_bit_set CORTEX_X925_CPUACTLR6_EL1, BIT(41)
workaround_reset_end cortex_x925, CVE(2024, 7881)
check_erratum_chosen cortex_x925, CVE(2024, 7881), WORKAROUND_CVE_2024_7881
cpu_reset_func_start cortex_x925 cpu_reset_func_start cortex_x925
/* Disable speculative loads */ /* Disable speculative loads */
msr SSBS, xzr msr SSBS, xzr