mirror of
https://github.com/ARM-software/arm-trusted-firmware.git
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Merge "feat(ethos-n)!: add support for SMMU streams" into integration
This commit is contained in:
Joanna Farley
TrustedFirmware Code Review
commit
4e7983b71d
8 changed files with 475 additions and 107 deletions
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@ -92,7 +92,7 @@ Arm Platform Build Options
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SBROM library must be specified via ``CCSBROM_LIB_PATH`` flag.
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- ``ARM_ETHOSN_NPU_DRIVER``: boolean option to enable a SiP service that can
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configure an Arm Ethos-N NPU. To use this service the target platform's
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configure an Arm® Ethos™-N NPU. To use this service the target platform's
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``HW_CONFIG`` must include the device tree nodes for the NPU. Currently, only
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the Arm Juno platform has this included in its ``HW_CONFIG`` and the platform
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only loads the ``HW_CONFIG`` in AArch64 builds. Default is 0.
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@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2021, Arm Limited. All rights reserved.
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* Copyright (c) 2021-2022, Arm Limited. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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@ -12,18 +12,17 @@
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#include <drivers/arm/ethosn.h>
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#include <drivers/delay_timer.h>
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#include <lib/mmio.h>
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#include <lib/utils_def.h>
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#include <plat/arm/common/fconf_ethosn_getter.h>
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/*
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* Number of Arm Ethos-N NPU (NPU) cores available for a
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* particular parent device
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* Number of Arm(R) Ethos(TM)-N NPU (NPU) devices available
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*/
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#define ETHOSN_NUM_CORES \
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FCONF_GET_PROPERTY(hw_config, ethosn_config, num_cores)
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#define ETHOSN_NUM_DEVICES \
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FCONF_GET_PROPERTY(hw_config, ethosn_config, num_devices)
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/* Address to an NPU core */
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#define ETHOSN_CORE_ADDR(core_idx) \
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FCONF_GET_PROPERTY(hw_config, ethosn_core_addr, core_idx)
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#define ETHOSN_GET_DEVICE(dev_idx) \
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FCONF_GET_PROPERTY(hw_config, ethosn_device, dev_idx)
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/* NPU core sec registry address */
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#define ETHOSN_CORE_SEC_REG(core_addr, reg_offset) \
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@ -40,9 +39,6 @@
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#define SEC_SECCTLR_REG U(0x0010)
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#define SEC_SECCTLR_VAL U(0x3)
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#define SEC_DEL_MMUSID_REG U(0x2008)
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#define SEC_DEL_MMUSID_VAL U(0x3FFFF)
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#define SEC_DEL_ADDR_EXT_REG U(0x201C)
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#define SEC_DEL_ADDR_EXT_VAL U(0x15)
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@ -50,17 +46,63 @@
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#define SEC_SYSCTRL0_SOFT_RESET U(3U << 29)
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#define SEC_SYSCTRL0_HARD_RESET U(1U << 31)
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static bool ethosn_is_core_addr_valid(uintptr_t core_addr)
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#define SEC_MMUSID_REG_BASE U(0x3008)
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#define SEC_MMUSID_OFFSET U(0x1000)
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static bool ethosn_get_device_and_core(uintptr_t core_addr,
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const struct ethosn_device_t **dev_match,
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const struct ethosn_core_t **core_match)
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{
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for (uint32_t core_idx = 0U; core_idx < ETHOSN_NUM_CORES; core_idx++) {
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if (ETHOSN_CORE_ADDR(core_idx) == core_addr) {
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return true;
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uint32_t dev_idx;
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uint32_t core_idx;
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for (dev_idx = 0U; dev_idx < ETHOSN_NUM_DEVICES; ++dev_idx) {
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const struct ethosn_device_t *dev = ETHOSN_GET_DEVICE(dev_idx);
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for (core_idx = 0U; core_idx < dev->num_cores; ++core_idx) {
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const struct ethosn_core_t *core = &(dev->cores[core_idx]);
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if (core->addr == core_addr) {
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*dev_match = dev;
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*core_match = core;
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return true;
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}
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}
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}
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WARN("ETHOSN: Unknown core address given to SMC call.\n");
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return false;
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}
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static void ethosn_configure_smmu_streams(const struct ethosn_device_t *device,
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const struct ethosn_core_t *core,
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uint32_t asset_alloc_idx)
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{
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const struct ethosn_main_allocator_t *main_alloc =
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&(core->main_allocator);
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const struct ethosn_asset_allocator_t *asset_alloc =
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&(device->asset_allocators[asset_alloc_idx]);
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const uint32_t streams[9] = {
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main_alloc->firmware.stream_id,
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main_alloc->working_data.stream_id,
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asset_alloc->command_stream.stream_id,
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0U, /* Not used*/
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main_alloc->firmware.stream_id,
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asset_alloc->weight_data.stream_id,
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asset_alloc->buffer_data.stream_id,
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asset_alloc->intermediate_data.stream_id,
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asset_alloc->buffer_data.stream_id
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};
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size_t i;
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for (i = 0U; i < ARRAY_SIZE(streams); ++i) {
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const uintptr_t reg_addr = SEC_MMUSID_REG_BASE +
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(SEC_MMUSID_OFFSET * i);
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mmio_write_32(ETHOSN_CORE_SEC_REG(core->addr, reg_addr),
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streams[i]);
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}
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}
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static void ethosn_delegate_to_ns(uintptr_t core_addr)
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{
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mmio_setbits_32(ETHOSN_CORE_SEC_REG(core_addr, SEC_SECCTLR_REG),
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@ -69,9 +111,6 @@ static void ethosn_delegate_to_ns(uintptr_t core_addr)
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mmio_setbits_32(ETHOSN_CORE_SEC_REG(core_addr, SEC_DEL_REG),
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SEC_DEL_VAL);
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mmio_setbits_32(ETHOSN_CORE_SEC_REG(core_addr, SEC_DEL_MMUSID_REG),
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SEC_DEL_MMUSID_VAL);
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mmio_setbits_32(ETHOSN_CORE_SEC_REG(core_addr, SEC_DEL_ADDR_EXT_REG),
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SEC_DEL_ADDR_EXT_VAL);
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}
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@ -112,7 +151,7 @@ static bool ethosn_reset(uintptr_t core_addr, int hard_reset)
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uintptr_t ethosn_smc_handler(uint32_t smc_fid,
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u_register_t core_addr,
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u_register_t x2,
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u_register_t asset_alloc_idx,
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u_register_t x3,
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u_register_t x4,
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void *cookie,
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@ -120,6 +159,8 @@ uintptr_t ethosn_smc_handler(uint32_t smc_fid,
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u_register_t flags)
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{
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int hard_reset = 0;
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const struct ethosn_device_t *device = NULL;
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const struct ethosn_core_t *core = NULL;
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const uint32_t fid = smc_fid & FUNCID_NUM_MASK;
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/* Only SiP fast calls are expected */
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@ -131,12 +172,14 @@ uintptr_t ethosn_smc_handler(uint32_t smc_fid,
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/* Truncate parameters to 32-bits for SMC32 */
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if (GET_SMC_CC(smc_fid) == SMC_32) {
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core_addr &= 0xFFFFFFFF;
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x2 &= 0xFFFFFFFF;
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asset_alloc_idx &= 0xFFFFFFFF;
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x3 &= 0xFFFFFFFF;
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x4 &= 0xFFFFFFFF;
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}
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if (!is_ethosn_fid(smc_fid)) {
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if (!is_ethosn_fid(smc_fid) ||
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(fid < ETHOSN_FNUM_VERSION || fid > ETHOSN_FNUM_SOFT_RESET)) {
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WARN("ETHOSN: Unknown SMC call: 0x%x\n", smc_fid);
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SMC_RET1(handle, SMC_UNK);
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}
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@ -146,25 +189,41 @@ uintptr_t ethosn_smc_handler(uint32_t smc_fid,
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SMC_RET2(handle, ETHOSN_VERSION_MAJOR, ETHOSN_VERSION_MINOR);
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}
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if (!ethosn_is_core_addr_valid(core_addr)) {
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WARN("ETHOSN: Unknown core address given to SMC call.\n");
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if (!ethosn_get_device_and_core(core_addr, &device, &core)) {
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SMC_RET1(handle, ETHOSN_UNKNOWN_CORE_ADDRESS);
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}
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/* Commands that require a valid addr */
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/* Commands that require a valid core address */
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switch (fid) {
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case ETHOSN_FNUM_IS_SEC:
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SMC_RET1(handle, ethosn_is_sec(core_addr));
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SMC_RET1(handle, ethosn_is_sec(core->addr));
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}
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if (!device->has_reserved_memory &&
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asset_alloc_idx >= device->num_allocators) {
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WARN("ETHOSN: Unknown asset allocator index given to SMC call.\n");
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SMC_RET1(handle, ETHOSN_UNKNOWN_ALLOCATOR_IDX);
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}
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/* Commands that require a valid device, core and asset allocator */
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switch (fid) {
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case ETHOSN_FNUM_HARD_RESET:
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hard_reset = 1;
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/* Fallthrough */
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case ETHOSN_FNUM_SOFT_RESET:
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if (!ethosn_reset(core_addr, hard_reset)) {
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if (!ethosn_reset(core->addr, hard_reset)) {
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SMC_RET1(handle, ETHOSN_FAILURE);
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}
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ethosn_delegate_to_ns(core_addr);
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if (!device->has_reserved_memory) {
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ethosn_configure_smmu_streams(device, core,
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asset_alloc_idx);
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}
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ethosn_delegate_to_ns(core->addr);
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SMC_RET1(handle, ETHOSN_SUCCESS);
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default:
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WARN("ETHOSN: Unimplemented SMC call: 0x%x\n", fid);
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SMC_RET1(handle, SMC_UNK);
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}
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}
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@ -1,12 +1,13 @@
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/*
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* Copyright (c) 2021, Arm Limited. All rights reserved.
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* Copyright (c) 2021-2022, Arm Limited. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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/*
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* For examples of multi-core and multi-device NPU, refer to the examples given in the
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* Arm Ethos-N NPU driver stack.
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* This device tree is only an example and some properties have been omitted.
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*
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* Refer to the Arm(R) Ethos(TM)-N driver stack for complete device tree examples.
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* https://github.com/ARM-software/ethos-n-driver-stack
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*/
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@ -14,14 +15,62 @@
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#address-cells = <2>;
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#size-cells = <2>;
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ethosn0: ethosn@6f300000 {
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compatible = "ethosn";
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reg = <0 0x6f300000 0 0x00100000>;
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smmu_ethosn0: iommu@6f400000 {
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compatible = "arm,smmu-v3";
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reg = <0 0x6f400000 0 0x80000>;
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status = "okay";
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core0 {
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compatible = "ethosn-core";
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status = "okay";
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};
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/* msi-parent omitted */
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#iommu-cells = <0x1>;
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};
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ethosn0: ethosn@6f300000 {
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compatible = "ethosn";
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reg = <0 0x6f300000 0 0x00100000>;
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status = "okay";
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core0 {
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compatible = "ethosn-core";
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status = "okay";
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main_allocator {
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compatible = "ethosn-main_allocator";
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status = "okay";
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firmware {
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compatible = "ethosn-memory";
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iommus = <&smmu_ethosn0 0>;
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};
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working_data {
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compatible = "ethosn-memory";
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iommus = <&smmu_ethosn0 1>;
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};
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};
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};
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asset_allocator {
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compatible = "ethosn-asset_allocator";
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status = "okay";
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command_stream {
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compatible = "ethosn-memory";
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iommus = <&smmu_ethosn0 2>;
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};
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weight_data {
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compatible = "ethosn-memory";
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iommus = <&smmu_ethosn0 3>;
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};
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buffer_data {
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compatible = "ethosn-memory";
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iommus = <&smmu_ethosn0 4>;
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};
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intermediate_data {
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compatible = "ethosn-memory";
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iommus = <&smmu_ethosn0 5>;
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};
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};
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};
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};
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@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2021, Arm Limited. All rights reserved.
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* Copyright (c) 2021-2022, Arm Limited. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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@ -38,7 +38,7 @@
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#define is_ethosn_fid(_fid) (((_fid) & ETHOSN_FID_MASK) == ETHOSN_FID_VALUE)
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/* Service version */
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#define ETHOSN_VERSION_MAJOR U(1)
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#define ETHOSN_VERSION_MAJOR U(2)
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#define ETHOSN_VERSION_MINOR U(0)
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/* Return codes for function calls */
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@ -48,10 +48,11 @@
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/* -3 Reserved for INVALID_PARAMETER */
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#define ETHOSN_FAILURE -4
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#define ETHOSN_UNKNOWN_CORE_ADDRESS -5
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#define ETHOSN_UNKNOWN_ALLOCATOR_IDX -6
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uintptr_t ethosn_smc_handler(uint32_t smc_fid,
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u_register_t core_addr,
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u_register_t x2,
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u_register_t asset_alloc_idx,
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u_register_t x3,
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u_register_t x4,
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void *cookie,
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@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2016-2019,2021, ARM Limited and Contributors. All rights reserved.
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* Copyright (c) 2016-2019,2021-2022, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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@ -26,7 +26,7 @@
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/* DEBUGFS_SMC_64 0xC2000030U */
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/*
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* Arm Ethos-N NPU SiP SMC function IDs
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* Arm(R) Ethos(TM)-N NPU SiP SMC function IDs
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* 0xC2000050-0xC200005F
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* 0x82000050-0x8200005F
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*/
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@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2021, Arm Limited. All rights reserved.
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* Copyright (c) 2021-2022, Arm Limited. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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@ -8,27 +8,52 @@
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#define FCONF_ETHOSN_GETTER_H
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#include <assert.h>
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#include <stdbool.h>
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#include <lib/fconf/fconf.h>
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#define hw_config__ethosn_config_getter(prop) ethosn_config.prop
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#define hw_config__ethosn_core_addr_getter(idx) __extension__ ({ \
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assert(idx < ethosn_config.num_cores); \
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ethosn_config.core[idx].addr; \
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#define hw_config__ethosn_device_getter(dev_idx) __extension__ ({ \
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assert(dev_idx < ethosn_config.num_devices); \
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ðosn_config.devices[dev_idx]; \
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})
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#define ETHOSN_STATUS_DISABLED U(0)
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#define ETHOSN_STATUS_ENABLED U(1)
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#define ETHOSN_DEV_NUM_MAX U(2)
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#define ETHOSN_DEV_CORE_NUM_MAX U(8)
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#define ETHOSN_DEV_ASSET_ALLOCATOR_NUM_MAX U(16)
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#define ETHOSN_CORE_NUM_MAX U(64)
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struct ethosn_allocator_t {
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uint32_t stream_id;
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};
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struct ethosn_main_allocator_t {
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struct ethosn_allocator_t firmware;
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struct ethosn_allocator_t working_data;
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};
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struct ethosn_asset_allocator_t {
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struct ethosn_allocator_t command_stream;
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struct ethosn_allocator_t weight_data;
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struct ethosn_allocator_t buffer_data;
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struct ethosn_allocator_t intermediate_data;
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};
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struct ethosn_core_t {
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uint64_t addr;
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struct ethosn_main_allocator_t main_allocator;
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};
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struct ethosn_device_t {
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bool has_reserved_memory;
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uint32_t num_cores;
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struct ethosn_core_t cores[ETHOSN_DEV_CORE_NUM_MAX];
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uint32_t num_allocators;
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struct ethosn_asset_allocator_t asset_allocators[ETHOSN_DEV_ASSET_ALLOCATOR_NUM_MAX];
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};
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struct ethosn_config_t {
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uint32_t num_cores;
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struct ethosn_core_t core[ETHOSN_CORE_NUM_MAX];
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uint32_t num_devices;
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struct ethosn_device_t devices[ETHOSN_DEV_NUM_MAX];
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};
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int fconf_populate_arm_ethosn(uintptr_t config);
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|
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@ -114,7 +114,7 @@ ifeq (${ARM_LINUX_KERNEL_AS_BL33},1)
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endif
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endif
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# Arm Ethos-N NPU SiP service
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# Arm(R) Ethos(TM)-N NPU SiP service
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ARM_ETHOSN_NPU_DRIVER := 0
|
||||
$(eval $(call assert_boolean,ARM_ETHOSN_NPU_DRIVER))
|
||||
$(eval $(call add_define,ARM_ETHOSN_NPU_DRIVER))
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
/*
|
||||
* Copyright (c) 2021, Arm Limited. All rights reserved.
|
||||
* Copyright (c) 2021-2022, Arm Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
|
@ -12,107 +12,341 @@
|
|||
#include <libfdt.h>
|
||||
#include <plat/arm/common/fconf_ethosn_getter.h>
|
||||
|
||||
struct ethosn_config_t ethosn_config = {.num_cores = 0};
|
||||
struct ethosn_config_t ethosn_config = {0};
|
||||
|
||||
static uint8_t fdt_node_get_status(const void *fdt, int node)
|
||||
struct ethosn_sub_allocator_t {
|
||||
const char *name;
|
||||
size_t name_len;
|
||||
uint32_t stream_id;
|
||||
};
|
||||
|
||||
static bool fdt_node_is_enabled(const void *fdt, int node)
|
||||
{
|
||||
int len;
|
||||
uint8_t status = ETHOSN_STATUS_DISABLED;
|
||||
const char *node_status;
|
||||
|
||||
node_status = fdt_getprop(fdt, node, "status", &len);
|
||||
if (node_status == NULL ||
|
||||
(len == 5 && /* Includes null character */
|
||||
strncmp(node_status, "okay", 4U) == 0)) {
|
||||
status = ETHOSN_STATUS_ENABLED;
|
||||
return true;
|
||||
}
|
||||
|
||||
return status;
|
||||
return false;
|
||||
}
|
||||
|
||||
static bool fdt_node_has_reserved_memory(const void *fdt, int dev_node)
|
||||
{
|
||||
return fdt_get_property(fdt, dev_node, "memory-region", NULL) != NULL;
|
||||
}
|
||||
|
||||
static int fdt_node_get_iommus_stream_id(const void *fdt, int node, uint32_t *stream_id)
|
||||
{
|
||||
int err;
|
||||
uint32_t iommus_array[2] = {0U};
|
||||
|
||||
err = fdt_read_uint32_array(fdt, node, "iommus", 2U, iommus_array);
|
||||
if (err) {
|
||||
return err;
|
||||
}
|
||||
|
||||
*stream_id = iommus_array[1];
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int fdt_node_populate_sub_allocators(const void *fdt,
|
||||
int alloc_node,
|
||||
struct ethosn_sub_allocator_t *sub_allocators,
|
||||
size_t num_allocs)
|
||||
{
|
||||
int sub_node;
|
||||
size_t i;
|
||||
int err = -FDT_ERR_NOTFOUND;
|
||||
uint32_t found_sub_allocators = 0U;
|
||||
|
||||
fdt_for_each_subnode(sub_node, fdt, alloc_node) {
|
||||
const char *node_name;
|
||||
|
||||
if (!fdt_node_is_enabled(fdt, sub_node)) {
|
||||
/* Ignore disabled node */
|
||||
continue;
|
||||
}
|
||||
|
||||
if (fdt_node_check_compatible(fdt, sub_node, "ethosn-memory") != 0) {
|
||||
continue;
|
||||
}
|
||||
|
||||
node_name = fdt_get_name(fdt, sub_node, NULL);
|
||||
for (i = 0U; i < num_allocs; ++i) {
|
||||
if (strncmp(node_name, sub_allocators[i].name,
|
||||
sub_allocators[i].name_len) != 0) {
|
||||
continue;
|
||||
}
|
||||
|
||||
err = fdt_node_get_iommus_stream_id(fdt, sub_node,
|
||||
&sub_allocators[i].stream_id);
|
||||
if (err) {
|
||||
ERROR("FCONF: Failed to get stream ID from sub-allocator %s\n",
|
||||
node_name);
|
||||
return err;
|
||||
}
|
||||
|
||||
++found_sub_allocators;
|
||||
/* Nothing more to do for this node */
|
||||
break;
|
||||
}
|
||||
|
||||
/* Check that at least one of the sub-allocators matched */
|
||||
if (i == num_allocs) {
|
||||
ERROR("FCONF: Unknown sub-allocator %s\n", node_name);
|
||||
return -FDT_ERR_BADSTRUCTURE;
|
||||
}
|
||||
}
|
||||
|
||||
if ((sub_node < 0) && (sub_node != -FDT_ERR_NOTFOUND)) {
|
||||
ERROR("FCONF: Failed to parse sub-allocators\n");
|
||||
return -FDT_ERR_BADSTRUCTURE;
|
||||
}
|
||||
|
||||
if (err == -FDT_ERR_NOTFOUND) {
|
||||
ERROR("FCONF: No matching sub-allocator found\n");
|
||||
return err;
|
||||
}
|
||||
|
||||
if (found_sub_allocators != num_allocs) {
|
||||
ERROR("FCONF: Not all sub-allocators were found\n");
|
||||
return -FDT_ERR_BADSTRUCTURE;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int fdt_node_populate_main_allocator(const void *fdt,
|
||||
int alloc_node,
|
||||
struct ethosn_main_allocator_t *allocator)
|
||||
{
|
||||
int err;
|
||||
struct ethosn_sub_allocator_t sub_allocators[] = {
|
||||
{.name = "firmware", .name_len = 8U},
|
||||
{.name = "working_data", .name_len = 12U}
|
||||
};
|
||||
|
||||
err = fdt_node_populate_sub_allocators(fdt, alloc_node, sub_allocators,
|
||||
ARRAY_SIZE(sub_allocators));
|
||||
if (err) {
|
||||
return err;
|
||||
}
|
||||
|
||||
allocator->firmware.stream_id = sub_allocators[0].stream_id;
|
||||
allocator->working_data.stream_id = sub_allocators[1].stream_id;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int fdt_node_populate_asset_allocator(const void *fdt,
|
||||
int alloc_node,
|
||||
struct ethosn_asset_allocator_t *allocator)
|
||||
{
|
||||
int err;
|
||||
struct ethosn_sub_allocator_t sub_allocators[] = {
|
||||
{.name = "command_stream", .name_len = 14U},
|
||||
{.name = "weight_data", .name_len = 11U},
|
||||
{.name = "buffer_data", .name_len = 11U},
|
||||
{.name = "intermediate_data", .name_len = 17U}
|
||||
};
|
||||
|
||||
err = fdt_node_populate_sub_allocators(fdt, alloc_node, sub_allocators,
|
||||
ARRAY_SIZE(sub_allocators));
|
||||
if (err) {
|
||||
return err;
|
||||
}
|
||||
|
||||
|
||||
allocator->command_stream.stream_id = sub_allocators[0].stream_id;
|
||||
allocator->weight_data.stream_id = sub_allocators[1].stream_id;
|
||||
allocator->buffer_data.stream_id = sub_allocators[2].stream_id;
|
||||
allocator->intermediate_data.stream_id = sub_allocators[3].stream_id;
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int fdt_node_populate_core(const void *fdt,
|
||||
int device_node,
|
||||
int core_node,
|
||||
bool has_reserved_memory,
|
||||
uint32_t core_index,
|
||||
struct ethosn_core_t *core)
|
||||
{
|
||||
int err;
|
||||
int sub_node;
|
||||
uintptr_t core_addr;
|
||||
|
||||
err = fdt_get_reg_props_by_index(fdt, device_node, core_index,
|
||||
&core_addr, NULL);
|
||||
if (err < 0) {
|
||||
ERROR("FCONF: Failed to read reg property for NPU core %u\n",
|
||||
core_index);
|
||||
return err;
|
||||
}
|
||||
|
||||
err = -FDT_ERR_NOTFOUND;
|
||||
fdt_for_each_subnode(sub_node, fdt, core_node) {
|
||||
|
||||
if (!fdt_node_is_enabled(fdt, sub_node)) {
|
||||
continue;
|
||||
}
|
||||
|
||||
if (fdt_node_check_compatible(fdt,
|
||||
sub_node,
|
||||
"ethosn-main_allocator") != 0) {
|
||||
continue;
|
||||
}
|
||||
|
||||
if (has_reserved_memory) {
|
||||
ERROR("FCONF: Main allocator not supported when using reserved memory\n");
|
||||
return -FDT_ERR_BADSTRUCTURE;
|
||||
}
|
||||
|
||||
if (err != -FDT_ERR_NOTFOUND) {
|
||||
ERROR("FCONF: NPU core 0x%lx has more than one main allocator\n",
|
||||
core_addr);
|
||||
return -FDT_ERR_BADSTRUCTURE;
|
||||
}
|
||||
|
||||
err = fdt_node_populate_main_allocator(fdt, sub_node, &core->main_allocator);
|
||||
if (err) {
|
||||
ERROR("FCONF: Failed to parse main allocator for NPU core 0x%lx\n",
|
||||
core_addr);
|
||||
return err;
|
||||
}
|
||||
}
|
||||
|
||||
if ((sub_node < 0) && (sub_node != -FDT_ERR_NOTFOUND)) {
|
||||
ERROR("FCONF: Failed to parse core sub nodes\n");
|
||||
return -FDT_ERR_BADSTRUCTURE;
|
||||
}
|
||||
|
||||
if (!has_reserved_memory && err) {
|
||||
ERROR("FCONF: Main allocator not found for NPU core 0x%lx\n",
|
||||
core_addr);
|
||||
return err;
|
||||
}
|
||||
|
||||
core->addr = core_addr;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int fconf_populate_ethosn_config(uintptr_t config)
|
||||
{
|
||||
int ethosn_node;
|
||||
uint32_t dev_count = 0U;
|
||||
const void *hw_conf_dtb = (const void *)config;
|
||||
|
||||
/* Find offset to node with 'ethosn' compatible property */
|
||||
INFO("Probing Arm Ethos-N NPU\n");
|
||||
uint32_t total_core_count = 0U;
|
||||
INFO("Probing Arm(R) Ethos(TM)-N NPU\n");
|
||||
|
||||
fdt_for_each_compatible_node(hw_conf_dtb, ethosn_node, "ethosn") {
|
||||
struct ethosn_device_t *dev = ðosn_config.devices[dev_count];
|
||||
uint32_t dev_asset_alloc_count = 0U;
|
||||
uint32_t dev_core_count = 0U;
|
||||
bool has_reserved_memory;
|
||||
int sub_node;
|
||||
uint8_t ethosn_status;
|
||||
uint32_t device_core_count = 0U;
|
||||
|
||||
/* If the Arm Ethos-N NPU is disabled the core check can be skipped */
|
||||
ethosn_status = fdt_node_get_status(hw_conf_dtb, ethosn_node);
|
||||
if (ethosn_status == ETHOSN_STATUS_DISABLED) {
|
||||
if (!fdt_node_is_enabled(hw_conf_dtb, ethosn_node)) {
|
||||
continue;
|
||||
}
|
||||
|
||||
if (dev_count >= ETHOSN_DEV_NUM_MAX) {
|
||||
ERROR("FCONF: Reached max number of NPUs\n");
|
||||
return -FDT_ERR_BADSTRUCTURE;
|
||||
}
|
||||
|
||||
has_reserved_memory = fdt_node_has_reserved_memory(hw_conf_dtb, ethosn_node);
|
||||
fdt_for_each_subnode(sub_node, hw_conf_dtb, ethosn_node) {
|
||||
int err;
|
||||
uintptr_t core_addr;
|
||||
uint8_t core_status;
|
||||
|
||||
if (total_core_count >= ETHOSN_CORE_NUM_MAX) {
|
||||
ERROR("FCONF: Reached max number of Arm Ethos-N NPU cores\n");
|
||||
return -FDT_ERR_BADSTRUCTURE;
|
||||
if (!fdt_node_is_enabled(hw_conf_dtb, sub_node)) {
|
||||
/* Ignore disabled sub node */
|
||||
continue;
|
||||
}
|
||||
|
||||
/* Check that the sub node is "ethosn-core" compatible */
|
||||
if (fdt_node_check_compatible(hw_conf_dtb,
|
||||
sub_node,
|
||||
"ethosn-core") != 0) {
|
||||
/* Ignore incompatible sub node */
|
||||
continue;
|
||||
}
|
||||
"ethosn-core") == 0) {
|
||||
|
||||
core_status = fdt_node_get_status(hw_conf_dtb, sub_node);
|
||||
if (core_status == ETHOSN_STATUS_DISABLED) {
|
||||
continue;
|
||||
}
|
||||
if (dev_core_count >= ETHOSN_DEV_CORE_NUM_MAX) {
|
||||
ERROR("FCONF: Reached max number of NPU cores for NPU %u\n",
|
||||
dev_count);
|
||||
return -FDT_ERR_BADSTRUCTURE;
|
||||
}
|
||||
|
||||
err = fdt_get_reg_props_by_index(hw_conf_dtb,
|
||||
ethosn_node,
|
||||
device_core_count,
|
||||
&core_addr,
|
||||
NULL);
|
||||
if (err < 0) {
|
||||
ERROR(
|
||||
"FCONF: Failed to read reg property for Arm Ethos-N NPU core %u\n",
|
||||
device_core_count);
|
||||
return err;
|
||||
}
|
||||
err = fdt_node_populate_core(hw_conf_dtb,
|
||||
ethosn_node,
|
||||
sub_node,
|
||||
has_reserved_memory,
|
||||
dev_core_count,
|
||||
&(dev->cores[dev_core_count]));
|
||||
if (err) {
|
||||
return err;
|
||||
}
|
||||
++dev_core_count;
|
||||
} else if (fdt_node_check_compatible(hw_conf_dtb,
|
||||
sub_node,
|
||||
"ethosn-asset_allocator") == 0) {
|
||||
|
||||
INFO("NPU core probed at address 0x%lx\n", core_addr);
|
||||
ethosn_config.core[total_core_count].addr = core_addr;
|
||||
total_core_count++;
|
||||
device_core_count++;
|
||||
if (dev_asset_alloc_count >=
|
||||
ETHOSN_DEV_ASSET_ALLOCATOR_NUM_MAX) {
|
||||
ERROR("FCONF: Reached max number of asset allocators for NPU %u\n",
|
||||
dev_count);
|
||||
return -FDT_ERR_BADSTRUCTURE;
|
||||
}
|
||||
|
||||
if (has_reserved_memory) {
|
||||
ERROR("FCONF: Asset allocator not supported when using reserved memory\n");
|
||||
return -FDT_ERR_BADSTRUCTURE;
|
||||
}
|
||||
|
||||
err = fdt_node_populate_asset_allocator(hw_conf_dtb,
|
||||
sub_node,
|
||||
&(dev->asset_allocators[dev_asset_alloc_count]));
|
||||
if (err) {
|
||||
ERROR("FCONF: Failed to parse asset allocator for NPU %u\n",
|
||||
dev_count);
|
||||
return err;
|
||||
}
|
||||
++dev_asset_alloc_count;
|
||||
}
|
||||
}
|
||||
|
||||
if ((sub_node < 0) && (sub_node != -FDT_ERR_NOTFOUND)) {
|
||||
ERROR("FCONF: Failed to parse sub nodes\n");
|
||||
ERROR("FCONF: Failed to parse sub nodes for NPU %u\n",
|
||||
dev_count);
|
||||
return -FDT_ERR_BADSTRUCTURE;
|
||||
}
|
||||
|
||||
if (device_core_count == 0U) {
|
||||
ERROR(
|
||||
"FCONF: Enabled Arm Ethos-N NPU device must have at least one enabled core\n");
|
||||
if (dev_core_count == 0U) {
|
||||
ERROR("FCONF: NPU %u must have at least one enabled core\n",
|
||||
dev_count);
|
||||
return -FDT_ERR_BADSTRUCTURE;
|
||||
}
|
||||
|
||||
if (!has_reserved_memory && dev_asset_alloc_count == 0U) {
|
||||
ERROR("FCONF: NPU %u must have at least one asset allocator\n",
|
||||
dev_count);
|
||||
return -FDT_ERR_BADSTRUCTURE;
|
||||
}
|
||||
|
||||
dev->num_cores = dev_core_count;
|
||||
dev->num_allocators = dev_asset_alloc_count;
|
||||
dev->has_reserved_memory = has_reserved_memory;
|
||||
++dev_count;
|
||||
}
|
||||
|
||||
if (total_core_count == 0U) {
|
||||
if (dev_count == 0U) {
|
||||
ERROR("FCONF: Can't find 'ethosn' compatible node in dtb\n");
|
||||
return -FDT_ERR_BADSTRUCTURE;
|
||||
}
|
||||
|
||||
ethosn_config.num_cores = total_core_count;
|
||||
|
||||
INFO("%d NPU core%s probed\n",
|
||||
ethosn_config.num_cores,
|
||||
ethosn_config.num_cores > 1 ? "s" : "");
|
||||
ethosn_config.num_devices = dev_count;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue