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fix(errata): workaround for Cortex-X2 erratum 2216384

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Cortex-X2 erratum 2216384 is a Cat B erratum that applies to
revisions r0p0, r1p0 and r2p0 of CPU. It is fixed in r2p1.
The workaround is to set CPUACTLR5_EL1[17] to 1'b1 followed by
applying an instruction patching sequence.

SDEN can be found here:
https://developer.arm.com/documentation/SDEN1775100/latest

Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>
Change-Id: I3c216161678887c06a28c59644e784e0c7d37bab
This commit is contained in:
Bipin Ravi 2022-02-06 01:29:31 -06:00
parent c060b5337a
commit 4dff7594f9
4 changed files with 58 additions and 0 deletions
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4
docs/design/cpu-specific-build-macros.rst
View file

@ -462,6 +462,10 @@ For Cortex-X2, the following errata build flags are defined :
Cortex-X2 CPU. This needs to be enabled only for revisions r0p0, r1p0 and
r2p0 of the CPU, it is fixed in r2p1.
- ``ERRATA_X2_2216384``: This applies errata 2216384 workaround to
Cortex-X2 CPU. This needs to be enabled only for revisions r0p0, r1p0 and
r2p0 of the CPU, it is fixed in r2p1.
DSU Errata Workarounds
----------------------

1
include/lib/cpus/aarch64/cortex_x2.h
View file

@ -34,6 +34,7 @@
* CPU Auxiliary Control Register 5 definitions
******************************************************************************/
#define CORTEX_X2_CPUACTLR5_EL1 S3_0_C15_C8_0
#define CORTEX_X2_CPUACTLR5_EL1_BIT_17 (ULL(1) << 17)
/*******************************************************************************
* CPU Implementation Specific Selected Instruction registers

44
lib/cpus/aarch64/cortex_x2.S
View file

@ -184,6 +184,44 @@ func check_errata_2081180
b cpu_rev_var_ls
endfunc check_errata_2081180
/* --------------------------------------------------
* Errata Workaround for Cortex X2 Errata 2216384.
* This applies to revisions r0p0, r1p0, and r2p0
* and is fixed in r2p1.
* x0: variant[4:7] and revision[0:3] of current cpu.
* Shall clobber: x0, x1, x17
* --------------------------------------------------
*/
func errata_x2_2216384_wa
/* Check workaround compatibility. */
mov x17, x30
bl check_errata_2216384
cbz x0, 1f
mrs x1, CORTEX_X2_CPUACTLR5_EL1
orr x1, x1, CORTEX_X2_CPUACTLR5_EL1_BIT_17
msr CORTEX_X2_CPUACTLR5_EL1, x1
/* Apply instruction patching sequence */
ldr x0, =0x5
msr CORTEX_X2_IMP_CPUPSELR_EL3, x0
ldr x0, =0x10F600E000
msr CORTEX_X2_IMP_CPUPOR_EL3, x0
ldr x0, =0x10FF80E000
msr CORTEX_X2_IMP_CPUPMR_EL3, x0
ldr x0, =0x80000000003FF
msr CORTEX_X2_IMP_CPUPCR_EL3, x0
isb
1:
ret x17
endfunc errata_x2_2216384_wa
func check_errata_2216384
/* Applies to r0p0 - r2p0 */
mov x1, #0x20
b cpu_rev_var_ls
endfunc check_errata_2216384
/* ----------------------------------------------------
* HW will do the cache maintenance while powering down
* ----------------------------------------------------
@ -219,6 +257,7 @@ func cortex_x2_errata_report
report_errata ERRATA_X2_2083908, cortex_x2, 2083908
report_errata ERRATA_X2_2017096, cortex_x2, 2017096
report_errata ERRATA_X2_2081180, cortex_x2, 2081180
report_errata ERRATA_X2_2216384, cortex_x2, 2216384
ldp x8, x30, [sp], #16
ret
@ -261,6 +300,11 @@ func cortex_x2_reset_func
bl errata_x2_2081180_wa
#endif
#if ERRATA_X2_2216384
mov x0, x18
bl errata_x2_2216384_wa
#endif
ret x19
endfunc cortex_x2_reset_func

9
lib/cpus/cpu-ops.mk
View file

@ -517,6 +517,11 @@ ERRATA_X2_2017096 ?=0
# r2p1.
ERRATA_X2_2081180 ?=0
# Flag to apply erratum 2216384 workaround during reset. This erratum applies
# only to revisions r0p0, r1p0 and r2p0 of the Cortex-X2 cpu, it is fixed in
# r2p1.
ERRATA_X2_2216384 ?=0
# Flag to apply DSU erratum 798953. This erratum applies to DSUs revision r0p0.
# Applying the workaround results in higher DSU power consumption on idle.
ERRATA_DSU_798953 ?=0
@ -962,6 +967,10 @@ $(eval $(call add_define,ERRATA_X2_2017096))
$(eval $(call assert_boolean,ERRATA_X2_2081180))
$(eval $(call add_define,ERRATA_X2_2081180))
# Process ERRATA_X2_2216384 flag
$(eval $(call assert_boolean,ERRATA_X2_2216384))
$(eval $(call add_define,ERRATA_X2_2216384))
# Process ERRATA_DSU_798953 flag
$(eval $(call assert_boolean,ERRATA_DSU_798953))
$(eval $(call add_define,ERRATA_DSU_798953))