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feat(s32g274a): enable sdhc clock

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The uSDHC module clock must be enabled to use the SD/eMMC storage from
where the BL2 is expected to load images for the next boot stages.

Change-Id: Ib1cc7d5dda7a4283a29716f5b3d776048bd5b7ba
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>
This commit is contained in:
Ghennadi Procopciuc 2025-01-28 12:06:16 +02:00
parent cf6d73d4c3
commit 47b3a8251f
1 changed files with 37 additions and 1 deletions

38
drivers/nxp/clk/s32cc/s32cc_early_clks.c
View file

@ -1,5 +1,5 @@
/*
* Copyright 2024 NXP
* Copyright 2024-2025 NXP
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -18,6 +18,8 @@
#define S32CC_PERIPH_PLL_PHI3_FREQ UART_CLOCK_HZ
#define S32CC_DDR_PLL_VCO_FREQ (1600U * MHZ)
#define S32CC_DDR_PLL_PHI0_FREQ (800U * MHZ)
#define S32CC_PERIPH_DFS_PHI3_FREQ (800U * MHZ)
#define S32CC_USDHC_FREQ (400U * MHZ)
static int setup_fxosc(void)
{
@ -180,6 +182,35 @@ static int enable_ddr_clk(void)
return ret;
}
static int enable_usdhc_clk(void)
{
int ret;
ret = clk_set_parent(S32CC_CLK_MC_CGM0_MUX14,
S32CC_CLK_PERIPH_PLL_DFS3);
if (ret != 0) {
return ret;
}
ret = clk_set_rate(S32CC_CLK_PERIPH_PLL_DFS3,
S32CC_PERIPH_DFS_PHI3_FREQ, NULL);
if (ret != 0) {
return ret;
}
ret = clk_set_rate(S32CC_CLK_USDHC, S32CC_USDHC_FREQ, NULL);
if (ret != 0) {
return ret;
}
ret = clk_enable(S32CC_CLK_USDHC);
if (ret != 0) {
return ret;
}
return ret;
}
int s32cc_init_core_clocks(void)
{
int ret;
@ -241,5 +272,10 @@ int s32cc_init_early_clks(void)
return ret;
}
ret = enable_usdhc_clk();
if (ret != 0) {
return ret;
}
return ret;
}