From 47b3a8251f1b7948360714254f8ec22b0e23875e Mon Sep 17 00:00:00 2001 From: Ghennadi Procopciuc Date: Tue, 28 Jan 2025 12:06:16 +0200 Subject: [PATCH] feat(s32g274a): enable sdhc clock The uSDHC module clock must be enabled to use the SD/eMMC storage from where the BL2 is expected to load images for the next boot stages. Change-Id: Ib1cc7d5dda7a4283a29716f5b3d776048bd5b7ba Signed-off-by: Ghennadi Procopciuc --- drivers/nxp/clk/s32cc/s32cc_early_clks.c | 38 +++++++++++++++++++++++- 1 file changed, 37 insertions(+), 1 deletion(-) diff --git a/drivers/nxp/clk/s32cc/s32cc_early_clks.c b/drivers/nxp/clk/s32cc/s32cc_early_clks.c index f001568f4..92182a0b7 100644 --- a/drivers/nxp/clk/s32cc/s32cc_early_clks.c +++ b/drivers/nxp/clk/s32cc/s32cc_early_clks.c @@ -1,5 +1,5 @@ /* - * Copyright 2024 NXP + * Copyright 2024-2025 NXP * * SPDX-License-Identifier: BSD-3-Clause */ @@ -18,6 +18,8 @@ #define S32CC_PERIPH_PLL_PHI3_FREQ UART_CLOCK_HZ #define S32CC_DDR_PLL_VCO_FREQ (1600U * MHZ) #define S32CC_DDR_PLL_PHI0_FREQ (800U * MHZ) +#define S32CC_PERIPH_DFS_PHI3_FREQ (800U * MHZ) +#define S32CC_USDHC_FREQ (400U * MHZ) static int setup_fxosc(void) { @@ -180,6 +182,35 @@ static int enable_ddr_clk(void) return ret; } +static int enable_usdhc_clk(void) +{ + int ret; + + ret = clk_set_parent(S32CC_CLK_MC_CGM0_MUX14, + S32CC_CLK_PERIPH_PLL_DFS3); + if (ret != 0) { + return ret; + } + + ret = clk_set_rate(S32CC_CLK_PERIPH_PLL_DFS3, + S32CC_PERIPH_DFS_PHI3_FREQ, NULL); + if (ret != 0) { + return ret; + } + + ret = clk_set_rate(S32CC_CLK_USDHC, S32CC_USDHC_FREQ, NULL); + if (ret != 0) { + return ret; + } + + ret = clk_enable(S32CC_CLK_USDHC); + if (ret != 0) { + return ret; + } + + return ret; +} + int s32cc_init_core_clocks(void) { int ret; @@ -241,5 +272,10 @@ int s32cc_init_early_clks(void) return ret; } + ret = enable_usdhc_clk(); + if (ret != 0) { + return ret; + } + return ret; }