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fix(cpus): workaround for Cortex-X4 erratum 2763018

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Cortex-X4 erratum 2763018 is a Cat B erratum that is present
in revisions r0p0, r0p1 and is fixed in r0p2.

The workaround is to set bit[47] of CPUACTLR3_EL1 register.
Setting this chicken bit might have a small impact on power
and negligible impact on performance.

SDEN documentation:
https://developer.arm.com/documentation/SDEN2432808/latest

Change-Id: Ia188e08c2eb2952923ec72e2a56efdeea836fe1e
Signed-off-by: Sona Mathew <sonarebecca.mathew@arm.com>
This commit is contained in:
Sona Mathew 2024-04-05 16:27:07 -05:00
parent fb7aa37560
commit 47312115de
4 changed files with 19 additions and 1 deletions
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3
docs/design/cpu-specific-build-macros.rst
View file

@ -830,6 +830,9 @@ For Cortex-X4, the following errata build flags are defined :
CPU. This needs to be enabled for revisions r0p0 and r0p1. It is fixed
in r0p2.
- ``ERRATA_X4_2763018``: This applies errata 2763018 workaround to Cortex-X4
CPU. This needs to be enabled for revisions r0p0 and r0p1. It is fixed in r0p2.
For Cortex-A510, the following errata build flags are defined :
- ``ERRATA_A510_1922240``: This applies errata 1922240 workaround to

7
include/lib/cpus/aarch64/cortex_x4.h
View file

@ -1,5 +1,5 @@
/*
* Copyright (c) 2022-2023, Arm Limited. All rights reserved.
* Copyright (c) 2022-2024, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -23,4 +23,9 @@
#define CORTEX_X4_CPUPWRCTLR_EL1 S3_0_C15_C2_7
#define CORTEX_X4_CPUPWRCTLR_EL1_CORE_PWRDN_BIT U(1)
/*******************************************************************************
* CPU Auxiliary control register specific definitions
******************************************************************************/
#define CORTEX_X4_CPUACTLR3_EL1 S3_0_C15_C1_2
#endif /* CORTEX_X4_H */

6
lib/cpus/aarch64/cortex_x4.S
View file

@ -33,6 +33,12 @@ workaround_runtime_end cortex_x4, ERRATUM(2740089)
check_erratum_ls cortex_x4, ERRATUM(2740089), CPU_REV(0, 1)
workaround_reset_start cortex_x4, ERRATUM(2763018), ERRATA_X4_2763018
sysreg_bit_set CORTEX_X4_CPUACTLR3_EL1, BIT(47)
workaround_reset_end cortex_x4, ERRATUM(2763018)
check_erratum_ls cortex_x4, ERRATUM(2763018), CPU_REV(0, 1)
workaround_reset_start cortex_x4, CVE(2022, 23960), WORKAROUND_CVE_2022_23960
#if IMAGE_BL31
/*

4
lib/cpus/cpu-ops.mk
View file

@ -827,6 +827,10 @@ CPU_FLAG_LIST += ERRATA_X4_2701112
# applies to all revisions <= r0p1 of the Cortex-X4 cpu, it is fixed in r0p2.
CPU_FLAG_LIST += ERRATA_X4_2740089
# Flag to apply erratum 2763018 workaround on reset. This erratum applies
# to revisions r0p0 and r0p1 of the Cortex-X4 cpu. It is fixed in r0p2.
CPU_FLAG_LIST += ERRATA_X4_2763018
# Flag to apply erratum 1922240 workaround during reset. This erratum applies
# to revision r0p0 of the Cortex-A510 cpu and is fixed in r0p1.
CPU_FLAG_LIST += ERRATA_A510_1922240