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47312115de
Cortex-X4 erratum 2763018 is a Cat B erratum that is present in revisions r0p0, r0p1 and is fixed in r0p2. The workaround is to set bit[47] of CPUACTLR3_EL1 register. Setting this chicken bit might have a small impact on power and negligible impact on performance. SDEN documentation: https://developer.arm.com/documentation/SDEN2432808/latest Change-Id: Ia188e08c2eb2952923ec72e2a56efdeea836fe1e Signed-off-by: Sona Mathew <sonarebecca.mathew@arm.com>
31 lines
1.1 KiB
C
31 lines
1.1 KiB
C
/*
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* Copyright (c) 2022-2024, Arm Limited. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef CORTEX_X4_H
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#define CORTEX_X4_H
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#define CORTEX_X4_MIDR U(0x410FD821)
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/* Cortex X4 loop count for CVE-2022-23960 mitigation */
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#define CORTEX_X4_BHB_LOOP_COUNT U(132)
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/*******************************************************************************
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* CPU Extended Control register specific definitions
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******************************************************************************/
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#define CORTEX_X4_CPUECTLR_EL1 S3_0_C15_C1_4
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/*******************************************************************************
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* CPU Power Control register specific definitions
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******************************************************************************/
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#define CORTEX_X4_CPUPWRCTLR_EL1 S3_0_C15_C2_7
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#define CORTEX_X4_CPUPWRCTLR_EL1_CORE_PWRDN_BIT U(1)
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/*******************************************************************************
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* CPU Auxiliary control register specific definitions
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******************************************************************************/
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#define CORTEX_X4_CPUACTLR3_EL1 S3_0_C15_C1_2
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#endif /* CORTEX_X4_H */
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