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Merge "docs(zynqmp): add ddr address usage" into integration

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Joanna Farley 2023-03-13 09:51:19 +01:00 • committed by TrustedFirmware Code Review
commit 404e835c33
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docs/plat/xilinx-zynqmp.rst
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@ -76,6 +76,18 @@ make CROSS_COMPILE=aarch64-none-elf- PLAT=zynqmp RESET_TO_BL31=1 DEBUG=1 \
ZYNQMP_ATF_MEM_BASE=<DDR address> ZYNQMP_ATF_MEM_SIZE=<size> \ ZYNQMP_ATF_MEM_BASE=<DDR address> ZYNQMP_ATF_MEM_SIZE=<size> \
XILINX_OF_BOARD_DTB_ADDR=<DTB address> bl31 XILINX_OF_BOARD_DTB_ADDR=<DTB address> bl31
DDR Address Range Usage
-----------------------
When FSBL runs on RPU and TF-A is to be placed in DDR address range,
then the user needs to make sure that the DDR address is beyond 256KB.
In the RPU view, the first 256 KB is TCM memory.
For this use case, with the minimum base address in DDR for TF-A,
the build command example is;
make CROSS_COMPILE=aarch64-none-elf- PLAT=zynqmp RESET_TO_BL31=1 DEBUG=1 \
ZYNQMP_ATF_MEM_BASE=0x40000 ZYNQMP_ATF_MEM_SIZE=<size>
FSBL->TF-A Parameter Passing FSBL->TF-A Parameter Passing
---------------------------- ----------------------------