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docs(zynqmp): add ddr address usage

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Update documentation for TF-A DDR address range usage when the FSBL is
run on RPU instead of APU.

Change-Id: I223d67c35ac9ce3384820531a7453d3b32a1eb58
Signed-off-by: Akshay Belsare <akshay.belsare@amd.com>
This commit is contained in:
Belsare, Akshay 2023-03-06 15:08:54 +05:30 • committed by Akshay Belsare
parent 2b7150b381
commit 2b932f83db
1 changed files with 12 additions and 0 deletions

12
docs/plat/xilinx-zynqmp.rst
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@ -76,6 +76,18 @@ make CROSS_COMPILE=aarch64-none-elf- PLAT=zynqmp RESET_TO_BL31=1 DEBUG=1 \
ZYNQMP_ATF_MEM_BASE=<DDR address> ZYNQMP_ATF_MEM_SIZE=<size> \
XILINX_OF_BOARD_DTB_ADDR=<DTB address> bl31
DDR Address Range Usage
-----------------------
When FSBL runs on RPU and TF-A is to be placed in DDR address range,
then the user needs to make sure that the DDR address is beyond 256KB.
In the RPU view, the first 256 KB is TCM memory.
For this use case, with the minimum base address in DDR for TF-A,
the build command example is;
make CROSS_COMPILE=aarch64-none-elf- PLAT=zynqmp RESET_TO_BL31=1 DEBUG=1 \
ZYNQMP_ATF_MEM_BASE=0x40000 ZYNQMP_ATF_MEM_SIZE=<size>
FSBL->TF-A Parameter Passing
----------------------------