mirror of
https://github.com/ARM-software/arm-trusted-firmware.git
synced 2025-04-16 09:34:18 +00:00
feat(cpus): add a concise way to implement AArch64 errata
Errata implementation involves adding a lot of boilerplate to random
places with just conventions on how to do them. Copy pasting is the
usual method for doing this. The result is an error-prone and verbose
patch that is a nightmare to get through review.
Errata workarounds have a very large degree of similarity - most of them
involve setting a bit at reset. As such most of the boilerplate is not
strictly necessary. To solve this, add a collection of assembly macros
to wrap errata implementations such that only the actual mitigations
need to be written. A new erratum mitigation looks something like:
workaround_reset_start cortex_a77, ERRATUM(1925769), ERRATA_A77_1925769
sysreg_bit_set CORTEX_A77_CPUECTLR_EL1, CORTEX_A77_CPUECTLR_EL1_BIT_8
workaround_reset_end cortex_a77, ERRATUM(1925769)
check_erratum_ls cortex_a77, ERRATUM(1925769), CPU_REV(1, 1)
Note, that the long comment on every mitigation is missing. This is on
purpose, as this new format includes all of its contents into an easily
readable format.
The workaround wrappers add an erratum entry (24 bytes) to a per-cpu
data structure which can then be read by a standard reset function to
apply all errata automatically. This has the added benefit of collecting
all errata TF-A knows about in a central way, which was previously
missing. This can then be used at runtime with the errata ABI.
If an erratum doesn't fit this standard definition (eg. the
CVE_2022_23960), it can progressively be unwrapped to the old
convention. The only differences are that the naming format is slightly
more verbose and a call to add_erratum_entry is needed to inform the
framework about the errata.
Finally, the internal workaround names change a tiny bit, especially
CVEs.
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
Change-Id: Iac644f85dcf85b8279b25e83baf1e7d08b253b16
This commit is contained in:
Boyan Karatotev
parent
dd9fae1ce0
commit
3f4c1e1e7b
3 changed files with 372 additions and 6 deletions
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@ -91,6 +91,27 @@
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/* Insert list of functions */
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fill_constants CPU_MAX_PWR_DWN_OPS, \_power_down_ops
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#endif
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/*
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* It is possible (although unlikely) that a cpu may have no errata in
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* code. In that case the start label will not be defined. The list is
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* intended to be used in a loop, so define it as zero-length for
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* predictable behaviour. Since this macro is always called at the end
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* of the cpu file (after all errata have been parsed) we can be sure
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* that we are at the end of the list. Some cpus call declare_cpu_ops
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* twice, so only do this once.
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*/
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.pushsection .rodata.errata_entries
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.ifndef \_name\()_errata_list_start
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\_name\()_errata_list_start:
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.endif
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.ifndef \_name\()_errata_list_end
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\_name\()_errata_list_end:
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.endif
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.popsection
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/* and now put them in cpu_ops */
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.quad \_name\()_errata_list_start
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.quad \_name\()_errata_list_end
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#if REPORT_ERRATA
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.ifndef \_name\()_cpu_str
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@ -111,18 +132,20 @@
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.popsection
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.endif
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/*
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* Mandatory errata status printing function for CPUs of
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* this class.
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*/
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.quad \_name\()_errata_report
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.quad \_name\()_cpu_str
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#ifdef IMAGE_BL31
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/* Pointers to errata lock and reported flag */
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.quad \_name\()_errata_lock
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.quad \_name\()_errata_reported
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#endif
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#endif
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#endif /* IMAGE_BL31 */
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#endif /* REPORT_ERRATA */
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#if defined(IMAGE_BL31) && CRASH_REPORTING
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.quad \_name\()_cpu_reg_dump
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@ -148,6 +171,7 @@
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\_extra1, \_extra2, \_extra3, 0, \_power_down_ops
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.endm
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/* TODO can be deleted once all CPUs have been converted */
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#if REPORT_ERRATA
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/*
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* Print status of a CPU errata
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@ -230,4 +254,302 @@
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b.eq \_label
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.endm
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/*
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* Workaround wrappers for errata that apply at reset or runtime. Reset errata
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* will be applied automatically
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*
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* _cpu:
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* Name of cpu as given to declare_cpu_ops
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*
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* _cve:
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* Whether erratum is a CVE. CVE year if yes, 0 otherwise
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*
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* _id:
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* Erratum or CVE number. Please combine with previous field with ERRATUM
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* or CVE macros
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*
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* _chosen:
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* Compile time flag on whether the erratum is included
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*
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* _apply_at_reset:
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* Whether the erratum should be automatically applied at reset
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*/
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.macro add_erratum_entry _cpu:req, _cve:req, _id:req, _chosen:req, _apply_at_reset:req
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.pushsection .rodata.errata_entries
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.align 3
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.ifndef \_cpu\()_errata_list_start
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\_cpu\()_errata_list_start:
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.endif
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/* check if unused and compile out if no references */
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.if \_apply_at_reset && \_chosen
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.quad erratum_\_cpu\()_\_id\()_wa
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.else
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.quad 0
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.endif
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/* TODO(errata ABI): this prevents all checker functions from
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* being optimised away. Can be done away with unless the ABI
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* needs them */
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.quad check_erratum_\_cpu\()_\_id
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/* Will fit CVEs with up to 10 character in the ID field */
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.word \_id
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.hword \_cve
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.byte \_chosen
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/* TODO(errata ABI): mitigated field for known but unmitigated
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* errata */
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.byte 0x1
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.popsection
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.endm
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.macro _workaround_start _cpu:req, _cve:req, _id:req, _chosen:req, _apply_at_reset:req
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add_erratum_entry \_cpu, \_cve, \_id, \_chosen, \_apply_at_reset
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func erratum_\_cpu\()_\_id\()_wa
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mov x8, x30
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/* save rev_var for workarounds that might need it but don't
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* restore to x0 because few will care */
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mov x7, x0
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bl check_erratum_\_cpu\()_\_id
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cbz x0, erratum_\_cpu\()_\_id\()_skip
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.endm
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.macro _workaround_end _cpu:req, _id:req
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erratum_\_cpu\()_\_id\()_skip:
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ret x8
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endfunc erratum_\_cpu\()_\_id\()_wa
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.endm
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/*******************************************************************************
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* Errata workaround wrappers
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******************************************************************************/
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/*
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* Workaround wrappers for errata that apply at reset or runtime. Reset errata
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* will be applied automatically
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*
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* _cpu:
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* Name of cpu as given to declare_cpu_ops
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*
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* _cve:
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* Whether erratum is a CVE. CVE year if yes, 0 otherwise
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*
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* _id:
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* Erratum or CVE number. Please combine with previous field with ERRATUM
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* or CVE macros
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*
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* _chosen:
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* Compile time flag on whether the erratum is included
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*
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* in body:
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* clobber x0 to x7 (please only use those)
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* argument x7 - cpu_rev_var
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*
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* _wa clobbers: x0-x8 (PCS compliant)
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*/
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.macro workaround_reset_start _cpu:req, _cve:req, _id:req, _chosen:req
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_workaround_start \_cpu, \_cve, \_id, \_chosen, 1
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.endm
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/*
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* See `workaround_reset_start` for usage info. Additional arguments:
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*
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* _midr:
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* Check if CPU's MIDR matches the CPU it's meant for. Must be specified
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* for errata applied in generic code
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*/
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.macro workaround_runtime_start _cpu:req, _cve:req, _id:req, _chosen:req, _midr
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/*
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* Let errata specify if they need MIDR checking. Sadly, storing the
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* MIDR in an .equ to retrieve automatically blows up as it stores some
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* brackets in the symbol
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*/
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.ifnb \_midr
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jump_if_cpu_midr \_midr, 1f
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b erratum_\_cpu\()_\_id\()_skip
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1:
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.endif
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_workaround_start \_cpu, \_cve, \_id, \_chosen, 0
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.endm
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/*
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* Usage and arguments identical to `workaround_reset_start`. The _cve argument
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* is kept here so the same #define can be used as that macro
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*/
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.macro workaround_reset_end _cpu:req, _cve:req, _id:req
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_workaround_end \_cpu, \_id
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.endm
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/*
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* See `workaround_reset_start` for usage info. The _cve argument is kept here
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* so the same #define can be used as that macro. Additional arguments:
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*
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* _no_isb:
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* Optionally do not include the trailing isb. Please disable with the
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* NO_ISB macro
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*/
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.macro workaround_runtime_end _cpu:req, _cve:req, _id:req, _no_isb
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/*
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* Runtime errata do not have a reset function to call the isb for them
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* and missing the isb could be very problematic. It is also likely as
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* they tend to be scattered in generic code.
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*/
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.ifb \_no_isb
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isb
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.endif
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_workaround_end \_cpu, \_id
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.endm
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/*******************************************************************************
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* Errata workaround helpers
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******************************************************************************/
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/*
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* Set a bit in a system register. Can set multiple bits but is limited by the
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* way the ORR instruction encodes them.
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*
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* _reg:
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* Register to write to
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*
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* _bit:
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* Bit to set. Please use a descriptive #define
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*
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* _assert:
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* Optionally whether to read back and assert that the bit has been
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* written. Please disable with NO_ASSERT macro
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*
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* clobbers: x1
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*/
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.macro sysreg_bit_set _reg:req, _bit:req, _assert=1
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mrs x1, \_reg
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orr x1, x1, #\_bit
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msr \_reg, x1
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.endm
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/*
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* Apply erratum
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*
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* _cpu:
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* Name of cpu as given to declare_cpu_ops
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*
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* _cve:
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* Whether erratum is a CVE. CVE year if yes, 0 otherwise
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*
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* _id:
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* Erratum or CVE number. Please combine with previous field with ERRATUM
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* or CVE macros
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*
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* _chosen:
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* Compile time flag on whether the erratum is included
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*
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* clobbers: x0-x9 (PCS compliant)
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*/
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.macro apply_erratum _cpu:req, _cve:req, _id:req, _chosen:req
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.if \_chosen
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mov x9, x30
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bl cpu_get_rev_var
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bl erratum_\_cpu\()_\_id\()_wa
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mov x30, x9
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.endif
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.endm
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/*
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* Helpers to select which revisions errata apply to. Don't leave a link
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* register as the cpu_rev_var_*** will call the ret and we can save on one.
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*
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* _cpu:
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* Name of cpu as given to declare_cpu_ops
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*
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* _cve:
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* Whether erratum is a CVE. CVE year if yes, 0 otherwise
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*
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* _id:
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* Erratum or CVE number. Please combine with previous field with ERRATUM
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* or CVE macros
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*
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* _rev_num:
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* Revision to apply to
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*
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* in body:
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* clobber: x0 to x4
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* argument: x0 - cpu_rev_var
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*/
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.macro check_erratum_ls _cpu:req, _cve:req, _id:req, _rev_num:req
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func check_erratum_\_cpu\()_\_id
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mov x1, #\_rev_num
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b cpu_rev_var_ls
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endfunc check_erratum_\_cpu\()_\_id
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.endm
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.macro check_erratum_hs _cpu:req, _cve:req, _id:req, _rev_num:req
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func check_erratum_\_cpu\()_\_id
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mov x1, #\_rev_num
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b cpu_rev_var_hs
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endfunc check_erratum_\_cpu\()_\_id
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.endm
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.macro check_erratum_range _cpu:req, _cve:req, _id:req, _rev_num_lo:req, _rev_num_hi:req
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func check_erratum_\_cpu\()_\_id
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mov x1, #\_rev_num_lo
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mov x2, #\_rev_num_hi
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b cpu_rev_var_range
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endfunc check_erratum_\_cpu\()_\_id
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.endm
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/*******************************************************************************
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* CPU reset function wrapper
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******************************************************************************/
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/*
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* Wrapper to automatically apply all reset-time errata. Will end with an isb.
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*
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* _cpu:
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* Name of cpu as given to declare_cpu_ops
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*
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* in body:
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* clobber x8 to x14
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* argument x14 - cpu_rev_var
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*/
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.macro cpu_reset_func_start _cpu:req
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func \_cpu\()_reset_func
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mov x15, x30
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bl cpu_get_rev_var
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mov x14, x0
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/* short circuit the location to avoid searching the list */
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adrp x12, \_cpu\()_errata_list_start
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add x12, x12, :lo12:\_cpu\()_errata_list_start
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adrp x13, \_cpu\()_errata_list_end
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add x13, x13, :lo12:\_cpu\()_errata_list_end
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errata_begin:
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/* if head catches up with end of list, exit */
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cmp x12, x13
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b.eq errata_end
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ldr x10, [x12, #ERRATUM_WA_FUNC]
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/* TODO(errata ABI): check mitigated and checker function fields
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* for 0 */
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ldrb w11, [x12, #ERRATUM_CHOSEN]
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/* skip if not chosen */
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cbz x11, 1f
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/* skip if runtime erratum */
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cbz x10, 1f
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/* put cpu revision in x0 and call workaround */
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mov x0, x14
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blr x10
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1:
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add x12, x12, #ERRATUM_ENTRY_SIZE
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b errata_begin
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errata_end:
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.endm
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.macro cpu_reset_func_end _cpu:req
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isb
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ret x15
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endfunc \_cpu\()_reset_func
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.endm
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#endif /* CPU_MACROS_S */
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@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2023, ARM Limited and Contributors. All rights reserved.
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* Copyright (c) 2023, Arm Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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@ -53,9 +53,12 @@
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#define CPU_PWR_DWN_OPS_SIZE 0
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#endif /* defined(IMAGE_BL31) || defined(IMAGE_BL32) */
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#define CPU_ERRATA_LIST_START_SIZE CPU_WORD_SIZE
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#define CPU_ERRATA_LIST_END_SIZE CPU_WORD_SIZE
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/* Fields required to print errata status */
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#if REPORT_ERRATA
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#define CPU_ERRATA_FUNC_SIZE CPU_WORD_SIZE
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#define CPU_CPU_STR_SIZE CPU_WORD_SIZE
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/* BL1 doesn't require mutual exclusion and printed flag. */
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#if defined(IMAGE_BL31) || defined(IMAGE_BL32)
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#define CPU_ERRATA_LOCK_SIZE CPU_WORD_SIZE
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@ -66,6 +69,7 @@
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#endif /* defined(IMAGE_BL31) || defined(IMAGE_BL32) */
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#else
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#define CPU_ERRATA_FUNC_SIZE 0
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#define CPU_CPU_STR_SIZE 0
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#define CPU_ERRATA_LOCK_SIZE 0
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#define CPU_ERRATA_PRINTED_SIZE 0
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#endif /* REPORT_ERRATA */
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@ -92,8 +96,11 @@
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#else
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#define CPU_PWR_DWN_OPS CPU_RESET_FUNC + CPU_RESET_FUNC_SIZE
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#endif /* __aarch64__ */
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#define CPU_ERRATA_FUNC CPU_PWR_DWN_OPS + CPU_PWR_DWN_OPS_SIZE
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#define CPU_ERRATA_LOCK CPU_ERRATA_FUNC + CPU_ERRATA_FUNC_SIZE
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#define CPU_ERRATA_LIST_START CPU_PWR_DWN_OPS + CPU_PWR_DWN_OPS_SIZE
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#define CPU_ERRATA_LIST_END CPU_ERRATA_LIST_START + CPU_ERRATA_LIST_START_SIZE
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#define CPU_ERRATA_FUNC CPU_ERRATA_LIST_END + CPU_ERRATA_LIST_END_SIZE
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#define CPU_CPU_STR CPU_ERRATA_FUNC + CPU_ERRATA_FUNC_SIZE
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#define CPU_ERRATA_LOCK CPU_CPU_STR + CPU_CPU_STR_SIZE
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#define CPU_ERRATA_PRINTED CPU_ERRATA_LOCK + CPU_ERRATA_LOCK_SIZE
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#if __aarch64__
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#define CPU_REG_DUMP CPU_ERRATA_PRINTED + CPU_ERRATA_PRINTED_SIZE
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@ -120,8 +127,11 @@ struct cpu_ops {
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#if (defined(IMAGE_BL31) || defined(IMAGE_BL32)) && CPU_MAX_PWR_DWN_OPS
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void (*pwr_dwn_ops[CPU_MAX_PWR_DWN_OPS])(void);
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#endif /* (defined(IMAGE_BL31) || defined(IMAGE_BL32)) && CPU_MAX_PWR_DWN_OPS */
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void *errata_list_start;
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void *errata_list_end;
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#if REPORT_ERRATA
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void (*errata_func)(void);
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char *cpu_str;
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#if defined(IMAGE_BL31) || defined(IMAGE_BL32)
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spinlock_t *errata_lock;
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unsigned int *errata_reported;
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@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2017-2023, ARM Limited and Contributors. All rights reserved.
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* Copyright (c) 2017-2023, Arm Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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@ -7,11 +7,45 @@
|
|||
#ifndef ERRATA_REPORT_H
|
||||
#define ERRATA_REPORT_H
|
||||
|
||||
#include <lib/cpus/cpu_ops.h>
|
||||
|
||||
|
||||
#define ERRATUM_WA_FUNC_SIZE CPU_WORD_SIZE
|
||||
#define ERRATUM_CHECK_FUNC_SIZE CPU_WORD_SIZE
|
||||
#define ERRATUM_ID_SIZE 4
|
||||
#define ERRATUM_CVE_SIZE 2
|
||||
#define ERRATUM_CHOSEN_SIZE 1
|
||||
#define ERRATUM_MITIGATED_SIZE 1
|
||||
|
||||
#define ERRATUM_WA_FUNC 0
|
||||
#define ERRATUM_CHECK_FUNC ERRATUM_WA_FUNC + ERRATUM_WA_FUNC_SIZE
|
||||
#define ERRATUM_ID ERRATUM_CHECK_FUNC + ERRATUM_CHECK_FUNC_SIZE
|
||||
#define ERRATUM_CVE ERRATUM_ID + ERRATUM_ID_SIZE
|
||||
#define ERRATUM_CHOSEN ERRATUM_CVE + ERRATUM_CVE_SIZE
|
||||
#define ERRATUM_MITIGATED ERRATUM_CHOSEN + ERRATUM_CHOSEN_SIZE
|
||||
#define ERRATUM_ENTRY_SIZE ERRATUM_MITIGATED + ERRATUM_MITIGATED_SIZE
|
||||
|
||||
#ifndef __ASSEMBLER__
|
||||
|
||||
void print_errata_status(void);
|
||||
void errata_print_msg(unsigned int status, const char *cpu, const char *id);
|
||||
|
||||
#else
|
||||
|
||||
/*
|
||||
* errata framework macro helpers
|
||||
*
|
||||
* NOTE an erratum and CVE id could clash. However, both numbers are very large
|
||||
* and the probablity is minuscule. Working around this makes code very
|
||||
* complicated and extremely difficult to read so it is not considered. In the
|
||||
* unlikely event that this does happen, prepending the CVE id with a 0 should
|
||||
* resolve the conflict
|
||||
*/
|
||||
#define ERRATUM(id) 0, id
|
||||
#define CVE(year, id) year, id
|
||||
#define NO_ISB 1
|
||||
#define NO_ASSERT 0
|
||||
|
||||
#endif /* __ASSEMBLER__ */
|
||||
|
||||
/* Errata status */
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue