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Merge "fix(intel): update individual return result for hps and fpga bridges" into integration

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This commit is contained in:
Manish Pandey 2023-11-27 16:39:04 +01:00 • committed by TrustedFirmware Code Review
commit 3a1dd15287
1 changed files with 4 additions and 2 deletions
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6
plat/intel/soc/common/soc/socfpga_reset_manager.c
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@ -407,6 +407,7 @@ int socfpga_bridges_reset(uint32_t mask)
int socfpga_bridges_enable(uint32_t mask) int socfpga_bridges_enable(uint32_t mask)
{ {
int ret = 0; int ret = 0;
int ret_hps = 0;
uint32_t brg_mask = 0; uint32_t brg_mask = 0;
uint32_t noc_mask = 0; uint32_t noc_mask = 0;
uint32_t f2s_idlereq = 0; uint32_t f2s_idlereq = 0;
@ -505,9 +506,9 @@ int socfpga_bridges_enable(uint32_t mask)
mmio_clrbits_32(SOCFPGA_RSTMGR(BRGMODRST), brg_mask); mmio_clrbits_32(SOCFPGA_RSTMGR(BRGMODRST), brg_mask);
/* Wait until idle ack becomes 0 */ /* Wait until idle ack becomes 0 */
ret = poll_idle_status(SOCFPGA_SYSMGR(NOC_IDLEACK), ret_hps = poll_idle_status(SOCFPGA_SYSMGR(NOC_IDLEACK),
noc_mask, 0, 300); noc_mask, 0, 300);
if (ret < 0) { if (ret_hps < 0) {
ERROR("S2F bridge enable: Timeout idle ack\n"); ERROR("S2F bridge enable: Timeout idle ack\n");
} }
} }
@ -711,6 +712,7 @@ int socfpga_bridges_enable(uint32_t mask)
udelay(5); udelay(5);
} }
#endif #endif
ret = ret | ret_hps;
return ret; return ret;
} }