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feat(cpufeat): added few helper functions

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Following utility functions/bit definitions done
 - Write a helper function to return the presence of following features
    - FEAT_UAO
    - FEAT_EBEP
    - FEAT_SEBEP
    - FEAT_SSBS
    - FEAT_NMI
    - FEAT_PAN
 - Add definition of some missing bits of SPSR.
 - Add GCSCR_EL1 register encoding and accessor function.

Signed-off-by: Manish Pandey <manish.pandey2@arm.com>
Change-Id: Ifcead0dd8e3b32096e4ab810dde5d582a889785a
This commit is contained in:
Manish Pandey 2024-01-09 15:55:20 +00:00
parent df21d41b77
commit 30f05b4f5d
6 changed files with 117 additions and 13 deletions
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6
include/arch/aarch32/arch.h
View file

@ -163,6 +163,11 @@
#define ID_PFR1_SEC_MASK U(0xf)
#define ID_PFR1_ELx_ENABLED U(1)
/* ID_PFR2 definitions */
#define ID_PFR2_SSBS_SHIFT U(4)
#define ID_PFR2_SSBS_MASK U(0xf)
#define SSBS_UNAVAILABLE U(0)
/* SCTLR definitions */
#define SCTLR_RES1_DEF ((U(1) << 23) | (U(1) << 22) | (U(1) << 4) | \
(U(1) << 3))
@ -552,6 +557,7 @@
#define ID_DFR1 p15, 0, c0, c3, 5
#define ID_PFR0 p15, 0, c0, c1, 0
#define ID_PFR1 p15, 0, c0, c1, 1
#define ID_PFR2 p15, 0, c0, c3, 4
#define MAIR0 p15, 0, c10, c2, 0
#define MAIR1 p15, 0, c10, c2, 1
#define TTBCR p15, 0, c2, c0, 2

15
include/arch/aarch32/arch_features.h
View file

@ -128,6 +128,17 @@ static inline bool is_feat_pan_supported(void)
return read_feat_pan_id_field() != 0U;
}
static inline bool is_feat_pan_present(void)
{
return read_feat_pan_id_field() != 0U;
}
static inline unsigned int is_feat_ssbs_present(void)
{
return ((read_id_pfr2() >> ID_PFR2_SSBS_SHIFT) &
ID_PFR2_SSBS_MASK) != SSBS_UNAVAILABLE;
}
/*
* TWED, ECV, CSV2, RAS are only used by the AArch64 EL2 context switch
* code. In fact, EL2 context switching is only needed for AArch64 (since
@ -164,6 +175,10 @@ static inline bool is_feat_sxpoe_supported(void) { return false; }
static inline bool is_feat_s2pie_supported(void) { return false; }
static inline bool is_feat_s1pie_supported(void) { return false; }
static inline bool is_feat_sxpie_supported(void) { return false; }
static inline bool is_feat_uao_present(void) { return false; }
static inline bool is_feat_nmi_present(void) { return false; }
static inline bool is_feat_ebep_present(void) { return false; }
static inline bool is_feat_sebep_present(void) { return false; }
static inline unsigned int read_feat_pmuv3_id_field(void)
{

1
include/arch/aarch32/arch_helpers.h
View file

@ -224,6 +224,7 @@ DEFINE_COPROCR_READ_FUNC(id_dfr0, ID_DFR0)
DEFINE_COPROCR_READ_FUNC(id_dfr1, ID_DFR1)
DEFINE_COPROCR_READ_FUNC(id_pfr0, ID_PFR0)
DEFINE_COPROCR_READ_FUNC(id_pfr1, ID_PFR1)
DEFINE_COPROCR_READ_FUNC(id_pfr2, ID_PFR2)
DEFINE_COPROCR_READ_FUNC(isr, ISR)
DEFINE_COPROCR_READ_FUNC(clidr, CLIDR)
DEFINE_COPROCR_READ_FUNC_64(cntpct, CNTPCT_64)

59
include/arch/aarch64/arch.h
View file

@ -231,6 +231,11 @@
#define ID_AA64DFR0_PMUVER_PMUV3P7 U(7)
#define ID_AA64DFR0_PMUVER_IMP_DEF U(0xf)
/* ID_AA64DFR0_EL1.SEBEP definitions */
#define ID_AA64DFR0_SEBEP_SHIFT U(24)
#define ID_AA64DFR0_SEBEP_MASK ULL(0xf)
#define SEBEP_IMPLEMENTED ULL(1)
/* ID_AA64DFR0_EL1.PMS definitions (for ARMv8.2+) */
#define ID_AA64DFR0_PMS_SHIFT U(32)
#define ID_AA64DFR0_PMS_MASK ULL(0xf)
@ -253,6 +258,11 @@
#define ID_AA64DFR0_BRBE_MASK ULL(0xf)
#define ID_AA64DFR0_BRBE_SUPPORTED ULL(1)
/* ID_AA64DFR1_EL1 definitions */
#define ID_AA64DFR1_EBEP_SHIFT U(48)
#define ID_AA64DFR1_EBEP_MASK ULL(0xf)
#define EBEP_IMPLEMENTED ULL(1)
/* ID_AA64ISAR0_EL1 definitions */
#define ID_AA64ISAR0_RNDR_SHIFT U(60)
#define ID_AA64ISAR0_RNDR_MASK ULL(0xf)
@ -358,6 +368,9 @@
#define ID_AA64MMFR2_EL1_CCIDX_MASK ULL(0xf)
#define ID_AA64MMFR2_EL1_CCIDX_LENGTH U(4)
#define ID_AA64MMFR2_EL1_UAO_SHIFT U(4)
#define ID_AA64MMFR2_EL1_UAO_MASK ULL(0xf)
#define ID_AA64MMFR2_EL1_CNP_SHIFT U(0)
#define ID_AA64MMFR2_EL1_CNP_MASK ULL(0xf)
@ -386,25 +399,29 @@
#define ID_AA64MMFR3_EL1_TCRX_MASK ULL(0xf)
/* ID_AA64PFR1_EL1 definitions */
#define ID_AA64PFR1_EL1_GCS_SHIFT U(44)
#define ID_AA64PFR1_EL1_GCS_MASK ULL(0xf)
#define ID_AA64PFR1_EL1_SSBS_SHIFT U(4)
#define ID_AA64PFR1_EL1_SSBS_MASK ULL(0xf)
#define SSBS_UNAVAILABLE ULL(0) /* No architectural SSBS support */
#define ID_AA64PFR1_EL1_BT_SHIFT U(0)
#define ID_AA64PFR1_EL1_BT_MASK ULL(0xf)
#define BTI_IMPLEMENTED ULL(1) /* The BTI mechanism is implemented */
#define ID_AA64PFR1_EL1_SSBS_SHIFT U(4)
#define ID_AA64PFR1_EL1_SSBS_MASK ULL(0xf)
#define SSBS_UNAVAILABLE ULL(0) /* No architectural SSBS support */
#define ID_AA64PFR1_EL1_MTE_SHIFT U(8)
#define ID_AA64PFR1_EL1_MTE_MASK ULL(0xf)
#define ID_AA64PFR1_EL1_RNDR_TRAP_SHIFT U(28)
#define ID_AA64PFR1_EL1_RNDR_TRAP_MASK U(0xf)
#define ID_AA64PFR1_EL1_NMI_SHIFT U(36)
#define ID_AA64PFR1_EL1_NMI_MASK ULL(0xf)
#define NMI_IMPLEMENTED ULL(1)
#define ID_AA64PFR1_EL1_GCS_SHIFT U(44)
#define ID_AA64PFR1_EL1_GCS_MASK ULL(0xf)
#define GCS_IMPLEMENTED ULL(1)
#define ID_AA64PFR1_EL1_RNG_TRAP_SUPPORTED ULL(0x1)
#define ID_AA64PFR1_EL1_RNG_TRAP_NOT_SUPPORTED ULL(0x0)
@ -503,6 +520,7 @@
#define SCTLR_TCF0_SHIFT U(38)
#define SCTLR_TCF0_MASK ULL(3)
#define SCTLR_ENTP2_BIT (ULL(1) << 60)
#define SCTLR_SPINTMASK_BIT (ULL(1) << 62)
/* Tag Check Faults in EL0 have no effect on the PE */
#define SCTLR_TCF0_NO_EFFECT U(0)
@ -730,6 +748,10 @@
#define DAIF_IRQ_BIT (U(1) << 1)
#define DAIF_ABT_BIT (U(1) << 2)
#define DAIF_DBG_BIT (U(1) << 3)
#define SPSR_V_BIT (U(1) << 28)
#define SPSR_C_BIT (U(1) << 29)
#define SPSR_Z_BIT (U(1) << 30)
#define SPSR_N_BIT (U(1) << 31)
#define SPSR_DAIF_SHIFT U(6)
#define SPSR_DAIF_MASK U(0xf)
@ -750,25 +772,32 @@
#define SPSR_M_MASK U(0x1)
#define SPSR_M_AARCH64 U(0x0)
#define SPSR_M_AARCH32 U(0x1)
#define SPSR_M_EL1H U(0x5)
#define SPSR_M_EL2H U(0x9)
#define SPSR_EL_SHIFT U(2)
#define SPSR_EL_WIDTH U(2)
#define SPSR_SSBS_SHIFT_AARCH64 U(12)
#define SPSR_BTYPE_SHIFT_AARCH64 U(10)
#define SPSR_BTYPE_MASK_AARCH64 U(0x3)
#define SPSR_SSBS_SHIFT_AARCH64 U(12)
#define SPSR_SSBS_BIT_AARCH64 (ULL(1) << SPSR_SSBS_SHIFT_AARCH64)
#define SPSR_SSBS_SHIFT_AARCH32 U(23)
#define SPSR_SSBS_BIT_AARCH32 (ULL(1) << SPSR_SSBS_SHIFT_AARCH32)
#define SPSR_ALLINT_BIT_AARCH64 BIT_64(13)
#define SPSR_IL_BIT BIT_64(20)
#define SPSR_SS_BIT BIT_64(21)
#define SPSR_PAN_BIT BIT_64(22)
#define SPSR_UAO_BIT_AARCH64 BIT_64(23)
#define SPSR_DIT_BIT BIT(24)
#define SPSR_TCO_BIT_AARCH64 BIT_64(25)
#define SPSR_PM_BIT_AARCH64 BIT_64(32)
#define SPSR_PPEND_BIT BIT(33)
#define SPSR_EXLOCK_BIT_AARCH64 BIT_64(34)
#define SPSR_NZCV (SPSR_V_BIT | SPSR_C_BIT | SPSR_Z_BIT | SPSR_N_BIT)
#define DISABLE_ALL_EXCEPTIONS \
(DAIF_FIQ_BIT | DAIF_IRQ_BIT | DAIF_ABT_BIT | DAIF_DBG_BIT)
#define DISABLE_INTERRUPTS (DAIF_FIQ_BIT | DAIF_IRQ_BIT)
/*
@ -946,6 +975,7 @@
#define ESR_EC_LENGTH U(6)
#define ESR_ISS_SHIFT U(0)
#define ESR_ISS_LENGTH U(25)
#define ESR_IL_BIT (U(1) << 25)
#define EC_UNKNOWN U(0x0)
#define EC_WFE_WFI U(0x1)
#define EC_AARCH32_CP15_MRC_MCR U(0x3)
@ -1408,6 +1438,9 @@
******************************************************************************/
#define GCSCR_EL2 S3_4_C2_C5_0
#define GCSPR_EL2 S3_4_C2_C5_1
#define GCSCR_EL1 S3_0_C2_C5_0
#define GCSCR_EXLOCK_EN_BIT (UL(1) << 6)
/*******************************************************************************
* Definitions for DynamicIQ Shared Unit registers

47
include/arch/aarch64/arch_features.h
View file

@ -42,6 +42,11 @@ static inline bool is_armv7_gentimer_present(void)
CREATE_FEATURE_FUNCS(feat_pan, id_aa64mmfr1_el1, ID_AA64MMFR1_EL1_PAN_SHIFT,
ENABLE_FEAT_PAN)
static inline bool is_feat_pan_present(void)
{
return read_feat_pan_id_field() != 0U;
}
CREATE_FEATURE_FUNCS(feat_vhe, id_aa64mmfr1_el1, ID_AA64MMFR1_EL1_VHE_SHIFT,
ENABLE_FEAT_VHE)
@ -51,6 +56,12 @@ static inline bool is_armv8_2_ttcnp_present(void)
ID_AA64MMFR2_EL1_CNP_MASK) != 0U;
}
static inline bool is_feat_uao_present(void)
{
return ((read_id_aa64mmfr2_el1() >> ID_AA64MMFR2_EL1_UAO_SHIFT) &
ID_AA64MMFR2_EL1_UAO_MASK) != 0U;
}
static inline bool is_feat_pacqarma3_present(void)
{
uint64_t mask_id_aa64isar2 =
@ -89,6 +100,42 @@ static inline bool is_armv8_5_bti_present(void)
ID_AA64PFR1_EL1_BT_MASK) == BTI_IMPLEMENTED;
}
static inline unsigned int get_armv8_5_mte_support(void)
{
return ((read_id_aa64pfr1_el1() >> ID_AA64PFR1_EL1_MTE_SHIFT) &
ID_AA64PFR1_EL1_MTE_MASK);
}
static inline bool is_feat_ssbs_present(void)
{
return ((read_id_aa64pfr1_el1() >> ID_AA64PFR1_EL1_SSBS_SHIFT) &
ID_AA64PFR1_EL1_SSBS_MASK) != SSBS_UNAVAILABLE;
}
static inline bool is_feat_nmi_present(void)
{
return ((read_id_aa64pfr1_el1() >> ID_AA64PFR1_EL1_NMI_SHIFT) &
ID_AA64PFR1_EL1_NMI_MASK) == NMI_IMPLEMENTED;
}
static inline bool is_feat_gcs_present(void)
{
return ((read_id_aa64pfr1_el1() >> ID_AA64PFR1_EL1_GCS_SHIFT) &
ID_AA64PFR1_EL1_GCS_MASK) == GCS_IMPLEMENTED;
}
static inline bool is_feat_ebep_present(void)
{
return ((read_id_aa64dfr1_el1() >> ID_AA64DFR1_EBEP_SHIFT) &
ID_AA64DFR1_EBEP_MASK) == EBEP_IMPLEMENTED;
}
static inline bool is_feat_sebep_present(void)
{
return ((read_id_aa64dfr0_el1() >> ID_AA64DFR0_SEBEP_SHIFT) &
ID_AA64DFR0_SEBEP_MASK) == SEBEP_IMPLEMENTED;
}
CREATE_FEATURE_FUNCS(feat_mte, id_aa64pfr1_el1, ID_AA64PFR1_EL1_MTE_SHIFT,
ENABLE_FEAT_MTE)
CREATE_FEATURE_FUNCS_VER(feat_mte2, read_feat_mte_id_field, MTE_IMPLEMENTED_ELX,

2
include/arch/aarch64/arch_helpers.h
View file

@ -271,6 +271,7 @@ DEFINE_IDREG_READ_FUNC(id_aa64pfr0_el1)
DEFINE_IDREG_READ_FUNC(id_aa64pfr1_el1)
DEFINE_RENAME_IDREG_READ_FUNC(id_aa64pfr2_el1, ID_AA64PFR2_EL1)
DEFINE_IDREG_READ_FUNC(id_aa64dfr0_el1)
DEFINE_IDREG_READ_FUNC(id_aa64dfr1_el1)
DEFINE_IDREG_READ_FUNC(id_afr0_el1)
DEFINE_SYSREG_READ_FUNC(CurrentEl)
DEFINE_SYSREG_READ_FUNC(ctr_el0)
@ -645,6 +646,7 @@ DEFINE_RENAME_SYSREG_RW_FUNCS(por_el2, POR_EL2)
/* FEAT_GCS Registers */
DEFINE_RENAME_SYSREG_RW_FUNCS(gcscr_el2, GCSCR_EL2)
DEFINE_RENAME_SYSREG_RW_FUNCS(gcspr_el2, GCSPR_EL2)
DEFINE_RENAME_SYSREG_RW_FUNCS(gcscr_el1, GCSCR_EL1)
/* DynamIQ Shared Unit power management */
DEFINE_RENAME_SYSREG_RW_FUNCS(clusterpwrdn_el1, CLUSTERPWRDN_EL1)