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Merge changes I1415e402,Ia92cc693,I7a42f72e,I6e75659e,I4c6136c5, ... into integration

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* changes:
  refactor(tc): correlate secure world addresses with platform_def
  feat(tc): add memory node in the device tree
  feat(tc): pass the DTB address to BL33 in R0
  feat(tc): add arm_ffa node in dts
  chore(tc): add dummy entropy to speed up the Linux boot
  feat(tc): choose the DPU address and irq based on the target
  feat(tc): add SCMI power domain and IOMMU toggles
  refactor(tc): move the FVP RoS to a separate file
  feat(tc): factor in FVP/FPGA differences
  feat(tc): introduce an FPGA subvariant and TC3 CPUs
  feat(tc): add TC3 platform definitions
  refactor(tc): sanitise the device tree
  feat(tc): add PMU entry
  feat(tc): allow booting from DRAM
  chore(tc): remove unused hdlcd
  feat(tc): add firmware update secure partition
  feat(tc): add spmc manifest with trusty sp
  refactor(tc): unify all the spmc manifests
  feat(arm): add trusty_sp_fw_config build option
  fix(tc): do not enable MPMM and Aux AMU counters always
  fix(tc): correct interrupts
  feat(tc): interrupt numbers for `smmu_700`
  feat(tc): enable gpu/dpu scmi power domain and also gpu perf domain
This commit is contained in:
Manish V Badarkhe 2024-02-27 10:59:58 +01:00 • committed by TrustedFirmware Code Review
commit df21d41b77
19 changed files with 812 additions and 330 deletions
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6
Makefile
View file

@ -452,8 +452,12 @@ ifneq (${SPD},none)
DTC_CPPFLAGS += -DOPTEE_SP_FW_CONFIG
endif
ifeq ($(findstring trusty_sp,$(ARM_SPMC_MANIFEST_DTS)),trusty_sp)
DTC_CPPFLAGS += -DTRUSTY_SP_FW_CONFIG
endif
ifeq ($(TS_SP_FW_CONFIG),1)
DTC_CPPFLAGS += -DTS_SP_FW_CONFIG
DTC_CPPFLAGS += -DTS_SP_FW_CONFIG
endif
ifneq ($(ARM_BL2_SP_LIST_DTS),)

8
docs/getting_started/build-internals.rst
View file

@ -19,3 +19,11 @@ depends on certain options to be enabled or disabled.
``HANDLE_EA_EL3_FIRST_NS`` is set. Currently only NS world routes EA to EL3 but
in future when Secure/Realm wants to use FFH then they can introduce new macros
which will enable this option implicitly.
- ``OPTEE_SP_FW_CONFIG``: DTC build flag to include OP-TEE as SP in
tb_fw_config device tree. This flag is defined only when
``ARM_SPMC_MANIFEST_DTS`` manifest file name contains pattern optee_sp.
- ``TRUSTY_SP_FW_CONFIG``: DTC build flag to include Trusty as SP in
tb_fw_config device tree. This flag is defined only when
``ARM_SPMC_MANIFEST_DTS`` manifest file name contains pattern trusty_sp.

4
docs/getting_started/build-options.rst
View file

@ -740,10 +740,6 @@ Common build options
1 (do save and restore). 0 is the default. An SPD may set this to 1 if it
wants the timer registers to be saved and restored.
- ``OPTEE_SP_FW_CONFIG``: DTC build flag to include OP-TEE as SP in
tb_fw_config device tree. This flag is defined only when
``ARM_SPMC_MANIFEST_DTS`` manifest file name contains pattern optee_sp.
- ``OVERRIDE_LIBC``: This option allows platforms to override the default libc
for the BL image. It can be either 0 (include) or 1 (remove). The default
value is 0.

454
fdts/tc.dts
View file

@ -6,6 +6,14 @@
/dts-v1/;
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include "platform_def.h"
#include "tc_vers.dtsi"
#if TARGET_FLAVOUR_FVP
#include "tc_fvp.dtsi"
#endif /* TARGET_FLAVOUR_FVP */
/ {
compatible = "arm,tc";
interrupt-parent = <&gic>;
@ -13,11 +21,23 @@
#size-cells = <2>;
aliases {
serial0 = &ap_ns_uart;
serial0 = &os_uart;
};
chosen {
stdout-path = "serial0:115200n8";
stdout-path = STDOUT_PATH;
/*
* Add some dummy entropy for Linux so it
* doesn't delay the boot waiting for it.
*/
rng-seed = <0x01 0x02 0x04 0x05 0x06 0x07 0x08 \
0x01 0x02 0x04 0x05 0x06 0x07 0x08 \
0x01 0x02 0x04 0x05 0x06 0x07 0x08 \
0x01 0x02 0x04 0x05 0x06 0x07 0x08 \
0x01 0x02 0x04 0x05 0x06 0x07 0x08 \
0x01 0x02 0x04 0x05 0x06 0x07 0x08 \
0x01 0x02 0x04 0x05 0x06 0x07 0x08 \
0x01 0x02 0x04 0x05 0x06 0x07 0x08 >;
};
cpus {
@ -50,6 +70,26 @@
core7 {
cpu = <&CPU7>;
};
#if TARGET_FLAVOUR_FPGA && TARGET_PLATFORM <= 2
core8 {
cpu = <&CPU8>;
};
core9 {
cpu = <&CPU9>;
};
core10 {
cpu = <&CPU10>;
};
core11 {
cpu = <&CPU11>;
};
core12 {
cpu = <&CPU12>;
};
core13 {
cpu = <&CPU13>;
};
#endif /* TARGET_FLAVOUR_FPGA && TARGET_PLATFORM <= 2 */
};
};
@ -58,7 +98,7 @@
* These values may be inaccurate.
*/
idle-states {
entry-method = "arm,psci";
entry-method = "psci";
CPU_SLEEP_0: cpu-sleep-0 {
compatible = "arm,idle-state";
@ -85,19 +125,16 @@
mpmm_gear0: counter@0 {
reg = <0>;
enable-at-el3;
};
mpmm_gear1: counter@1 {
reg = <1>;
enable-at-el3;
};
mpmm_gear2: counter@2 {
reg = <2>;
enable-at-el3;
};
};
@ -110,7 +147,7 @@
enable-method = "psci";
clocks = <&scmi_dvfs 0>;
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
capacity-dmips-mhz = <406>;
capacity-dmips-mhz = <LIT_CAPACITY>;
amu = <&amu>;
supports-mpmm;
};
@ -122,7 +159,7 @@
enable-method = "psci";
clocks = <&scmi_dvfs 0>;
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
capacity-dmips-mhz = <406>;
capacity-dmips-mhz = <LIT_CAPACITY>;
amu = <&amu>;
supports-mpmm;
};
@ -132,9 +169,14 @@
compatible = "arm,armv8";
reg = <0x200>;
enable-method = "psci";
clocks = <&scmi_dvfs 0>;
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
capacity-dmips-mhz = <406>;
#if TARGET_PLATFORM <= 2
clocks = <&scmi_dvfs 0>;
capacity-dmips-mhz = <LIT_CAPACITY>;
#elif TARGET_PLATFORM == 3
clocks = <&scmi_dvfs 1>;
capacity-dmips-mhz = <MID_CAPACITY>;
#endif /* TARGET_PLATFORM == 3 */
amu = <&amu>;
supports-mpmm;
};
@ -144,9 +186,14 @@
compatible = "arm,armv8";
reg = <0x300>;
enable-method = "psci";
clocks = <&scmi_dvfs 0>;
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
capacity-dmips-mhz = <406>;
#if TARGET_PLATFORM <= 2
clocks = <&scmi_dvfs 0>;
capacity-dmips-mhz = <LIT_CAPACITY>;
#elif TARGET_PLATFORM == 3
clocks = <&scmi_dvfs 1>;
capacity-dmips-mhz = <MID_CAPACITY>;
#endif /* TARGET_PLATFORM == 3 */
amu = <&amu>;
supports-mpmm;
};
@ -158,7 +205,7 @@
enable-method = "psci";
clocks = <&scmi_dvfs 1>;
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
capacity-dmips-mhz = <912>;
capacity-dmips-mhz = <MID_CAPACITY>;
amu = <&amu>;
supports-mpmm;
};
@ -170,7 +217,7 @@
enable-method = "psci";
clocks = <&scmi_dvfs 1>;
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
capacity-dmips-mhz = <912>;
capacity-dmips-mhz = <MID_CAPACITY>;
amu = <&amu>;
supports-mpmm;
};
@ -180,9 +227,14 @@
compatible = "arm,armv8";
reg = <0x600>;
enable-method = "psci";
clocks = <&scmi_dvfs 1>;
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
capacity-dmips-mhz = <912>;
#if TARGET_PLATFORM <= 2
clocks = <&scmi_dvfs 1>;
capacity-dmips-mhz = <MID_CAPACITY>;
#elif TARGET_PLATFORM == 3
clocks = <&scmi_dvfs 2>;
capacity-dmips-mhz = <BIG_CAPACITY>;
#endif /* TARGET_PLATFORM == 3 */
amu = <&amu>;
supports-mpmm;
};
@ -192,13 +244,85 @@
compatible = "arm,armv8";
reg = <0x700>;
enable-method = "psci";
clocks = <&scmi_dvfs 2>;
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
capacity-dmips-mhz = <1024>;
#if TARGET_FLAVOUR_FPGA && TARGET_PLATFORM <= 2
clocks = <&scmi_dvfs 1>;
capacity-dmips-mhz = <MID_CAPACITY>;
#else
clocks = <&scmi_dvfs 2>;
capacity-dmips-mhz = <BIG_CAPACITY>;
#endif /* TARGET_FLAVOUR_FPGA && TARGET_PLATFORM <= 2 */
amu = <&amu>;
supports-mpmm;
};
#if TARGET_FLAVOUR_FPGA && TARGET_PLATFORM <= 2
CPU8:cpu@800 {
device_type = "cpu";
compatible = "arm,armv8";
reg = <0x800>;
enable-method = "psci";
clocks = <&scmi_dvfs 1>;
capacity-dmips-mhz = <MID_CAPACITY>;
amu = <&amu>;
supports-mpmm;
};
CPU9:cpu@900 {
device_type = "cpu";
compatible = "arm,armv8";
reg = <0x900>;
enable-method = "psci";
clocks = <&scmi_dvfs 2>;
capacity-dmips-mhz = <BIG2_CAPACITY>;
amu = <&amu>;
supports-mpmm;
};
CPU10:cpu@A00 {
device_type = "cpu";
compatible = "arm,armv8";
reg = <0xA00>;
enable-method = "psci";
clocks = <&scmi_dvfs 2>;
capacity-dmips-mhz = <BIG2_CAPACITY>;
amu = <&amu>;
supports-mpmm;
};
CPU11:cpu@B00 {
device_type = "cpu";
compatible = "arm,armv8";
reg = <0xB00>;
enable-method = "psci";
clocks = <&scmi_dvfs 2>;
capacity-dmips-mhz = <BIG2_CAPACITY>;
amu = <&amu>;
supports-mpmm;
};
CPU12:cpu@C00 {
device_type = "cpu";
compatible = "arm,armv8";
reg = <0xC00>;
enable-method = "psci";
clocks = <&scmi_dvfs 3>;
capacity-dmips-mhz = <BIG_CAPACITY>;
amu = <&amu>;
supports-mpmm;
};
CPU13:cpu@D00 {
device_type = "cpu";
compatible = "arm,armv8";
reg = <0xD00>;
enable-method = "psci";
clocks = <&scmi_dvfs 3>;
capacity-dmips-mhz = <BIG_CAPACITY>;
amu = <&amu>;
supports-mpmm;
};
#endif /* TARGET_FLAVOUR_FPGA && TARGET_PLATFORM <= 2 */
};
reserved-memory {
@ -213,10 +337,22 @@
linux,cma-default;
};
optee@0xf8e00000 {
optee {
compatible = "restricted-dma-pool";
reg = <0x00000000 0xf8e00000 0 0x00200000>;
reg = <0x0 TC_NS_OPTEE_BASE 0x0 TC_NS_OPTEE_SIZE>;
};
fwu_mm {
reg = <0x0 TC_NS_FWU_BASE 0x0 TC_NS_FWU_SIZE>;
no-map;
};
};
memory {
device_type = "memory";
reg = <0x0 TC_NS_DRAM1_BASE 0x0 TC_NS_DRAM1_SIZE>,
<HI(PLAT_ARM_DRAM2_BASE) LO(PLAT_ARM_DRAM2_BASE)
HI(TC_NS_DRAM2_SIZE) LO(TC_NS_DRAM2_SIZE)>;
};
psci {
@ -224,13 +360,25 @@
method = "smc";
};
cpu-pmu {
compatible = "arm,armv8-pmuv3";
interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
interrupt-affinity = <&CPU0>, <&CPU1>, <&CPU2>, <&CPU3>,
<&CPU4>, <&CPU5>, <&CPU6>, <&CPU7>
#if TARGET_FLAVOUR_FPGA && TARGET_PLATFORM <= 2
,<&CPU8>, <&CPU9>, <&CPU10>, <&CPU11>,
<&CPU12>, <&CPU13>
#endif /* TARGET_FLAVOUR_FPGA && TARGET_PLATFORM <= 2 */
;
};
sram: sram@6000000 {
compatible = "mmio-sram";
reg = <0x0 0x06000000 0x0 0x8000>;
reg = <0x0 PLAT_ARM_NSRAM_BASE 0x0 PLAT_ARM_NSRAM_SIZE>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x0 0x06000000 0x8000>;
ranges = <0 0x0 PLAT_ARM_NSRAM_BASE PLAT_ARM_NSRAM_SIZE>;
cpu_scp_scmi_mem: scp-shmem@0 {
compatible = "arm,scmi-shmem";
@ -238,22 +386,22 @@
};
};
mbox_db_rx: mhu@45010000 {
mbox_db_rx: mhu@MHU_RX_ADDR() {
compatible = "arm,mhuv2-rx","arm,primecell";
reg = <0x0 0x45010000 0x0 0x1000>;
clocks = <&soc_refclk100mhz>;
reg = <0x0 MHU_RX_ADDR(0x) 0x0 0x1000>;
clocks = <&soc_refclk>;
clock-names = "apb_pclk";
#mbox-cells = <2>;
interrupts = <0 317 4>;
interrupts = <GIC_SPI INT_MBOX_RX IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "mhu_rx";
mhu-protocol = "doorbell";
arm,mhuv2-protocols = <0 1>;
};
mbox_db_tx: mhu@45000000 {
mbox_db_tx: mhu@MHU_TX_ADDR() {
compatible = "arm,mhuv2-tx","arm,primecell";
reg = <0x0 0x45000000 0x0 0x1000>;
clocks = <&soc_refclk100mhz>;
reg = <0x0 MHU_TX_ADDR(0x) 0x0 0x1000>;
clocks = <&soc_refclk>;
clock-names = "apb_pclk";
#mbox-cells = <2>;
interrupt-names = "mhu_tx";
@ -261,12 +409,6 @@
arm,mhuv2-protocols = <0 1>;
};
cmn-pmu {
compatible = "arm,ci-700";
reg = <0x0 0x50000000 0x0 0x10000000>;
interrupts = <0x0 460 0x4>;
};
scmi {
compatible = "arm,scmi";
mbox-names = "tx", "rx";
@ -275,6 +417,13 @@
#address-cells = <1>;
#size-cells = <0>;
#if TC_SCMI_PD_CTRL_EN
scmi_devpd: protocol@11 {
reg = <0x11>;
#power-domain-cells = <1>;
};
#endif /* TC_SCMI_PD_CTRL_EN */
scmi_dvfs: protocol@13 {
reg = <0x13>;
#clock-cells = <1>;
@ -286,30 +435,30 @@
};
};
gic: interrupt-controller@2c010000 {
compatible = "arm,gic-600", "arm,gic-v3";
gic: interrupt-controller@GIC_CTRL_ADDR {
compatible = "arm,gic-v3";
#address-cells = <2>;
#interrupt-cells = <3>;
#size-cells = <2>;
ranges;
interrupt-controller;
reg = <0x0 0x30000000 0 0x10000>, /* GICD */
<0x0 0x30080000 0 0x200000>; /* GICR */
interrupts = <0x1 0x9 0x4>;
<0x0 0x30080000 0 GIC_GICR_OFFSET>; /* GICR */
interrupts = <GIC_PPI 0x9 IRQ_TYPE_LEVEL_LOW>;
};
timer {
compatible = "arm,armv8-timer";
interrupts = <0x1 13 0x8>,
<0x1 14 0x8>,
<0x1 11 0x8>,
<0x1 10 0x8>;
interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
};
soc_refclk100mhz: refclk100mhz {
soc_refclk: refclk {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <100000000>;
clock-frequency = <1000000000>;
clock-output-names = "apb_pclk";
};
@ -320,34 +469,25 @@
clock-output-names = "iofpga_clk";
};
soc_uartclk: uartclk {
soc_uartclk: uartclk {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <50000000>;
clock-frequency = <UARTCLK_FREQ>;
clock-output-names = "uartclk";
};
ap_ns_uart: uart@2A400000 {
/* soc_uart0 on FPGA, ap_ns_uart on FVP */
os_uart: serial@2a400000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x0 0x2A400000 0x0 0x1000>;
interrupts = <0x0 63 0x4>;
clocks = <&soc_uartclk>, <&soc_refclk100mhz>;
reg = <0x0 0x2A400000 0x0 UART_OFFSET>;
interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&soc_uartclk>, <&soc_refclk>;
clock-names = "uartclk", "apb_pclk";
status = "okay";
};
rtc0: rtc@1C170000 {
compatible = "arm,pl031", "arm,primecell";
reg = <0x0 0x1C170000 0x0 0x1000>;
interrupts = <0x0 100 0x4>;
clocks = <&soc_refclk100mhz>;
clock-names = "apb_pclk";
wakeup-source;
};
vencoder {
compatible = "drm,virtual-encoder";
port {
vencoder_in: endpoint {
remote-endpoint = <&dp_pl0_out0>;
@ -355,63 +495,22 @@
};
display-timings {
panel-timing {
clock-frequency = <25175000>;
hactive = <640>;
vactive = <480>;
hfront-porch = <16>;
hback-porch = <48>;
hsync-len = <96>;
vfront-porch = <10>;
vback-porch = <33>;
vsync-len = <2>;
timing-panel {
VENCODER_TIMING;
};
};
};
hdlcd: hdlcd@7ff60000 {
compatible = "arm,hdlcd";
reg = <0x0 0x7ff60000 0x0 0x1000>;
interrupts = <0x0 117 0x4>;
clocks = <&fake_hdlcd_clk>;
clock-names = "pxlclk";
status = "disabled";
port {
hdlcd_out: endpoint {
remote-endpoint = <&vencoder_in>;
};
};
};
fake_hdlcd_clk: fake-hdlcd-clk {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <25175000>;
clock-output-names = "pxlclk";
};
ethernet@18000000 {
compatible = "smsc,lan91c111";
compatible = ETH_COMPATIBLE;
reg = <0x0 0x18000000 0x0 0x10000>;
interrupts = <0 109 4>;
};
interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
kmi@1c060000 {
compatible = "arm,pl050", "arm,primecell";
reg = <0x0 0x001c060000 0x0 0x1000>;
interrupts = <0 197 4>;
clocks = <&bp_clock24mhz>, <&bp_clock24mhz>;
clock-names = "KMIREFCLK", "apb_pclk";
};
kmi@1c070000 {
compatible = "arm,pl050", "arm,primecell";
reg = <0x0 0x001c070000 0x0 0x1000>;
interrupts = <0 103 4>;
clocks = <&bp_clock24mhz>, <&bp_clock24mhz>;
clock-names = "KMIREFCLK", "apb_pclk";
/* FPGA only but will work on FVP. Keep for simplicity */
phy-mode = "mii";
reg-io-width = <2>;
smsc,irq-push-pull;
};
bp_clock24mhz: clock24mhz {
@ -421,11 +520,6 @@
clock-output-names = "bp:clock24mhz";
};
virtio_block@1c130000 {
compatible = "virtio,mmio";
reg = <0x0 0x1c130000 0x0 0x200>;
interrupts = <0 204 4>;
};
sysreg: sysreg@1c010000 {
compatible = "arm,vexpress-sysreg";
@ -445,12 +539,12 @@
mmci@1c050000 {
compatible = "arm,pl180", "arm,primecell";
reg = <0x0 0x001c050000 0x0 0x1000>;
interrupts = <0 107 0x4>,
<0 108 0x4>;
cd-gpios = <&sysreg 0 0>;
interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
MMC_REMOVABLE;
wp-gpios = <&sysreg 1 0>;
bus-width = <8>;
max-frequency = <12000000>;
bus-width = <4>;
max-frequency = <25000000>;
vmmc-supply = <&fixed_3v3>;
clocks = <&bp_clock24mhz>, <&bp_clock24mhz>;
clock-names = "mclk", "apb_pclk";
@ -471,18 +565,23 @@
gpu: gpu@2d000000 {
compatible = "arm,mali-midgard";
reg = <0x0 0x2d000000 0x0 0x200000>;
interrupts = <0 66 4>, <0 67 4>, <0 65 4>;
interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "JOB", "MMU", "GPU";
clocks = <&gpu_clk>, <&gpu_core_clk>;
clock-names = "clk_mali", "shadercores";
clocks = <&gpu_core_clk>;
clock-names = "shadercores";
#if TC_SCMI_PD_CTRL_EN
power-domains = <&scmi_devpd GPU_SCMI_PD_IDX>;
scmi-perf-domain = <3>;
#endif /* TC_SCMI_PD_CTRL_EN */
#if TC_IOMMU_EN
iommus = <&smmu_700 0x200>;
operating-points = <
/* KHz uV */
50000 820000
>;
#endif /* TC_IOMMU_EN */
};
power_model@simple {
power_model_simple {
/*
* Numbers used are irrelevant to Titan,
* it helps suppressing the kernel warnings.
@ -494,27 +593,37 @@
thermal-zone = "";
};
smmu_700: smmu_700@3f000000 {
#if TC_IOMMU_EN
smmu_700: iommu@3f000000 {
#iommu-cells = <1>;
compatible = "arm,smmu-v3";
reg = <0x0 0x3f000000 0x0 0x5000000>;
interrupts = <GIC_SPI 228 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 229 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 230 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "eventq", "cmdq-sync", "gerror";
dma-coherent;
};
#endif /* TC_IOMMU_EN */
dp0: display@2cc00000 {
dp0: display@DPU_ADDR() {
#address-cells = <1>;
#size-cells = <0>;
compatible = "arm,mali-d71";
reg = <0 0x2cc00000 0 0x20000>;
interrupts = <0 69 4>;
reg = <HI(DPU_ADDR(0x)) LO(DPU_ADDR(0x)) 0 0x20000>;
interrupts = <GIC_SPI DPU_IRQ IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "DPU";
clocks = <&scmi_clk 0>;
clock-names = "aclk";
DPU_CLK_ATTR1;
#if TC_IOMMU_EN
iommus = <&smmu_700 0x100>;
#endif /* TC_IOMMU_EN */
#if TC_SCMI_PD_CTRL_EN && (TARGET_PLATFORM != 3)
power-domains = <&scmi_devpd DPU_SCMI_PD_IDX>;
#endif /* TC_SCMI_PD_CTRL_EN && (TARGET_PLATFORM != 3) */
pl0: pipeline@0 {
reg = <0>;
clocks = <&scmi_clk 1>;
clock-names = "pxclk";
DPU_CLK_ATTR2;
pl_id = <0>;
ports {
#address-cells = <1>;
@ -530,8 +639,7 @@
pl1: pipeline@1 {
reg = <1>;
clocks = <&scmi_clk 2>;
clock-names = "pxclk";
DPU_CLK_ATTR3;
pl_id = <1>;
ports {
#address-cells = <1>;
@ -549,7 +657,7 @@
*/
msc0 {
compatible = "arm,mpam-msc";
reg = <0x1 0x00010000 0x0 0x2000>;
reg = <MPAM_ADDR 0x0 0x2000>;
};
ete0 {
@ -592,8 +700,72 @@
cpu = <&CPU7>;
};
trbe0 {
#if TARGET_FLAVOUR_FPGA && TARGET_PLATFORM <= 2
ete8 {
compatible = "arm,embedded-trace-extension";
cpu = <&CPU8>;
};
ete9 {
compatible = "arm,embedded-trace-extension";
cpu = <&CPU9>;
};
ete10 {
compatible = "arm,embedded-trace-extension";
cpu = <&CPU10>;
};
ete11 {
compatible = "arm,embedded-trace-extension";
cpu = <&CPU11>;
};
ete12 {
compatible = "arm,embedded-trace-extension";
cpu = <&CPU12>;
};
ete13 {
compatible = "arm,embedded-trace-extension";
cpu = <&CPU13>;
};
#endif /* TARGET_FLAVOUR_FPGA && TARGET_PLATFORM <= 2 */
trbe {
compatible = "arm,trace-buffer-extension";
interrupts = <1 2 4>;
interrupts = <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>;
};
trusty {
#size-cells = <0x02>;
#address-cells = <0x02>;
ranges = <0x00>;
compatible = "android,trusty-v1";
virtio {
compatible = "android,trusty-virtio-v1";
};
test {
compatible = "android,trusty-test-v1";
};
log {
compatible = "android,trusty-log-v1";
};
irq {
ipi-range = <0x08 0x0f 0x08>;
interrupt-ranges = <0x00 0x0f 0x00 0x10 0x1f 0x01 0x20 0x3f 0x02>;
interrupt-templates = <0x01 0x00 0x8001 0x01 0x01 0x04 0x8001 0x01 0x00 0x04>;
compatible = "android,trusty-irq-v1";
};
};
/* used in U-boot, Linux doesn't care */
arm_ffa {
compatible = "arm,ffa";
method = "smc";
};
};

38
fdts/tc_fvp.dtsi Normal file
View file

@ -0,0 +1,38 @@
/*
* Copyright (c) 2023-2024, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
/ {
rtc@1c170000 {
compatible = "arm,pl031", "arm,primecell";
reg = <0x0 0x1C170000 0x0 0x1000>;
interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&soc_refclk>;
clock-names = "apb_pclk";
};
kmi@1c060000 {
compatible = "arm,pl050", "arm,primecell";
reg = <0x0 0x001c060000 0x0 0x1000>;
interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&bp_clock24mhz>, <&bp_clock24mhz>;
clock-names = "KMIREFCLK", "apb_pclk";
};
kmi@1c070000 {
compatible = "arm,pl050", "arm,primecell";
reg = <0x0 0x001c070000 0x0 0x1000>;
interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&bp_clock24mhz>, <&bp_clock24mhz>;
clock-names = "KMIREFCLK", "apb_pclk";
};
virtio_block@1c130000 {
compatible = "virtio,mmio";
reg = <0x0 0x1c130000 0x0 0x200>;
/* spec lists this wrong */
interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>;
};
};

147
fdts/tc_vers.dtsi Normal file
View file

@ -0,0 +1,147 @@
/*
* Copyright (c) 2023-2024, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
/* If SCMI power domain control is enabled */
#if TC_SCMI_PD_CTRL_EN
#define GPU_SCMI_PD_IDX (PLAT_MAX_CPUS_PER_CLUSTER + 1)
#define DPU_SCMI_PD_IDX (PLAT_MAX_CPUS_PER_CLUSTER + 2)
#endif /* TC_SCMI_PD_CTRL_EN */
/* All perf is normalized against the big core */
#define BIG_CAPACITY 1024
#if TARGET_PLATFORM <= 2
#if TARGET_FLAVOUR_FVP
#define LIT_CAPACITY 406
#define MID_CAPACITY 912
#else /* TARGET_FLAVOUR_FPGA */
#define LIT_CAPACITY 280
#define MID_CAPACITY 775
/* this is an area optimized configuration of the big core */
#define BIG2_CAPACITY 930
#endif /* TARGET_FLAVOUR_FPGA */
#define INT_MBOX_RX 317
#define MHU_TX_ADDR(pref) pref##45000000 /* hex */
#define MHU_RX_ADDR(pref) pref##45010000 /* hex */
#define MPAM_ADDR 0x1 0x00010000 /* 0x1_0001_0000 */
#define UARTCLK_FREQ 5000000
#elif TARGET_PLATFORM == 3
#define LIT_CAPACITY 239
#define MID_CAPACITY 686
#define INT_MBOX_RX 300
#define MHU_TX_ADDR(pref) pref##46040000 /* hex */
#define MHU_RX_ADDR(pref) pref##46140000 /* hex */
#define MPAM_ADDR 0x0 0x5f010000 /* 0x5f01_0000 */
#define UARTCLK_FREQ 3750000
#endif /* TARGET_PLATFORM == 3 */
#if TARGET_FLAVOUR_FVP
#define STDOUT_PATH "serial0:115200n8"
#define GIC_CTRL_ADDR 2c010000
#define GIC_GICR_OFFSET 0x200000
#define UART_OFFSET 0x1000
#define VENCODER_TIMING_CLK 25175000
#define VENCODER_TIMING \
clock-frequency = <VENCODER_TIMING_CLK>; \
hactive = <640>; \
vactive = <480>; \
hfront-porch = <16>; \
hback-porch = <48>; \
hsync-len = <96>; \
vfront-porch = <10>; \
vback-porch = <33>; \
vsync-len = <2>
#define ETH_COMPATIBLE "smsc,lan91c111"
#define MMC_REMOVABLE cd-gpios = <&sysreg 0 0>
#if TARGET_PLATFORM <= 2
#define DPU_ADDR(pref) pref##2cc00000
#define DPU_IRQ 69
#else /* TARGET_PLATFORM >= 3 */
#define DPU_ADDR(pref) pref##4000000000
#define DPU_IRQ 579
#endif /* TARGET_PLATFORM >= 3 */
#else /* TARGET_FLAVOUR_FPGA */
#define STDOUT_PATH "serial0:38400n8"
#define GIC_CTRL_ADDR 30000000
#define GIC_GICR_OFFSET 0x1000000
#define UART_OFFSET 0x10000
/* 1440x3200@120 framebuffer */
#define VENCODER_TIMING_CLK 836000000
#define VENCODER_TIMING \
clock-frequency = <VENCODER_TIMING_CLK>; \
hactive = <1440>; \
vactive = <3200>; \
hfront-porch = <136>; \
hback-porch = <296>; \
hsync-len = <160>; \
vfront-porch = <3>; \
vback-porch = <217>; \
vsync-len = <10>
#define ETH_COMPATIBLE "smsc,lan9115"
#define MMC_REMOVABLE non-removable
#define DPU_ADDR(pref) pref##2cc00000
#define DPU_IRQ 69
#endif /* TARGET_FLAVOUR_FPGA */
/* Use SCMI controlled clocks */
#if TC_DPU_USE_SCMI_CLK
#define DPU_CLK_ATTR1 \
clocks = <&scmi_clk 0>; \
clock-names = "aclk"
#define DPU_CLK_ATTR2 \
clocks = <&scmi_clk 1>; \
clock-names = "pxclk"
#define DPU_CLK_ATTR3 \
clocks = <&scmi_clk 2>; \
clock-names = "pxclk" \
/* Use fixed clocks */
#else /* !TC_DPU_USE_SCMI_CLK */
#define DPU_CLK_ATTR1 \
clocks = <&dpu_aclk>; \
clock-names = "aclk"
#define DPU_CLK_ATTR2 \
clocks = <&dpu_pixel_clk>, <&dpu_aclk>; \
clock-names = "pxclk", "aclk"
#define DPU_CLK_ATTR3 DPU_CLK_ATTR2
#endif /* !TC_DPU_USE_SCMI_CLK */
/ {
#if TARGET_PLATFORM <= 2
cmn-pmu {
compatible = "arm,ci-700";
reg = <0x0 0x50000000 0x0 0x10000000>;
interrupts = <GIC_SPI 460 IRQ_TYPE_LEVEL_HIGH>;
};
#endif /* TARGET_PLATFORM <= 2 */
#if !TC_DPU_USE_SCMI_CLK
dpu_aclk: dpu_aclk {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <VENCODER_TIMING_CLK>;
clock-output-names = "fpga:dpu_aclk";
};
dpu_pixel_clk: dpu-pixel-clk {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <VENCODER_TIMING_CLK>;
clock-output-names = "pxclk";
};
#endif /* !TC_DPU_USE_SCMI_CLK */
};

5
include/lib/utils_def.h
View file

@ -1,5 +1,5 @@
/*
* Copyright (c) 2016-2023, Arm Limited and Contributors. All rights reserved.
* Copyright (c) 2016-2024, Arm Limited and Contributors. All rights reserved.
* Copyright (c) 2020, NVIDIA Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
@ -53,6 +53,9 @@
#define GENMASK GENMASK_32
#endif
#define HI(addr) (addr >> 32)
#define LO(addr) (addr & 0xffffffff)
/*
* This variant of div_round_up can be used in macro definition but should not
* be used in C code as the `div` parameter is evaluated twice.

7
include/plat/arm/common/fconf_arm_sp_getter.h
View file

@ -1,5 +1,5 @@
/*
* Copyright (c) 2020, Arm Limited and Contributors. All rights reserved.
* Copyright (c) 2020-2024, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -9,12 +9,17 @@
#include <common/tbbr/tbbr_img_def.h>
#include <lib/fconf/fconf.h>
#include <platform_def.h>
#include <tools_share/uuid.h>
/* arm_sp getter */
#define arm__sp_getter(prop) arm_sp.prop
#ifdef PLAT_ARM_SP_MAX_SIZE
#define ARM_SP_MAX_SIZE PLAT_ARM_SP_MAX_SIZE
#else
#define ARM_SP_MAX_SIZE U(0xb0000)
#endif /* PLAT_ARM_SP_MAX_SIZE */
#define ARM_SP_OWNER_NAME_LEN U(8)
struct arm_sp_t {

61
plat/arm/board/tc/fdts/tc_spmc_common_sp_manifest.dtsi Normal file
View file

@ -0,0 +1,61 @@
/*
* Copyright (c) 2023-2024, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
/*
* Secure world memory map. For a full view of the DRAM map, see platform_def.h
*
* 0xf900_c000 ------------------
* | ... |
* 0xf901_c000 ------------------
* | (63MB) | Trusty (=/=> OP-TEE)
* 0xfcf1_c000 ------------------
* | ... |
* 0xfd00_0000 ------------------
* | (512K) | Hafnium
* 0xfd08_0000 ------------------
* | ... | Hafnium stack
* 0xfd28_0000 ------------------
* | (11MB) | OP-TEE (=/=> Trusty)
* 0xfdd8_0000 ------------------
* | ... |
* 0xfde0_0000 ------------------
* | (2MB) | Firmware Upgrade
* 0xfec0_0000 ------------------
* | (2MB) | Crypto
* 0xfee0_0000 ------------------
* | (2MB) | Internal Truested Storage
* 0xff00_0000 ------------------
*/
&hafnium {
vm1 {
is_ffa_partition;
vcpu_count = <8>;
/* partition information filled in separately */
};
#ifdef TS_SP_FW_CONFIG
vm2 {
is_ffa_partition;
debug_name = "internal-trusted-storage";
load_address = <0xfee00000>;
vcpu_count = <1>;
mem_size = <0x200000>; /* 2MB TZC DRAM */
};
vm3 {
is_ffa_partition;
debug_name = "crypto";
load_address = <0xfec00000>;
vcpu_count = <1>;
mem_size = <0x200000>; /* 2MB TZC DRAM */
};
vm4 {
is_ffa_partition;
debug_name = "firmware-update";
load_address = <0xfde00000>;
vcpu_count = <1>;
mem_size = <0xe00000>; /* 14MB TZC DRAM */
};
#endif
};

48
plat/arm/board/tc/fdts/tc_spmc_manifest.dts → plat/arm/board/tc/fdts/tc_spmc_manifest.dtsi
View file

@ -1,9 +1,9 @@
/*
* Copyright (c) 2020-2023, Arm Limited. All rights reserved.
* Copyright (c) 2020-2024, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
/dts-v1/;
#include <platform_def.h>
/ {
compatible = "arm,ffa-core-manifest-1.0";
@ -20,36 +20,9 @@
binary_size = <0x80000>;
};
hypervisor {
hafnium:hypervisor {
compatible = "hafnium,hafnium";
vm1 {
is_ffa_partition;
debug_name = "cactus-primary";
load_address = <0xfe000000>;
vcpu_count = <8>;
mem_size = <1048576>;
};
vm2 {
is_ffa_partition;
debug_name = "cactus-secondary";
load_address = <0xfe100000>;
vcpu_count = <8>;
mem_size = <1048576>;
};
vm3 {
is_ffa_partition;
debug_name = "cactus-tertiary";
load_address = <0xfe200000>;
vcpu_count = <1>;
mem_size = <1048576>;
};
vm4 {
is_ffa_partition;
debug_name = "ivy";
load_address = <0xfe600000>;
vcpu_count = <1>;
mem_size = <1048576>;
};
/* filled in in top level .dts */
};
cpus {
@ -117,16 +90,21 @@
};
};
/* the full secure world range */
memory@0 {
device_type = "memory";
reg = <0x0 0xfd000000 0x0 0x2000000>,
<0x0 0x7000000 0x0 0x1000000>,
reg = <0x0 TC_TZC_DRAM1_BASE 0x0 TC_TZC_DRAM1_SIZE>,
<0x0 0xff000000 0x0 0x1000000>;
};
memory@1 {
device_type = "ns-memory";
reg = <0x00008800 0x80000000 0x0 0x7f000000>,
<0x0 0x88000000 0x1 0x00000000>;
reg =
#ifdef TS_SP_FW_CONFIG
<0x0 0x08000000 0x0 0x4000000>,
#endif /* TS_SP_FW_CONFIG */
<0x0 TC_NS_DRAM1_BASE 0x0 TC_NS_DRAM1_SIZE>,
<HI(PLAT_ARM_DRAM2_BASE) LO(PLAT_ARM_DRAM2_BASE)
HI(TC_NS_DRAM2_SIZE) LO(TC_NS_DRAM2_SIZE)>;
};
};

128
plat/arm/board/tc/fdts/tc_spmc_optee_sp_manifest.dts
View file

@ -1,129 +1,17 @@
/*
* Copyright (c) 2020-2023, Arm Limited. All rights reserved.
* Copyright (c) 2020-2024, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
/dts-v1/;
/ {
compatible = "arm,ffa-core-manifest-1.0";
#address-cells = <2>;
#size-cells = <2>;
#include <tc_spmc_manifest.dtsi>
#include <tc_spmc_common_sp_manifest.dtsi>
attribute {
spmc_id = <0x8000>;
maj_ver = <0x1>;
min_ver = <0x2>;
exec_state = <0x0>;
load_address = <0x0 0xfd000000>;
entrypoint = <0x0 0xfd000000>;
binary_size = <0x80000>;
};
hypervisor {
compatible = "hafnium,hafnium";
vm1 {
is_ffa_partition;
debug_name = "op-tee";
load_address = <0xfd280000>;
vcpu_count = <8>;
#ifdef TS_SP_FW_CONFIG
mem_size = <26738688>; /* 25MB TZC DRAM */
#else
mem_size = <30928896>; /* 29MB TZC DRAM */
#endif
};
#ifdef TS_SP_FW_CONFIG
vm2 {
is_ffa_partition;
debug_name = "internal-trusted-storage";
load_address = <0xfee00000>;
vcpu_count = <1>;
mem_size = <2097152>; /* 2MB TZC DRAM */
};
vm3 {
is_ffa_partition;
debug_name = "crypto";
load_address = <0xfec00000>;
vcpu_count = <1>;
mem_size = <2097152>; /* 2MB TZC DRAM */
};
#endif
};
cpus {
#address-cells = <0x2>;
#size-cells = <0x0>;
CPU0:cpu@0 {
device_type = "cpu";
compatible = "arm,armv8";
reg = <0x0 0x0>;
enable-method = "psci";
};
/*
* SPMC (Hafnium) requires secondary cpu nodes are declared in
* descending order
*/
CPU7:cpu@700 {
device_type = "cpu";
compatible = "arm,armv8";
reg = <0x0 0x700>;
enable-method = "psci";
};
CPU6:cpu@600 {
device_type = "cpu";
compatible = "arm,armv8";
reg = <0x0 0x600>;
enable-method = "psci";
};
CPU5:cpu@500 {
device_type = "cpu";
compatible = "arm,armv8";
reg = <0x0 0x500>;
enable-method = "psci";
};
CPU4:cpu@400 {
device_type = "cpu";
compatible = "arm,armv8";
reg = <0x0 0x400>;
enable-method = "psci";
};
CPU3:cpu@300 {
device_type = "cpu";
compatible = "arm,armv8";
reg = <0x0 0x300>;
enable-method = "psci";
};
CPU2:cpu@200 {
device_type = "cpu";
compatible = "arm,armv8";
reg = <0x0 0x200>;
enable-method = "psci";
};
CPU1:cpu@100 {
device_type = "cpu";
compatible = "arm,armv8";
reg = <0x0 0x100>;
enable-method = "psci";
};
};
memory@0 {
device_type = "memory";
reg = <0x0 0xfd000000 0x0 0x2000000>;
};
memory@1 {
device_type = "ns-memory";
reg = <0x0 0x80000000 0x0 0x79000000>,
<0x80 0x80000000 0x1 0x80000000>;
&hafnium {
vm1 {
debug_name = "op-tee";
load_address = <0xfd280000>;
mem_size = <0xb00000>; /* 11MB TZC DRAM */
};
};

41
plat/arm/board/tc/fdts/tc_spmc_test_manifest.dts Normal file
View file

@ -0,0 +1,41 @@
/*
* Copyright (c) 2023-2024, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
/dts-v1/;
#include <tc_spmc_manifest.dtsi>
/ {
hypervisor {
vm1 {
is_ffa_partition;
debug_name = "cactus-primary";
load_address = <0xfe000000>;
vcpu_count = <8>;
mem_size = <1048576>;
};
vm2 {
is_ffa_partition;
debug_name = "cactus-secondary";
load_address = <0xfe100000>;
vcpu_count = <8>;
mem_size = <1048576>;
};
vm3 {
is_ffa_partition;
debug_name = "cactus-tertiary";
load_address = <0xfe200000>;
vcpu_count = <1>;
mem_size = <1048576>;
};
vm4 {
is_ffa_partition;
debug_name = "ivy";
load_address = <0xfe600000>;
vcpu_count = <1>;
mem_size = <1048576>;
};
};
};

17
plat/arm/board/tc/fdts/tc_spmc_trusty_sp_manifest.dts Normal file
View file

@ -0,0 +1,17 @@
/*
* Copyright (c) 2023-2024, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
/dts-v1/;
#include <tc_spmc_manifest.dtsi>
#include <tc_spmc_common_sp_manifest.dtsi>
&hafnium {
vm1 {
debug_name = "trusty";
load_address = <0xf901c000>;
mem_size = <0x3f00000>; /* 64MB TZC DRAM - 1MB align */
};
};

11
plat/arm/board/tc/fdts/tc_tb_fw_config.dts
View file

@ -1,5 +1,5 @@
/*
* Copyright (c) 2020-2021, Arm Limited. All rights reserved.
* Copyright (c) 2020-2024, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -41,12 +41,21 @@
uuid = "d9df52d5-16a2-4bb2-9aa4-d26d3b84e8c0";
load-address = <0xfec00000>;
};
firmware-update {
uuid = "6823a838-1b06-470e-9774-0cce8bfb53fd";
load-address = <0xfde00000>;
};
#endif
#if OPTEE_SP_FW_CONFIG
op-tee {
uuid = "486178e0-e7f8-11e3-bc5e-0002a5d5c51b";
load-address = <0xfd280000>;
};
#elif TRUSTY_SP_FW_CONFIG
trusty {
uuid = "40ee25f0-a2bc-304c-8c4c-a173c57d8af1";
load-address = <0xf901c000>;
};
#else
cactus-primary {
uuid = "b4b5671e-4a90-4fe1-b81f-fb13dae1dacb";

84
plat/arm/board/tc/include/platform_def.h
View file

@ -17,8 +17,6 @@
#include <plat/arm/soc/common/soc_css_def.h>
#include <plat/common/common_def.h>
#define PLATFORM_CORE_COUNT 8
#define PLAT_ARM_TRUSTED_SRAM_SIZE 0x00080000 /* 512 KB */
/*
@ -30,6 +28,12 @@
* - Region to load secure partitions
*
*
* 0xf8a0_0000 ------------------ TC_NS_FWU_BASE
* | FWU shmem |
* | (4MB) |
* 0xf8e0_0000 ------------------ TC_NS_OPTEE_BASE
* | OP-TEE shmem |
* | (2MB) |
* 0xF900_0000 ------------------ TC_TZC_DRAM1_BASE
* | |
* | SPMC |
@ -46,7 +50,7 @@
*/
#define TC_TZC_DRAM1_BASE (ARM_AP_TZC_DRAM1_BASE - \
TC_TZC_DRAM1_SIZE)
#define TC_TZC_DRAM1_SIZE 96 * SZ_1M /* 96 MB */
#define TC_TZC_DRAM1_SIZE (96 * SZ_1M) /* 96 MB */
#define TC_TZC_DRAM1_END (TC_TZC_DRAM1_BASE + \
TC_TZC_DRAM1_SIZE - 1)
@ -54,8 +58,12 @@
#define TC_NS_DRAM1_SIZE (ARM_DRAM1_SIZE - \
ARM_TZC_DRAM1_SIZE - \
TC_TZC_DRAM1_SIZE)
#define TC_NS_DRAM1_END (TC_NS_DRAM1_BASE + \
TC_NS_DRAM1_SIZE - 1)
#define TC_NS_DRAM1_END (TC_NS_DRAM1_BASE + TC_NS_DRAM1_SIZE - 1)
#define TC_NS_OPTEE_SIZE (2 * SZ_1M)
#define TC_NS_OPTEE_BASE (TC_NS_DRAM1_BASE + TC_NS_DRAM1_SIZE - TC_NS_OPTEE_SIZE)
#define TC_NS_FWU_SIZE (4 * SZ_1M)
#define TC_NS_FWU_BASE (TC_NS_OPTEE_BASE - TC_NS_FWU_SIZE)
/*
* Mappings for TC DRAM1 (non-secure) and TC TZC DRAM1 (secure)
@ -186,6 +194,13 @@
#define TC_DEVICE_BASE 0x21000000
#define TC_DEVICE_SIZE 0x5f000000
#if defined(TARGET_FLAVOUR_FPGA)
#undef V2M_FLASH0_BASE
#undef V2M_FLASH0_SIZE
#define V2M_FLASH0_BASE UL(0x0C000000)
#define V2M_FLASH0_SIZE UL(0x02000000)
#endif
// TC_MAP_DEVICE covers different peripherals
// available to the platform
#define TC_MAP_DEVICE MAP_REGION_FLAT( \
@ -206,12 +221,24 @@
#define PLAT_ARM_TRUSTED_ROM_SIZE (0x00080000 - PLAT_ARM_TRUSTED_ROM_BASE)
#define PLAT_ARM_NSRAM_BASE 0x06000000
#if TARGET_FLAVOUR_FVP
#define PLAT_ARM_NSRAM_SIZE 0x00080000 /* 512KB */
#else /* TARGET_FLAVOUR_FPGA */
#define PLAT_ARM_NSRAM_SIZE 0x00008000 /* 64KB */
#endif /* TARGET_FLAVOUR_FPGA */
#if TARGET_PLATFORM <= 2
#define PLAT_ARM_DRAM2_BASE ULL(0x8080000000)
#elif TARGET_PLATFORM == 3
#define PLAT_ARM_DRAM2_BASE ULL(0x880000000)
#endif /* TARGET_PLATFORM == 3 */
#define PLAT_ARM_DRAM2_SIZE ULL(0x180000000)
#define PLAT_ARM_DRAM2_END (PLAT_ARM_DRAM2_BASE + PLAT_ARM_DRAM2_SIZE - 1ULL)
#define TC_NS_MTE_SIZE (256 * SZ_1M)
/* the SCP puts the carveout at the end of DRAM2 */
#define TC_NS_DRAM2_SIZE (PLAT_ARM_DRAM2_SIZE - TC_NS_MTE_SIZE)
#define PLAT_ARM_G1S_IRQ_PROPS(grp) CSS_G1S_INT_PROPS(grp)
#define PLAT_ARM_G0_IRQ_PROPS(grp) ARM_G0_IRQ_PROPS(grp), \
INTR_PROP_DESC(SBSA_SECURE_WDOG_INTID, \
@ -221,6 +248,8 @@
#define PLAT_ARM_SP_IMAGE_STACK_BASE (PLAT_SP_IMAGE_NS_BUF_BASE + \
PLAT_SP_IMAGE_NS_BUF_SIZE)
#define PLAT_ARM_SP_MAX_SIZE U(0x2000000)
/*******************************************************************************
* Memprotect definitions
******************************************************************************/
@ -252,11 +281,21 @@
CSS_SCMI_PAYLOAD_SIZE_MAX)
#define PLAT_ARM_CLUSTER_COUNT U(1)
#if TARGET_FLAVOUR_FPGA && TARGET_PLATFORM == 2
#define PLAT_MAX_CPUS_PER_CLUSTER U(14)
#else /* TARGET_FLAVOUR_FPGA && TARGET_PLATFORM == 2 */
#define PLAT_MAX_CPUS_PER_CLUSTER U(8)
#endif /* TARGET_FLAVOUR_FPGA && TARGET_PLATFORM == 2 */
#define PLAT_MAX_PE_PER_CPU U(1)
#define PLATFORM_CORE_COUNT (PLAT_MAX_CPUS_PER_CLUSTER * PLAT_ARM_CLUSTER_COUNT)
/* Message Handling Unit (MHU) base addresses */
#define PLAT_CSS_MHU_BASE UL(0x45400000)
#if TARGET_PLATFORM <= 2
#define PLAT_CSS_MHU_BASE UL(0x45400000)
#elif TARGET_PLATFORM == 3
#define PLAT_CSS_MHU_BASE UL(0x46000000)
#endif /* TARGET_PLATFORM == 3 */
#define PLAT_MHUV2_BASE PLAT_CSS_MHU_BASE
/* TC2: AP<->RSS MHUs */
@ -335,16 +374,41 @@
/* UART related constants */
#define TC_UART0 0x2a400000
#define TC_UART1 0x2a410000
/*
* TODO: if any more undefs are needed, it's better to consider dropping the
* board_css_def.h include above
*/
#undef PLAT_ARM_BOOT_UART_BASE
#define PLAT_ARM_BOOT_UART_BASE 0x2A410000
#undef PLAT_ARM_RUN_UART_BASE
#define PLAT_ARM_RUN_UART_BASE 0x2A400000
#undef PLAT_ARM_SP_MIN_RUN_UART_BASE
#define PLAT_ARM_SP_MIN_RUN_UART_BASE PLAT_ARM_RUN_UART_BASE
#undef PLAT_ARM_CRASH_UART_BASE
#undef PLAT_ARM_BOOT_UART_CLK_IN_HZ
#undef PLAT_ARM_RUN_UART_CLK_IN_HZ
#if TARGET_FLAVOUR_FVP
#define PLAT_ARM_BOOT_UART_BASE TC_UART1
#define TC_UARTCLK 7372800
#else /* TARGET_FLAVOUR_FPGA */
#define PLAT_ARM_BOOT_UART_BASE TC_UART0
#if TARGET_PLATFORM <= 2
#define TC_UARTCLK 5000000
#elif TARGET_PLATFORM >= 3
#define TC_UARTCLK 3750000
#endif /* TARGET_PLATFORM >= 3 */
#undef ARM_CONSOLE_BAUDRATE
#define ARM_CONSOLE_BAUDRATE 38400
#endif /* TARGET_FLAVOUR_FPGA */
#define PLAT_ARM_RUN_UART_BASE TC_UART0
#define PLAT_ARM_SP_MIN_RUN_UART_BASE PLAT_ARM_RUN_UART_BASE
#define PLAT_ARM_CRASH_UART_BASE PLAT_ARM_RUN_UART_BASE
#define PLAT_ARM_BOOT_UART_CLK_IN_HZ TC_UARTCLK
#define PLAT_ARM_RUN_UART_CLK_IN_HZ TC_UARTCLK
#endif /* PLATFORM_DEF_H */

50
plat/arm/board/tc/platform.mk
View file

@ -1,24 +1,38 @@
# Copyright (c) 2021-2023, Arm Limited. All rights reserved.
# Copyright (c) 2021-2024, Arm Limited. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
include common/fdt_wrappers.mk
ifeq ($(TARGET_PLATFORM), 0)
$(error Platform ${PLAT}$(TARGET_PLATFORM) is deprecated.)
endif
TARGET_FLAVOUR := fvp
# DPU with SCMI may not necessarily work, so allow its independence
TC_DPU_USE_SCMI_CLK := 1
# SCMI power domain control enable
TC_SCMI_PD_CTRL_EN := 1
# IOMMU: Enable the use of system or individual MMUs
TC_IOMMU_EN := 1
ifeq ($(TARGET_PLATFORM), 1)
ifneq ($(shell expr $(TARGET_PLATFORM) \<= 1), 0)
$(warning Platform ${PLAT}$(TARGET_PLATFORM) is deprecated. \
Some of the features might not work as expected)
endif
ifeq ($(shell expr $(TARGET_PLATFORM) \<= 2), 0)
$(error TARGET_PLATFORM must be less than or equal to 2)
ifeq ($(shell expr $(TARGET_PLATFORM) \<= 3), 0)
$(error TARGET_PLATFORM must be less than or equal to 3)
endif
$(eval $(call add_define,TARGET_PLATFORM))
ifeq ($(filter ${TARGET_FLAVOUR}, fvp fpga),)
$(error TARGET_FLAVOUR must be fvp or fpga)
endif
$(eval $(call add_defines, \
TARGET_PLATFORM \
TARGET_FLAVOUR_$(call uppercase,${TARGET_FLAVOUR}) \
TC_DPU_USE_SCMI_CLK \
TC_SCMI_PD_CTRL_EN \
TC_IOMMU_EN \
))
CSS_LOAD_SCP_IMAGES := 1
@ -70,7 +84,8 @@ override ARM_PLAT_MT := 1
TC_BASE = plat/arm/board/tc
PLAT_INCLUDES += -I${TC_BASE}/include/
PLAT_INCLUDES += -I${TC_BASE}/include/ \
-I${TC_BASE}/fdts/
# CPU libraries for TARGET_PLATFORM=1
ifeq (${TARGET_PLATFORM}, 1)
@ -86,6 +101,13 @@ TC_CPU_SOURCES += lib/cpus/aarch64/cortex_a520.S \
lib/cpus/aarch64/cortex_x4.S
endif
# CPU libraries for TARGET_PLATFORM=3
ifeq (${TARGET_PLATFORM}, 3)
TC_CPU_SOURCES += lib/cpus/aarch64/cortex_a520.S \
lib/cpus/aarch64/cortex_chaberton.S \
lib/cpus/aarch64/cortex_blackhawk.S
endif
INTERCONNECT_SOURCES := ${TC_BASE}/tc_interconnect.c
PLAT_BL_COMMON_SOURCES += ${TC_BASE}/tc_plat.c \
@ -133,7 +155,7 @@ $(eval $(call TOOL_ADD_PAYLOAD,${TB_FW_CONFIG},--tb-fw-config,${TB_FW_CONFIG}))
ifeq (${SPD},spmd)
ifeq ($(ARM_SPMC_MANIFEST_DTS),)
ARM_SPMC_MANIFEST_DTS := ${TC_BASE}/fdts/${PLAT}_spmc_manifest.dts
ARM_SPMC_MANIFEST_DTS := ${TC_BASE}/fdts/${PLAT}_spmc_test_manifest.dts
endif
FDT_SOURCES += ${ARM_SPMC_MANIFEST_DTS}
@ -159,11 +181,11 @@ override CTX_INCLUDE_PAUTH_REGS := 1
override ENABLE_SPE_FOR_NS := 0
override ENABLE_FEAT_AMU := 1
override ENABLE_AMU_AUXILIARY_COUNTERS := 1
override ENABLE_AMU_FCONF := 1
ENABLE_AMU_AUXILIARY_COUNTERS := 1
ENABLE_AMU_FCONF := 1
override ENABLE_MPMM := 1
override ENABLE_MPMM_FCONF := 1
ENABLE_MPMM := 1
ENABLE_MPMM_FCONF := 1
# Include Measured Boot makefile before any Crypto library makefile.
# Crypto library makefile may need default definitions of Measured Boot build

21
plat/arm/board/tc/tc_bl31_setup.c
View file

@ -1,5 +1,5 @@
/*
* Copyright (c) 2020-2023, Arm Limited and Contributors. All rights reserved.
* Copyright (c) 2020-2024, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -75,6 +75,25 @@ scmi_channel_plat_info_t *plat_css_get_scmi_info(unsigned int channel_id)
void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
u_register_t arg2, u_register_t arg3)
{
/*
* Pass the hw_config to BL33 in R0. You'll notice that
* arm_bl31_early_platform_setup does something similar but only behind
* ARM_LINUX_KERNEL_AS_BL33 and we want to pass the DTB even to a
* bootloader. Lucky for us, it copies the ep_info BL2 gave us to BL33
* unconditionally in the generic case so hijack that.
* TODO: this goes away with firmware handoff when it will be proper
*/
bl_params_node_t *bl_params = ((bl_params_t *)arg0)->head;
while (bl_params != NULL) {
if (bl_params->image_id == BL33_IMAGE_ID) {
bl_params->ep_info->args.arg0 = arg2;
break;
}
bl_params = bl_params->next_params_info;
}
arm_bl31_early_platform_setup((void *)arg0, arg1, arg2, (void *)arg3);
/* Fill the properties struct with the info from the config dtb */

1
plat/arm/board/tc/tc_plat.c
View file

@ -30,6 +30,7 @@
#if IMAGE_BL1
const mmap_region_t plat_arm_mmap[] = {
ARM_MAP_SHARED_RAM,
TC_MAP_NS_DRAM1,
TC_FLASH0_RO,
TC_MAP_DEVICE,
{0}

11
plat/arm/board/tc/tc_topology.c
View file

@ -1,11 +1,12 @@
/*
* Copyright (c) 2020, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2020-2024, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <plat/arm/common/plat_arm.h>
#include <plat/arm/css/common/css_pm.h>
#include <platform_def.h>
/******************************************************************************
* The power domain tree descriptor.
@ -36,6 +37,14 @@ const uint32_t plat_css_core_pos_to_scmi_dmn_id_map[] = {
(SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x5)),
(SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x6)),
(SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x7)),
#if PLATFORM_CORE_COUNT == 14
(SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x8)),
(SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x9)),
(SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0xA)),
(SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0xB)),
(SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0xC)),
(SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0xD)),
#endif /* PLATFORM_CORE_COUNT == 14 */
};
/*******************************************************************************