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Merge changes Ibb593369,I9cc984dd into integration

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* changes:
  fix(el3_runtime): allow SErrors when executing in EL3
  fix(el3_runtime): do not save scr_el3 during EL3 entry
This commit is contained in:
Bipin Ravi 2022-12-15 16:51:32 +01:00 • committed by TrustedFirmware Code Review
commit 309b18bdc9
2 changed files with 14 additions and 3 deletions
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7
bl31/aarch64/runtime_exceptions.S
View file

@ -493,15 +493,16 @@ smc_handler64:
msr spsel, #MODE_SP_EL0
/*
* Save the SPSR_EL3, ELR_EL3, & SCR_EL3 in case there is a world
* Save the SPSR_EL3 and ELR_EL3 in case there is a world
* switch during SMC handling.
* TODO: Revisit if all system registers can be saved later.
*/
mrs x16, spsr_el3
mrs x17, elr_el3
mrs x18, scr_el3
stp x16, x17, [x6, #CTX_EL3STATE_OFFSET + CTX_SPSR_EL3]
str x18, [x6, #CTX_EL3STATE_OFFSET + CTX_SCR_EL3]
/* Load SCR_EL3 */
mrs x18, scr_el3
/* Clear flag register */
mov x7, xzr

10
lib/el3_runtime/aarch64/context.S
View file

@ -787,6 +787,15 @@ func fpregs_context_restore
endfunc fpregs_context_restore
#endif /* CTX_INCLUDE_FPREGS */
/*
* Set SCR_EL3.EA bit to enable SErrors at EL3
*/
.macro enable_serror_at_el3
mrs x8, scr_el3
orr x8, x8, #SCR_EA_BIT
msr scr_el3, x8
.endm
/*
* Set the PSTATE bits not set when the exception was taken as
* described in the AArch64.TakeException() pseudocode function
@ -917,6 +926,7 @@ endfunc fpregs_context_restore
*/
func prepare_el3_entry
save_gp_pmcr_pauth_regs
enable_serror_at_el3
/*
* Set the PSTATE bits not described in the Aarch64.TakeException
* pseudocode to their default values.