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Merge changes I2b23e7c8,I779587af,Ic46de7a4,If753e987,I00171b05, ... into integration

Browse source 
* changes:
  fix(layerscape): unlock write access SMMU_CBn_ACTLR
  fix(nxp-ddr): add checking return value
  feat(lx2): enable OCRAM ECC
  fix(nxp-tools): fix coverity issue
  fix(nxp-ddr): fix coverity issue
  fix(nxp-ddr): fix underrun coverity issue
  fix(nxp-drivers): fix sd secure boot failure
  feat(lx2): support more variants
  fix(lx2): init global data before using it
  fix(ls1046a): 4 keys secureboot failure resolved
  fix(nxp-crypto): fix secure boot assert inclusion
  fix(nxp-crypto): fix coverity issue
  fix(nxp-drivers): fix fspi coverity issue
  fix(nxp-drivers): fix tzc380 memory regions config
  fix(layerscape): fix nv_storage assert checking
  fix(nxp-ddr): apply Max CDD values for warm boot
  fix(nxp-ddr): use CDDWW for write to read delay
  fix(layerscape): fix errata a008850
This commit is contained in:
Madhukar Pappireddy 2022-12-15 16:38:07 +01:00 • committed by TrustedFirmware Code Review
commit 79664cfcf9
25 changed files with 225 additions and 61 deletions
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2
drivers/nxp/auth/csf_hdr_parser/csf_hdr_parser.c
View file

@ -38,7 +38,7 @@ static const uint8_t barker_code[CSF_BARKER_LEN] = { 0x68, 0x39, 0x27, 0x81 };
/* Flag to indicate if values are there in rotpk_hash_table */
bool rotpk_not_dpld = true;
uint8_t rotpk_hash_table[MAX_KEY_ENTRIES][SHA256_BYTES];
uint8_t rotpk_hash_table[MAX_KEY_ENTRIES][SHA256_BYTES] __aligned(CACHE_WRITEBACK_GRANULE);
uint32_t num_rotpk_hash_entries;
/*

9
drivers/nxp/crypto/caam/src/jobdesc.c
View file

@ -1,5 +1,5 @@
/*
* Copyright 2017-2020 NXP
* Copyright 2017-2022 NXP
*
* SPDX-License-Identifier: BSD-3-Clause
*
@ -11,13 +11,13 @@
#include <stdio.h>
#include <stdlib.h>
#include <assert.h>
#include "caam.h"
#include <common/debug.h>
#include "jobdesc.h"
#include "rsa.h"
#include "sec_hw_specific.h"
/* Return Length of desctiptr from first word */
uint32_t desc_length(uint32_t *desc)
{
@ -41,6 +41,8 @@ void desc_add_word(uint32_t *desc, uint32_t word)
{
uint32_t len = desc_length(desc);
assert((len + 1) < MAX_DESC_SIZE_WORDS);
/* Add Word at Last */
uint32_t *last = desc + len;
*last = word;
@ -54,6 +56,9 @@ void desc_add_ptr(uint32_t *desc, phys_addr_t *ptr)
{
uint32_t len = desc_length(desc);
assert((len + (uint32_t) (sizeof(phys_addr_t) / sizeof(uint32_t)))
< MAX_DESC_SIZE_WORDS);
/* Add Word at Last */
phys_addr_t *last = (phys_addr_t *) (desc + len);

2
drivers/nxp/ddr/nxp-ddr/regs.c
View file

@ -1302,7 +1302,7 @@ static unsigned int skip_caslat(unsigned int tckmin_ps,
return 0;
}
if ((bin[i].taamin_ps[j] == 0) ||
if (((bin[i].taamin_ps[j] == 0) && j > 0) ||
(bin[i].taamin_ps[j] > taamin_ps && j > 0)) {
j--;
}

91
drivers/nxp/ddr/phy-gen2/phy.c
View file

@ -241,12 +241,6 @@ static void get_cdd_val(uint16_t **phy_ptr, uint32_t rank, uint32_t freq,
rwmax = tmp;
}
tmp = wrmax;
wrmax = cdd[56];
if (tmp > wrmax) {
wrmax = tmp;
}
break;
case 2U:
@ -276,15 +270,7 @@ static void get_cdd_val(uint16_t **phy_ptr, uint32_t rank, uint32_t freq,
rwmax = tmp;
}
buf[0] = cdd[56];
buf[1] = cdd[55];
buf[2] = cdd[52];
buf[3] = cdd[51];
tmp = wrmax;
wrmax = findmax(buf, 4U);
if (tmp > wrmax) {
wrmax = tmp;
}
wrmax = wwmax;
break;
@ -310,12 +296,7 @@ static void get_cdd_val(uint16_t **phy_ptr, uint32_t rank, uint32_t freq,
rwmax = tmp;
}
tmp = wrmax;
c = &cdd[41];
wrmax = findmax(c, 16U);
if (tmp > wrmax) {
wrmax = tmp;
}
wrmax = wwmax;
break;
@ -390,7 +371,12 @@ static void get_cdd_val(uint16_t **phy_ptr, uint32_t rank, uint32_t freq,
#ifdef NXP_WARM_BOOT
int save_phy_training_values(uint16_t **phy_ptr, uint32_t address_to_store,
uint32_t num_of_phy, int train2d)
uint32_t num_of_phy, int train2d
#ifdef NXP_APPLY_MAX_CDD
, struct ddr_ctrl_reg_values *ddrctrl_regs
#endif
)
{
uint16_t *phy = NULL, value = 0x0;
uint32_t size = 1U, num_of_regs = 1U, phy_store = 0U;
@ -457,6 +443,15 @@ int save_phy_training_values(uint16_t **phy_ptr, uint32_t address_to_store,
ret = xspi_write(phy_store, training_2D_values,
size);
}
#ifdef NXP_APPLY_MAX_CDD
/* Save DDR control register Timing CFG 0 and 4 */
phy_store += size;
size = sizeof(ddrctrl_regs);
if (ret != 0) {
ret = xspi_write(phy_store, ddrctrl_regs, size);
}
#endif
/* Disable clocks in case they were disabled. */
phy_io_write16(phy, t_drtub |
csr_ucclk_hclk_enables_addr, 0x0);
@ -472,7 +467,11 @@ int save_phy_training_values(uint16_t **phy_ptr, uint32_t address_to_store,
}
int restore_phy_training_values(uint16_t **phy_ptr, uint32_t address_to_restore,
uint32_t num_of_phy, int train2d)
uint32_t num_of_phy, int train2d
#ifdef NXP_APPLY_MAX_CDD
, struct ddr_ctrl_reg_values *ddrctrl_regs
#endif
)
{
uint16_t *phy = NULL;
uint32_t size = 1U, num_of_regs = 1U, phy_store = 0U;
@ -504,6 +503,14 @@ int restore_phy_training_values(uint16_t **phy_ptr, uint32_t address_to_restore,
/* Reading 1D training values from flash*/
ret = xspi_read(phy_store, (uint32_t *)training_1D_values,
size);
if (ret != 0) {
#ifdef DEBUG_WARM_RESET
debug("Unable to Read 1D training values %d\n",
ret);
#endif
return -EINVAL;
}
debug("Restoring 1D Training reg val at:%08x\n", phy_store);
for (i = 0; i < num_of_regs; i++) {
phy_io_write16(phy, training_1D_values[i].addr,
@ -523,6 +530,15 @@ int restore_phy_training_values(uint16_t **phy_ptr, uint32_t address_to_restore,
/* Reading 2D training values from flash */
ret = xspi_read(phy_store,
(uint32_t *)training_2D_values, size);
if (ret != 0) {
#ifdef DEBUG_WARM_RESET
debug("Unable to Read 2D training values %d\n",
ret);
#endif
return -EINVAL;
}
debug("Restoring 2D Training reg val at:%08x\n",
phy_store);
for (i = 0; i < num_of_regs; i++) {
@ -537,6 +553,11 @@ int restore_phy_training_values(uint16_t **phy_ptr, uint32_t address_to_restore,
#endif
}
}
#ifdef NXP_APPLY_MAX_CDD
phy_store = phy_store + size;
size = sizeof(ddrctrl_regs);
ret = xspi_read(phy_store, (uint32_t *)ddrctrl_regs, size);
#endif
/* Disable clocks in case they were disabled. */
phy_io_write16(phy, t_drtub |
csr_ucclk_hclk_enables_addr, 0x0);
@ -2292,6 +2313,7 @@ static void parse_odt(const unsigned int val,
if (i < 0 || i > 3) {
printf("Error: invalid chip-select value\n");
return;
}
switch (val) {
case DDR_ODT_CS:
@ -2473,6 +2495,9 @@ int compute_ddr_phy(struct ddr_info *priv)
__unused const soc_info_t *soc_info;
#ifdef NXP_APPLY_MAX_CDD
unsigned int tcfg0, tcfg4, rank;
#ifdef NXP_WARM_BOOT
struct ddr_ctrl_reg_values ddrctrl_regs;
#endif
#endif
if (dimm_param == NULL) {
@ -2577,11 +2602,19 @@ int compute_ddr_phy(struct ddr_info *priv)
ret = restore_phy_training_values(priv->phy,
PHY_TRAINING_REGS_ON_FLASH,
priv->num_ctlrs,
input.basic.train2d);
input.basic.train2d
#ifdef NXP_APPLY_MAX_CDD
, &ddrctrl_regs
#endif
);
if (ret != 0) {
ERROR("Restoring of training data failed %d\n", ret);
return ret;
}
#ifdef NXP_APPLY_MAX_CDD
regs->timing_cfg[0] = ddrctrl_regs.timing_cfg0;
regs->timing_cfg[4] = ddrctrl_regs.timing_cfg4;
#endif
} else {
#endif
/* Mapping IMG buffer firstly */
@ -2644,12 +2677,20 @@ int compute_ddr_phy(struct ddr_info *priv)
#ifdef NXP_WARM_BOOT
if (priv->warm_boot_flag != DDR_WRM_BOOT_NT_SUPPORTED &&
ret == 0) {
#ifdef NXP_APPLY_MAX_CDD
ddrctrl_regs.timing_cfg0 = regs->timing_cfg[0];
ddrctrl_regs.timing_cfg4 = regs->timing_cfg[4];
#endif
debug("save the phy training data\n");
//Save training data TBD
ret = save_phy_training_values(priv->phy,
PHY_TRAINING_REGS_ON_FLASH,
priv->num_ctlrs,
input.basic.train2d);
input.basic.train2d
#ifdef NXP_APPLY_MAX_CDD
, &ddrctrl_regs
#endif
);
if (ret != 0) {
ERROR("Saving training data failed.");
ERROR("Warm boot will fail. Error=%d.\n", ret);

26
drivers/nxp/ddr/phy-gen2/phy.h
View file

@ -11,11 +11,18 @@
/* To store sector size to be erase on flash*/
#define PHY_ERASE_SIZE F_SECTOR_ERASE_SZ
/*Structure to save DDR controller timing register 0 and 4 values*/
struct ddr_ctrl_reg_values {
uint32_t timing_cfg0;
uint32_t timing_cfg4;
};
/*Structure to implement address-data map tuples to store PHY training values*/
struct phy_training_values {
uint32_t addr;
uint16_t data;
};
/* Saves PHY Training Register values after cold reset
*@param[in] phy_ptr array to store addresses of PHYs
*@param[in] address_to_store address to save PHY training register values
@ -24,6 +31,8 @@ struct phy_training_values {
*to be saved
*@param[in] train2d flag to store whether 2D training registers are to
*be saved or not
*@param[in] ddrctrl_regs to save ddr controller registers in case
*NXP_APPLY_MAX_CDD is applied
*
*PHY training values will be stored on flash at contigous memory in the order:
*1D training registers, 2D training registers
@ -31,9 +40,13 @@ struct phy_training_values {
*
*if train2d is false saving 2D training registers will be skipped
*/
int save_phy_training_values(uint16_t **phy_ptr, uint32_t address_to_store,
uint32_t num_of_phy, int train2d);
int save_phy_training_values(uint16_t **phy_ptr, uint32_t address_to_store,
uint32_t num_of_phy, int train2d
#ifdef NXP_APPLY_MAX_CDD
, struct ddr_ctrl_reg_values *ddrctrl_regs
#endif
);
/*Restores PHY Training Register values after warm reset
*@param[in] phy_ptr array to store addresses of PHYs
*@param[in] address_to_store address to retrieve PHY training register
@ -42,12 +55,17 @@ int save_phy_training_values(uint16_t **phy_ptr, uint32_t address_to_store,
*to be restored
*@param[in] train2d flag to store whether 2D training registers are
*to be restored or not
*
*@param[in] ddrctrl_regs to restore ddr controller registers in case
*NXP_APPLY_MAX_CDD is applied
*if train2d is false saving 2D training registers will be skipped
*/
int restore_phy_training_values(uint16_t **phy_ptr, uint32_t address_to_restore,
uint32_t num_of_phy, int train2d);
uint32_t num_of_phy, int train2d
#ifdef NXP_APPLY_MAX_CDD
, struct ddr_ctrl_reg_values *ddrctrl_regs
#endif
);
/*
* Address data tuples to store the PHY 1D

3
drivers/nxp/flexspi/nor/fspi.c
View file

@ -123,6 +123,9 @@ static void fspi_op_setup(uint32_t fspi_op_seq_id, bool ignore_flash_sz)
cmd_id1 = FSPI_NOR_CMD_RDSR;
cmd_id2 = FSPI_NOR_CMD_RDSR;
break;
default:
ERROR("Unsupported command\n");
return;
}
x_addr = FSPI_LUTREG_OFFSET + (uint32_t)(0x10 * fspi_op_seq_id);

27
drivers/nxp/tzc/plat_tzc380.c
View file

@ -91,20 +91,37 @@ int populate_tzc380_reg_list(struct tzc380_reg *tzc380_reg_list,
}
/* Continue with list entries for index > 0 */
if (dram_idx == 0) {
/* TZC Region 1 on DRAM0 for Secure Memory*/
/*
* Region 1: Secure Region on DRAM 1 for 2MB out of 2MB,
* excluding 0 sub-region(=256KB).
*/
tzc380_reg_list[list_idx].secure = TZC_ATTR_SP_S_RW;
tzc380_reg_list[list_idx].enabled = TZC_ATTR_REGION_ENABLE;
tzc380_reg_list[list_idx].addr = dram_start_addr + dram_size;
tzc380_reg_list[list_idx].size = secure_dram_sz;
tzc380_reg_list[list_idx].size = TZC_REGION_SIZE_2M;
tzc380_reg_list[list_idx].sub_mask = 0x0; /* all enabled */
list_idx++;
/* TZC Region 2 on DRAM0 for Shared Memory*/
/*
* Region 2: Secure Region on DRAM 1 for 54MB out of 64MB,
* excluding 1 sub-rgion(=8MB) of 8MB.
*/
tzc380_reg_list[list_idx].secure = TZC_ATTR_SP_S_RW;
tzc380_reg_list[list_idx].enabled = TZC_ATTR_REGION_ENABLE;
tzc380_reg_list[list_idx].addr = dram_start_addr + dram_size + shrd_dram_sz;
tzc380_reg_list[list_idx].size = TZC_REGION_SIZE_64M;
tzc380_reg_list[list_idx].sub_mask = 0x80; /* Disable sub-region 7 */
list_idx++;
/*
* Region 3: Secure Region on DRAM 1 for 6MB out of 8MB,
* excluding 2 sub-rgion(=1MB) of 2MB.
*/
tzc380_reg_list[list_idx].secure = TZC_ATTR_SP_S_RW;
tzc380_reg_list[list_idx].enabled = TZC_ATTR_REGION_ENABLE;
tzc380_reg_list[list_idx].addr = dram_start_addr + dram_size + secure_dram_sz;
tzc380_reg_list[list_idx].size = shrd_dram_sz;
tzc380_reg_list[list_idx].sub_mask = 0x0; /* all enabled */
tzc380_reg_list[list_idx].size = TZC_REGION_SIZE_8M;
tzc380_reg_list[list_idx].sub_mask = 0xC0; /* Disable sub-region 6 & 7 */
list_idx++;
}

12
include/drivers/nxp/smmu/nxp_smmu.h
View file

@ -10,10 +10,13 @@
#define SMMU_SCR0 (0x0)
#define SMMU_NSCR0 (0x400)
#define SMMU_SACR (0x10)
#define SCR0_CLIENTPD_MASK 0x00000001
#define SCR0_USFCFG_MASK 0x00000400
#define SMMU_SACR_CACHE_LOCK_ENABLE_BIT (1ULL << 26U)
static inline void bypass_smmu(uintptr_t smmu_base_addr)
{
uint32_t val;
@ -27,4 +30,13 @@ static inline void bypass_smmu(uintptr_t smmu_base_addr)
mmio_write_32((smmu_base_addr + SMMU_NSCR0), val);
}
static inline void smmu_cache_unlock(uintptr_t smmu_base_addr)
{
uint32_t val;
val = mmio_read_32((smmu_base_addr + SMMU_SACR));
val &= (uint32_t)~SMMU_SACR_CACHE_LOCK_ENABLE_BIT;
mmio_write_32((smmu_base_addr + SMMU_SACR), val);
}
#endif

2
plat/nxp/common/nv_storage/plat_nv_storage.c
View file

@ -93,7 +93,7 @@ int wr_nv_app_data(int data_offset,
uint8_t ready_to_write_val[sizeof(nv_app_data_t)];
uintptr_t nv_base_addr = NV_STORAGE_BASE_ADDR;
assert((nv_base_addr + data_offset + data_size) > (nv_base_addr + F_SECTOR_ERASE_SZ));
assert((nv_base_addr + data_offset + data_size) <= (nv_base_addr + F_SECTOR_ERASE_SZ));
ret = fspi_init(NXP_FLEXSPI_ADDR, NXP_FLEXSPI_FLASH_ADDR);

2
plat/nxp/soc-ls1028a/soc.def
View file

@ -70,8 +70,8 @@ BL2_BASE := $(shell echo "0x"$$(echo "obase=16; ${BL2_BASE_ADDR}" | bc))
BL2_HDR_LOC := 0x1800A000
# SoC ERRATAS to be enabled
ERRATA_SOC_A008850 := 1
# DDR ERRATA
ERRATA_DDR_A009803 := 1
ERRATA_DDR_A009942 := 1
ERRATA_DDR_A010165 := 1

8
plat/nxp/soc-ls1043a/soc.c
View file

@ -21,9 +21,7 @@
#ifdef POLICY_FUSE_PROVISION
#include <nxp_gpio.h>
#endif
#if TRUSTED_BOARD_BOOT
#include <nxp_smmu.h>
#endif
#include <nxp_timer.h>
#include <plat_console.h>
#include <plat_gic.h>
@ -174,6 +172,12 @@ void soc_early_init(void)
get_cluster_info(soc_list, ARRAY_SIZE(soc_list), &num_clusters, &cores_per_cluster);
plat_ls_interconnect_enter_coherency(num_clusters);
/*
* Unlock write access for SMMU SMMU_CBn_ACTLR in all Non-secure contexts.
*/
smmu_cache_unlock(NXP_SMMU_ADDR);
INFO("SMMU Cache Unlocking is Configured.\n");
#if TRUSTED_BOARD_BOOT
uint32_t mode;

2
plat/nxp/soc-ls1043a/soc.mk
View file

@ -19,8 +19,8 @@ include ${PLAT_COMMON_PATH}/plat_make_helper/plat_build_macros.mk
# For Security Features
DISABLE_FUSE_WRITE := 1
ifeq (${TRUSTED_BOARD_BOOT}, 1)
$(eval $(call SET_NXP_MAKE_FLAG,SMMU_NEEDED,BL2))
ifeq (${TRUSTED_BOARD_BOOT}, 1)
$(eval $(call SET_NXP_MAKE_FLAG,SFP_NEEDED,BL2))
$(eval $(call SET_NXP_MAKE_FLAG,SNVS_NEEDED,BL2))
SECURE_BOOT := yes

8
plat/nxp/soc-ls1046a/soc.c
View file

@ -21,9 +21,7 @@
#ifdef POLICY_FUSE_PROVISION
#include <nxp_gpio.h>
#endif
#if TRUSTED_BOARD_BOOT
#include <nxp_smmu.h>
#endif
#include <nxp_timer.h>
#include <plat_console.h>
#include <plat_gic.h>
@ -168,6 +166,12 @@ void soc_early_init(void)
get_cluster_info(soc_list, ARRAY_SIZE(soc_list), &num_clusters, &cores_per_cluster);
plat_ls_interconnect_enter_coherency(num_clusters);
/*
* Unlock write access for SMMU SMMU_CBn_ACTLR in all Non-secure contexts.
*/
smmu_cache_unlock(NXP_SMMU_ADDR);
INFO("SMMU Cache Unlocking is Configured.\n");
#if TRUSTED_BOARD_BOOT
uint32_t mode;

4
plat/nxp/soc-ls1046a/soc.def
View file

@ -41,11 +41,11 @@ DDRCNTLR := NXP
DDRPHY := NXP
# Area of OCRAM reserved by ROM code
NXP_ROM_RSVD := 0x5900
NXP_ROM_RSVD := 0x8000
# Max Size of CSF header. Required to define BL2 TEXT LIMIT in soc.def
# Input to CST create_hdr_esbc tool
CSF_HDR_SZ := 0x3000
CSF_HDR_SZ := 0x4000
# In IMAGE_BL2, compile time flag for handling Cache coherency
# with CAAM for BL2 running from OCRAM

2
plat/nxp/soc-ls1046a/soc.mk
View file

@ -19,8 +19,8 @@ include ${PLAT_COMMON_PATH}/plat_make_helper/plat_build_macros.mk
# For Security Features
DISABLE_FUSE_WRITE := 1
ifeq (${TRUSTED_BOARD_BOOT}, 1)
$(eval $(call SET_NXP_MAKE_FLAG,SMMU_NEEDED,BL2))
ifeq (${TRUSTED_BOARD_BOOT}, 1)
$(eval $(call SET_NXP_MAKE_FLAG,SFP_NEEDED,BL2))
$(eval $(call SET_NXP_MAKE_FLAG,SNVS_NEEDED,BL2))
SECURE_BOOT := yes

2
plat/nxp/soc-ls1088a/ls1088aqds/ddr_init.c
View file

@ -78,7 +78,5 @@ long long init_ddr(void)
ERROR("DDR init failed.\n");
}
erratum_a008850_post();
return dram_size;
}

2
plat/nxp/soc-ls1088a/ls1088ardb/ddr_init.c
View file

@ -80,7 +80,5 @@ long long init_ddr(void)
ERROR("DDR init failed.\n");
}
erratum_a008850_post();
return dram_size;
}

8
plat/nxp/soc-ls1088a/soc.c
View file

@ -17,9 +17,7 @@
#include <lib/mmio.h>
#include <lib/xlat_tables/xlat_tables_v2.h>
#include <ls_interconnect.h>
#if TRUSTED_BOARD_BOOT
#include <nxp_smmu.h>
#endif
#include <nxp_timer.h>
#include <plat_console.h>
#include <plat_gic.h>
@ -254,6 +252,12 @@ void soc_early_init(void)
MT_DEVICE | MT_RW | MT_NS);
}
/*
* Unlock write access for SMMU SMMU_CBn_ACTLR in all Non-secure contexts.
*/
smmu_cache_unlock(NXP_SMMU_ADDR);
INFO("SMMU Cache Unlocking is Configured.\n");
#if TRUSTED_BOARD_BOOT
uint32_t mode;

1
plat/nxp/soc-ls1088a/soc.def
View file

@ -62,7 +62,6 @@ BL2_HDR_LOC := 0x1801D000
BL2_BASE := 0x1800a000
# SoC ERRATUM to be enabled
ERRATA_SOC_A008850 := 1
# ARM Erratum
ERRATA_A53_855873 := 1

2
plat/nxp/soc-ls1088a/soc.mk
View file

@ -23,12 +23,12 @@ include ${PLAT_COMMON_PATH}/plat_make_helper/plat_build_macros.mk
# For Security Features
DISABLE_FUSE_WRITE := 1
$(eval $(call SET_NXP_MAKE_FLAG,SMMU_NEEDED,BL2))
ifeq (${TRUSTED_BOARD_BOOT}, 1)
ifeq (${GENERATE_COT},1)
# Save Keys to be used by DDR FIP image
SAVE_KEYS=1
endif
$(eval $(call SET_NXP_MAKE_FLAG,SMMU_NEEDED,BL2))
$(eval $(call SET_NXP_MAKE_FLAG,SFP_NEEDED,BL2))
$(eval $(call SET_NXP_MAKE_FLAG,SNVS_NEEDED,BL2))
# Used by create_pbl tool to

23
plat/nxp/soc-lx2160a/include/soc.h
View file

@ -54,8 +54,31 @@
/* SVR Definition (not include major and minor rev) */
#define SVR_LX2160A 0x873601
#define SVR_LX2160E 0x873610
#define SVR_LX2160C 0x873600
#define SVR_LX2160N 0x873611
#define SVR_LX2120A 0x873621
#define SVR_LX2120E 0x873630
#define SVR_LX2120C 0x873620
#define SVR_LX2120N 0x873631
#define SVR_LX2080A 0x873603
#define SVR_LX2080E 0x873612
#define SVR_LX2080C 0x873602
#define SVR_LX2080N 0x873613
/* SVR Definition of SoC LX2162A. */
#define SVR_LX2162A 0x873609
#define SVR_LX2162E 0x873618
#define SVR_LX2162C 0x873608
#define SVR_LX2162N 0x873619
#define SVR_LX2122A 0x873629
#define SVR_LX2122E 0x873638
#define SVR_LX2122C 0x873628
#define SVR_LX2122N 0x873639
#define SVR_LX2082A 0x87360b
#define SVR_LX2082E 0x87361a
#define SVR_LX2082C 0x87360a
#define SVR_LX2082N 0x87361b
/* Number of cores in platform */
/* Used by common code for array initialization */

39
plat/nxp/soc-lx2160a/soc.c
View file

@ -23,9 +23,7 @@
#ifdef POLICY_FUSE_PROVISION
#include <nxp_gpio.h>
#endif
#if TRUSTED_BOARD_BOOT
#include <nxp_smmu.h>
#endif
#include <nxp_timer.h>
#include <plat_console.h>
#include <plat_gic.h>
@ -37,6 +35,9 @@
#include <errata.h>
#include <ls_interrupt_mgmt.h>
#ifdef CONFIG_OCRAM_ECC_EN
#include <ocram.h>
#endif
#include "plat_common.h"
#ifdef NXP_NV_SW_MAINT_LAST_EXEC_DATA
#include <plat_nv_storage.h>
@ -48,9 +49,32 @@
#include "soc.h"
static struct soc_type soc_list[] = {
/* SoC LX2160A */
SOC_ENTRY(LX2160A, LX2160A, 8, 2),
SOC_ENTRY(LX2160E, LX2160E, 8, 2),
SOC_ENTRY(LX2160C, LX2160C, 8, 2),
SOC_ENTRY(LX2160N, LX2160N, 8, 2),
SOC_ENTRY(LX2080A, LX2080A, 8, 1),
SOC_ENTRY(LX2080E, LX2080E, 8, 1),
SOC_ENTRY(LX2080C, LX2080C, 8, 1),
SOC_ENTRY(LX2080N, LX2080N, 8, 1),
SOC_ENTRY(LX2120A, LX2120A, 6, 2),
SOC_ENTRY(LX2120E, LX2120E, 6, 2),
SOC_ENTRY(LX2120C, LX2120C, 6, 2),
SOC_ENTRY(LX2120N, LX2120N, 6, 2),
/* SoC LX2162A */
SOC_ENTRY(LX2162A, LX2162A, 8, 2),
SOC_ENTRY(LX2162E, LX2162E, 8, 2),
SOC_ENTRY(LX2162C, LX2162C, 8, 2),
SOC_ENTRY(LX2162N, LX2162N, 8, 2),
SOC_ENTRY(LX2082A, LX2082A, 8, 1),
SOC_ENTRY(LX2082E, LX2082E, 8, 1),
SOC_ENTRY(LX2082C, LX2082C, 8, 1),
SOC_ENTRY(LX2082N, LX2082N, 8, 1),
SOC_ENTRY(LX2122A, LX2122A, 6, 2),
SOC_ENTRY(LX2122E, LX2122E, 6, 2),
SOC_ENTRY(LX2122C, LX2122C, 6, 2),
SOC_ENTRY(LX2122N, LX2122N, 6, 2),
};
static dcfg_init_info_t dcfg_init_data = {
@ -215,6 +239,9 @@ void soc_preload_setup(void)
******************************************************************************/
void soc_early_init(void)
{
#ifdef CONFIG_OCRAM_ECC_EN
ocram_init(NXP_OCRAM_ADDR, NXP_OCRAM_SIZE);
#endif
dcfg_init(&dcfg_init_data);
#ifdef POLICY_FUSE_PROVISION
gpio_init(&gpio_init_data);
@ -257,6 +284,12 @@ void soc_early_init(void)
sfp_init(NXP_SFP_ADDR);
#endif
/*
* Unlock write access for SMMU SMMU_CBn_ACTLR in all Non-secure contexts.
*/
smmu_cache_unlock(NXP_SMMU_ADDR);
INFO("SMMU Cache Unlocking is Configured.\n");
#if TRUSTED_BOARD_BOOT
uint32_t mode;
@ -451,8 +484,8 @@ void soc_init(void)
/* low-level init of the soc */
soc_init_start();
soc_init_percpu();
_init_global_data();
soc_init_percpu();
_initialize_psci();
if (ccn_get_part0_id(NXP_CCN_ADDR) != CCN_508_PART0_ID) {

3
plat/nxp/soc-lx2160a/soc.def
View file

@ -114,3 +114,6 @@ ERRATA_DDR_A050958 := 1
# enable dynamic memory mapping
PLAT_XLAT_TABLES_DYNAMIC := 1
# OCRAM ECC Enabled
OCRAM_ECC_EN := yes

2
plat/nxp/soc-lx2160a/soc.mk
View file

@ -36,12 +36,12 @@ endif
# For Security Features
DISABLE_FUSE_WRITE := 1
$(eval $(call SET_NXP_MAKE_FLAG,SMMU_NEEDED,BL2))
ifeq (${TRUSTED_BOARD_BOOT}, 1)
ifeq (${GENERATE_COT},1)
# Save Keys to be used by DDR FIP image
SAVE_KEYS=1
endif
$(eval $(call SET_NXP_MAKE_FLAG,SMMU_NEEDED,BL2))
$(eval $(call SET_NXP_MAKE_FLAG,SFP_NEEDED,BL2))
$(eval $(call SET_NXP_MAKE_FLAG,SNVS_NEEDED,BL2))
# Used by create_pbl tool to

4
tools/nxp/create_pbl/create_pbl.c
View file

@ -823,7 +823,9 @@ int main(int argc, char **argv)
}
}
if ((args & MAND_ARG_MASK) != MAND_ARG_MASK) {
if ((args & MAND_ARG_MASK) != MAND_ARG_MASK
|| pblimg.rcw_nm == NULL
|| pblimg.imagefile == NULL) {
print_usage();
}