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fix(intel): update outdated code for Linux direct boot

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1. Update emif rsthdshk  macro
2. Update mailbox return status
3. Update bridge return status

Change-Id: I33905508aceb258ac8759c10079b2af977df0e0a
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
This commit is contained in:
Sieu Mun Tang 2024-10-04 14:27:18 +08:00 • committed by Tang Sieu Mun
parent b6f2e376a8
commit 21a01dac87
5 changed files with 7 additions and 6 deletions
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2
plat/intel/soc/agilex/bl2_plat_setup.c
View file

@ -129,11 +129,13 @@ void bl2_el3_plat_arch_setup(void)
switch (boot_source) { switch (boot_source) {
case BOOT_SOURCE_SDMMC: case BOOT_SOURCE_SDMMC:
NOTICE("SDMMC boot\n");
dw_mmc_init(&params, &mmc_info); dw_mmc_init(&params, &mmc_info);
socfpga_io_setup(boot_source, PLAT_SDMMC_DATA_BASE); socfpga_io_setup(boot_source, PLAT_SDMMC_DATA_BASE);
break; break;
case BOOT_SOURCE_QSPI: case BOOT_SOURCE_QSPI:
NOTICE("QSPI boot\n");
cad_qspi_init(0, QSPI_CONFIG_CPHA, QSPI_CONFIG_CPOL, cad_qspi_init(0, QSPI_CONFIG_CPHA, QSPI_CONFIG_CPOL,
QSPI_CONFIG_CSDA, QSPI_CONFIG_CSDADS, QSPI_CONFIG_CSDA, QSPI_CONFIG_CSDADS,
QSPI_CONFIG_CSEOT, QSPI_CONFIG_CSSOT, 0); QSPI_CONFIG_CSEOT, QSPI_CONFIG_CSSOT, 0);

3
plat/intel/soc/agilex/include/agilex_memory_controller.h
View file

@ -1,5 +1,6 @@
/* /*
* Copyright (c) 2019, Intel Corporation. All rights reserved. * Copyright (c) 2019, Intel Corporation. All rights reserved.
* Copyright (c) 2024, Altera Corporation. All rights reserved.
* *
* SPDX-License-Identifier: BSD-3-Clause * SPDX-License-Identifier: BSD-3-Clause
*/ */
@ -27,7 +28,7 @@
#define AGX_MPFE_HMC_ADP_ECCCTRL1 0xf8011100 #define AGX_MPFE_HMC_ADP_ECCCTRL1 0xf8011100
#define AGX_MPFE_HMC_ADP_ECCCTRL2 0xf8011104 #define AGX_MPFE_HMC_ADP_ECCCTRL2 0xf8011104
#define AGX_MPFE_HMC_ADP_RSTHANDSHAKESTAT 0xf8011218 #define AGX_MPFE_HMC_ADP_RSTHANDSHAKESTAT 0xf8011218
#define AGX_MPFE_HMC_ADP_RSTHANDSHAKESTAT_SEQ2CORE 0x000000ff #define AGX_MPFE_HMC_ADP_RSTHANDSHAKESTAT_SEQ2CORE 0x0000000f
#define AGX_MPFE_HMC_ADP_RSTHANDSHAKECTRL 0xf8011214 #define AGX_MPFE_HMC_ADP_RSTHANDSHAKECTRL 0xf8011214

2
plat/intel/soc/common/soc/socfpga_mailbox.c
View file

@ -652,7 +652,7 @@ int intel_mailbox_get_config_status(uint32_t cmd, bool init_done)
res = response[RECONFIG_STATUS_SOFTFUNC_STATUS]; res = response[RECONFIG_STATUS_SOFTFUNC_STATUS];
if ((res & SOFTFUNC_STATUS_SEU_ERROR) != 0U) { if ((res & SOFTFUNC_STATUS_SEU_ERROR) != 0U) {
ERROR("SoftFunction Status SEU ERROR\n"); return MBOX_CFGSTAT_STATE_ERROR_HARDWARE;
} }
if ((res & SOFTFUNC_STATUS_CONF_DONE) == 0U) { if ((res & SOFTFUNC_STATUS_CONF_DONE) == 0U) {

3
plat/intel/soc/common/soc/socfpga_reset_manager.c
View file

@ -580,9 +580,6 @@ int socfpga_bridges_enable(uint32_t mask)
/* Wait until idle ack becomes 0 */ /* Wait until idle ack becomes 0 */
ret_hps = poll_idle_status(SOCFPGA_SYSMGR(NOC_IDLEACK), ret_hps = poll_idle_status(SOCFPGA_SYSMGR(NOC_IDLEACK),
noc_mask, 0, 1000); noc_mask, 0, 1000);
if (ret_hps < 0) {
ERROR("S2F bridge enable: Timeout idle ack\n");
}
} }
#endif #endif

3
plat/intel/soc/stratix10/include/s10_memory_controller.h
View file

@ -1,5 +1,6 @@
/* /*
* Copyright (c) 2019, Intel Corporation. All rights reserved. * Copyright (c) 2019, Intel Corporation. All rights reserved.
* Copyright (c) 2024, Altera Corporation. All rights reserved.
* *
* SPDX-License-Identifier: BSD-3-Clause * SPDX-License-Identifier: BSD-3-Clause
*/ */
@ -26,7 +27,7 @@
#define S10_MPFE_HMC_ADP_ECCCTRL1 0xf8011100 #define S10_MPFE_HMC_ADP_ECCCTRL1 0xf8011100
#define S10_MPFE_HMC_ADP_ECCCTRL2 0xf8011104 #define S10_MPFE_HMC_ADP_ECCCTRL2 0xf8011104
#define S10_MPFE_HMC_ADP_RSTHANDSHAKESTAT 0xf8011218 #define S10_MPFE_HMC_ADP_RSTHANDSHAKESTAT 0xf8011218
#define S10_MPFE_HMC_ADP_RSTHANDSHAKESTAT_SEQ2CORE 0x000000ff #define S10_MPFE_HMC_ADP_RSTHANDSHAKESTAT_SEQ2CORE 0x0000000f
#define S10_MPFE_HMC_ADP_RSTHANDSHAKECTRL 0xf8011214 #define S10_MPFE_HMC_ADP_RSTHANDSHAKECTRL 0xf8011214