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Merge changes from topic "ar/asymmetricSupport" into integration

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* changes:
  feat(trbe): introduce trbe_disable() function
  feat(spe): introduce spe_disable() function
  chore(spe): rename spe_disable() to spe_stop()
This commit is contained in:
Manish V Badarkhe 2024-08-05 17:16:52 +02:00 • committed by TrustedFirmware Code Review
commit 1baf62469e
5 changed files with 52 additions and 4 deletions
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8
include/lib/extensions/spe.h
View file

@ -12,16 +12,20 @@
#if ENABLE_SPE_FOR_NS
void spe_enable(cpu_context_t *ctx);
void spe_disable(cpu_context_t *ctx);
void spe_init_el2_unused(void);
void spe_disable(void);
void spe_stop(void);
#else
static inline void spe_enable(cpu_context_t *ctx)
{
}
static inline void spe_disable(cpu_context_t *ctx)
{
}
static inline void spe_init_el2_unused(void)
{
}
static inline void spe_disable(void)
static inline void spe_stop(void)
{
}
#endif /* ENABLE_SPE_FOR_NS */

4
include/lib/extensions/trbe.h
View file

@ -10,9 +10,13 @@
#include <context.h>
#if ENABLE_TRBE_FOR_NS
void trbe_disable(cpu_context_t *ctx);
void trbe_enable(cpu_context_t *ctx);
void trbe_init_el2_unused(void);
#else
static inline void trbe_disable(cpu_context_t *ctx)
{
}
static inline void trbe_enable(cpu_context_t *ctx)
{
}

23
lib/extensions/spe/spe.c
View file

@ -52,6 +52,27 @@ void spe_enable(cpu_context_t *ctx)
write_ctx_reg(state, CTX_MDCR_EL3, mdcr_el3_val);
}
void spe_disable(cpu_context_t *ctx)
{
el3_state_t *state = get_el3state_ctx(ctx);
u_register_t mdcr_el3_val = read_ctx_reg(state, CTX_MDCR_EL3);
/*
* MDCR_EL3.NSPB: Clear these bits to disable SPE feature, as it was enabled
* for Non-secure state only. After clearing these bits Secure state owns
* the Profiling Buffer and accesses to Statistical Profiling and Profiling
* Buffer control registers at EL2 and EL1 generate Trap exceptions to EL3
*
* MDCR_EL3.NSPBE: Don't care as it was cleared during spe_enable and setting
* this to 1 does not make sense as NSPBE{1} and NSPB{0b0x} is RESERVED.
*
* MDCR_EL3.EnPMSN (ARM v8.7): Clear the bit to trap access of PMSNEVFR_EL1
* from EL2/EL1 to EL3.
*/
mdcr_el3_val &= ~(MDCR_NSPB(MDCR_NSPB_EL1) | MDCR_EnPMSN_BIT);
write_ctx_reg(state, CTX_MDCR_EL3, mdcr_el3_val);
}
void spe_init_el2_unused(void)
{
uint64_t v;
@ -70,7 +91,7 @@ void spe_init_el2_unused(void)
write_mdcr_el2(v);
}
void spe_disable(void)
void spe_stop(void)
{
uint64_t v;

19
lib/extensions/trbe/trbe.c
View file

@ -39,6 +39,25 @@ void trbe_enable(cpu_context_t *ctx)
write_ctx_reg(state, CTX_MDCR_EL3, mdcr_el3_val);
}
void trbe_disable(cpu_context_t *ctx)
{
el3_state_t *state = get_el3state_ctx(ctx);
u_register_t mdcr_el3_val = read_ctx_reg(state, CTX_MDCR_EL3);
/*
* MDCR_EL3.NSTBE = 0b0
* Trace Buffer owning Security state is secure state. If FEAT_RME
* is not implemented, this field is RES0.
*
* MDCR_EL3.NSTB = 0b00
* Clear these bits to disable access of trace buffer control registers
* from lower ELs in any security state.
*/
mdcr_el3_val &= ~(MDCR_NSTB(MDCR_NSTB_EL1));
mdcr_el3_val &= ~(MDCR_NSTBE_BIT);
write_ctx_reg(state, CTX_MDCR_EL3, mdcr_el3_val);
}
void trbe_init_el2_unused(void)
{
/*

2
lib/psci/psci_common.c
View file

@ -1303,7 +1303,7 @@ void psci_do_manage_extensions(void)
* before exiting coherency.
*/
if (is_feat_spe_supported()) {
spe_disable();
spe_stop();
}
}