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Merge changes from topic "corstone1000-bugfixes" into integration

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* changes:
  fix(corstone1000): update memory layout comments
  fix(corstone1000): clean cache and disable interrupt before system reset
  fix(corstone1000): remove unused NS_SHARED_RAM region
  fix(corstone1000): pass spsr value explicitly
This commit is contained in:
Manish Pandey 2024-08-05 13:48:38 +02:00 • committed by TrustedFirmware Code Review
commit bbca58ffd3
4 changed files with 28 additions and 31 deletions

5
plat/arm/board/corstone1000/common/corstone1000_bl2_mem_params_desc.c
View file

@ -1,5 +1,5 @@
/*
* Copyright (c) 2021-2022, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2021-2022, 2024 ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -77,7 +77,8 @@ static bl_mem_params_node_t bl2_mem_params_descs[] = {
SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP,
VERSION_2, entry_point_info_t, NON_SECURE | EXECUTABLE),
.ep_info.pc = BL33_BASE,
.ep_info.spsr = SPSR_64(MODE_EL2, MODE_SP_ELX,
DISABLE_ALL_EXCEPTIONS),
SET_STATIC_PARAM_HEAD(image_info, PARAM_EP,
VERSION_2, image_info_t, 0),
.image_info.image_base = BL33_BASE,

3
plat/arm/board/corstone1000/common/corstone1000_plat.c
View file

@ -1,5 +1,5 @@
/*
* Copyright (c) 2021-2023, Arm Limited and Contributors. All rights reserved.
* Copyright (c) 2021-2024, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -23,7 +23,6 @@
const mmap_region_t plat_arm_mmap[] = {
ARM_MAP_SHARED_RAM,
ARM_MAP_NS_SHARED_RAM,
ARM_MAP_NS_DRAM1,
CORSTONE1000_MAP_DEVICE,
CORSTONE1000_EXTERNAL_FLASH,

10
plat/arm/board/corstone1000/common/corstone1000_pm.c
View file

@ -8,6 +8,7 @@
#include <plat/arm/common/plat_arm.h>
#include <platform_def.h>
#include <plat/common/platform.h>
#include <drivers/arm/gicv2.h>
/*******************************************************************************
* Export the platform handlers via plat_arm_psci_pm_ops. The ARM Standard
* platform layer will take care of registering the handlers with PSCI.
@ -19,6 +20,15 @@ static void __dead2 corstone1000_system_reset(void)
uint32_t volatile * const watchdog_ctrl_reg = (uint32_t *) SECURE_WATCHDOG_ADDR_CTRL_REG;
uint32_t volatile * const watchdog_val_reg = (uint32_t *) SECURE_WATCHDOG_ADDR_VAL_REG;
/*
* Disable GIC CPU interface to prevent pending interrupt
* from waking up the AP from WFI.
*/
gicv2_cpuif_disable();
/* Flush and invalidate data cache */
dcsw_op_all(DCCISW);
*(watchdog_val_reg) = SECURE_WATCHDOG_COUNTDOWN_VAL;
*watchdog_ctrl_reg = SECURE_WATCHDOG_MASK_ENABLE;
while (1) {

41
plat/arm/board/corstone1000/common/include/platform_def.h
View file

@ -55,42 +55,42 @@
/* Memory related constants */
/* SRAM (CVM) memory layout
/* Memory mappings of where the BLs in the FIP are copied to
*
* <ARM_TRUSTED_SRAM_BASE>
* <ARM_TRUSTED_SRAM_BASE> = 0x02000000
* partition size: sizeof(meminfo_t) = 16 bytes
* content: memory info area used by the next BL
*
* <ARM_FW_CONFIG_BASE>
* <ARM_FW_CONFIG_BASE> = 0x02000010
* partition size: 4080 bytes
*
* <ARM_BL2_MEM_DESC_BASE>
* <ARM_BL2_MEM_DESC_BASE> = 0x02001000
* partition size: 4 KB
* content: Area where BL2 copies the images descriptors
*
* <ARM_BL_RAM_BASE> = <BL32_BASE>
* partition size: 688 KB
* <ARM_BL_RAM_BASE> = <BL32_BASE> = 0x02002000
* partition size: 3752 KB
* content: BL32 (optee-os)
*
* <CORSTONE1000_TOS_FW_CONFIG_BASE> = 0x20ae000
* <CORSTONE1000_TOS_FW_CONFIG_BASE> = 0x023AC000
* partition size: 8 KB
* content: BL32 config (TOS_FW_CONFIG)
*
* <BL31_BASE>
* <BL31_BASE> = 0x023AE000
* partition size: 140 KB
* content: BL31
*
* <BL2_SIGNATURE_BASE>
* <BL2_SIGNATURE_BASE> = 0x023D1000
* partition size: 4 KB
* content: MCUBOOT data needed to verify TF-A BL2
*
* <BL2_BASE>
* <BL2_BASE> = 0x023D2000
* partition size: 176 KB
* content: BL2
*
* <ARM_NS_SHARED_RAM_BASE> = <ARM_TRUSTED_SRAM_BASE> + 1 MB
* partition size: 512 KB
* content: BL33 (u-boot)
* <BL33_BASE> = 0x80000000
* partition size: 12 MB
* content: BL33 (U-Boot)
*/
/* DDR memory */
@ -115,11 +115,8 @@
/* The remaining Trusted SRAM is used to load the BL images */
#define TOTAL_SRAM_SIZE (SZ_4M) /* 4 MB */
/* Last 512KB of CVM is allocated for shared RAM as an example openAMP */
#define ARM_NS_SHARED_RAM_SIZE (512 * SZ_1K)
#define PLAT_ARM_TRUSTED_SRAM_SIZE (TOTAL_SRAM_SIZE - \
ARM_NS_SHARED_RAM_SIZE - \
ARM_SHARED_RAM_SIZE)
#define PLAT_ARM_MAX_BL2_SIZE (180 * SZ_1K) /* 180 KB */
@ -158,11 +155,6 @@
/* NS memory */
/* The last 512KB of the SRAM is allocated as shared memory */
#define ARM_NS_SHARED_RAM_BASE (ARM_TRUSTED_SRAM_BASE + TOTAL_SRAM_SIZE - \
(PLAT_ARM_MAX_BL31_SIZE + \
PLAT_ARM_MAX_BL32_SIZE))
#define BL33_BASE ARM_DRAM1_BASE
#define PLAT_ARM_MAX_BL33_SIZE (12 * SZ_1M) /* 12 MB*/
#define BL33_LIMIT (ARM_DRAM1_BASE + PLAT_ARM_MAX_BL33_SIZE)
@ -277,7 +269,7 @@
#define PLAT_ARM_NSTIMER_FRAME_ID U(1)
#define PLAT_ARM_NS_IMAGE_BASE (ARM_NS_SHARED_RAM_BASE)
#define PLAT_ARM_NS_IMAGE_BASE (BL33_BASE)
#define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32)
#define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32)
@ -306,11 +298,6 @@
ARM_SHARED_RAM_SIZE, \
MT_MEMORY | MT_RW | MT_SECURE)
#define ARM_MAP_NS_SHARED_RAM MAP_REGION_FLAT( \
ARM_NS_SHARED_RAM_BASE, \
ARM_NS_SHARED_RAM_SIZE, \
MT_MEMORY | MT_RW | MT_NS)
#define ARM_MAP_NS_DRAM1 MAP_REGION_FLAT( \
ARM_NS_DRAM1_BASE, \
ARM_NS_DRAM1_SIZE, \