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fix(intel): update all the platforms hand-off data offset value

Browse source 
Move the hand-off data offset value from the common
platform header file to each socfpga platform specific
header file.

Change-Id: Icfe917f788814c329659c44e298cf05d6e3d0dd9
Signed-off-by: Girisha Dengi <girisha.dengi@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
This commit is contained in:
Sieu Mun Tang 2024-10-24 12:52:18 +08:00
parent fa5fc59f5a
commit 1838a39a44
5 changed files with 9 additions and 13 deletions
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1
plat/intel/soc/agilex/include/socfpga_plat_def.h
View file

@ -24,6 +24,7 @@
#define PLAT_PRIMARY_CPU 0 #define PLAT_PRIMARY_CPU 0
#define PLAT_CLUSTER_ID_MPIDR_AFF_SHIFT MPIDR_AFF1_SHIFT #define PLAT_CLUSTER_ID_MPIDR_AFF_SHIFT MPIDR_AFF1_SHIFT
#define PLAT_CPU_ID_MPIDR_AFF_SHIFT MPIDR_AFF0_SHIFT #define PLAT_CPU_ID_MPIDR_AFF_SHIFT MPIDR_AFF0_SHIFT
#define PLAT_HANDOFF_OFFSET 0xFFE3F000
#define PLAT_TIMER_BASE_ADDR 0xFFD01000 #define PLAT_TIMER_BASE_ADDR 0xFFD01000
/* FPGA config helpers */ /* FPGA config helpers */

1
plat/intel/soc/agilex5/include/socfpga_plat_def.h
View file

@ -28,6 +28,7 @@
#define PLAT_CLUSTER_ID_MPIDR_AFF_SHIFT MPIDR_AFF2_SHIFT #define PLAT_CLUSTER_ID_MPIDR_AFF_SHIFT MPIDR_AFF2_SHIFT
#define PLAT_CPU_ID_MPIDR_AFF_SHIFT MPIDR_AFF1_SHIFT #define PLAT_CPU_ID_MPIDR_AFF_SHIFT MPIDR_AFF1_SHIFT
#define PLAT_L2_RESET_REQ 0xB007C0DE #define PLAT_L2_RESET_REQ 0xB007C0DE
#define PLAT_HANDOFF_OFFSET 0x0007F000
#define PLAT_TIMER_BASE_ADDR 0x10D01000 #define PLAT_TIMER_BASE_ADDR 0x10D01000
/* System Counter */ /* System Counter */

16
plat/intel/soc/common/include/platform_def.h
View file

@ -31,23 +31,15 @@
/* Define next boot image name and offset */ /* Define next boot image name and offset */
/* Get non-secure image entrypoint for BL33. Zephyr and Linux */ /* Get non-secure image entrypoint for BL33. Zephyr and Linux */
#ifdef PRELOADED_BL33_BASE
#define PLAT_NS_IMAGE_OFFSET PRELOADED_BL33_BASE
#else
#if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5 #if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5
#ifndef PRELOADED_BL33_BASE
#define PLAT_NS_IMAGE_OFFSET 0x80200000 #define PLAT_NS_IMAGE_OFFSET 0x80200000
#else #else
#define PLAT_NS_IMAGE_OFFSET PRELOADED_BL33_BASE
#endif
#define PLAT_HANDOFF_OFFSET 0x0003F000
#else
/* Legacy Products. Please refactor with Agilex5 */
#ifndef PRELOADED_BL33_BASE
#define PLAT_NS_IMAGE_OFFSET 0x10000000 #define PLAT_NS_IMAGE_OFFSET 0x10000000
#else
#define PLAT_NS_IMAGE_OFFSET PRELOADED_BL33_BASE
#endif
#define PLAT_HANDOFF_OFFSET 0xFFE3F000
#endif #endif
#endif /* #if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5 */
#define PLAT_QSPI_DATA_BASE (0x3C00000) #define PLAT_QSPI_DATA_BASE (0x3C00000)
#define PLAT_NAND_DATA_BASE (0x0200000) #define PLAT_NAND_DATA_BASE (0x0200000)

1
plat/intel/soc/n5x/include/socfpga_plat_def.h
View file

@ -19,6 +19,7 @@
#define PLAT_PRIMARY_CPU 0 #define PLAT_PRIMARY_CPU 0
#define PLAT_CLUSTER_ID_MPIDR_AFF_SHIFT MPIDR_AFF1_SHIFT #define PLAT_CLUSTER_ID_MPIDR_AFF_SHIFT MPIDR_AFF1_SHIFT
#define PLAT_CPU_ID_MPIDR_AFF_SHIFT MPIDR_AFF0_SHIFT #define PLAT_CPU_ID_MPIDR_AFF_SHIFT MPIDR_AFF0_SHIFT
#define PLAT_HANDOFF_OFFSET 0xFFE3F000
#define PLAT_TIMER_BASE_ADDR 0xFFD01000 #define PLAT_TIMER_BASE_ADDR 0xFFD01000
/* FPGA config helpers */ /* FPGA config helpers */

1
plat/intel/soc/stratix10/include/socfpga_plat_def.h
View file

@ -18,6 +18,7 @@
#define PLAT_PRIMARY_CPU 0 #define PLAT_PRIMARY_CPU 0
#define PLAT_CLUSTER_ID_MPIDR_AFF_SHIFT MPIDR_AFF1_SHIFT #define PLAT_CLUSTER_ID_MPIDR_AFF_SHIFT MPIDR_AFF1_SHIFT
#define PLAT_CPU_ID_MPIDR_AFF_SHIFT MPIDR_AFF0_SHIFT #define PLAT_CPU_ID_MPIDR_AFF_SHIFT MPIDR_AFF0_SHIFT
#define PLAT_HANDOFF_OFFSET 0xFFE3F000
#define PLAT_TIMER_BASE_ADDR 0xFFD01000 #define PLAT_TIMER_BASE_ADDR 0xFFD01000
/* FPGA config helpers */ /* FPGA config helpers */