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https://github.com/ARM-software/arm-trusted-firmware.git
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1838a39a44
Move the hand-off data offset value from the common platform header file to each socfpga platform specific header file. Change-Id: Icfe917f788814c329659c44e298cf05d6e3d0dd9 Signed-off-by: Girisha Dengi <girisha.dengi@intel.com> Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
142 lines
4.8 KiB
C
142 lines
4.8 KiB
C
/*
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* Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
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* Copyright (c) 2019-2023, Intel Corporation. All rights reserved.
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* Copyright (c) 2024, Altera Corporation. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef PLAT_SOCFPGA_DEF_H
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#define PLAT_SOCFPGA_DEF_H
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#include "agilex5_memory_controller.h"
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#include "agilex5_system_manager.h"
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#include <platform_def.h>
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/* Platform Setting */
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#define PLATFORM_MODEL PLAT_SOCFPGA_AGILEX5
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#define BOOT_SOURCE BOOT_SOURCE_SDMMC
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/* 1 = Flush cache, 0 = No cache flush.
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* Default for Agilex5 is Cache flush.
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*/
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#define CACHE_FLUSH 1
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#define MMC_DEVICE_TYPE 1 /* MMC = 0, SD = 1 */
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#define XLAT_TABLES_V2 U(1)
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#define PLAT_PRIMARY_CPU_A55 0x000
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#define PLAT_PRIMARY_CPU_A76 0x200
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#define PLAT_CLUSTER_ID_MPIDR_AFF_SHIFT MPIDR_AFF2_SHIFT
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#define PLAT_CPU_ID_MPIDR_AFF_SHIFT MPIDR_AFF1_SHIFT
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#define PLAT_L2_RESET_REQ 0xB007C0DE
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#define PLAT_HANDOFF_OFFSET 0x0007F000
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#define PLAT_TIMER_BASE_ADDR 0x10D01000
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/* System Counter */
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/* TODO: Update back to 400MHz.
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* This shall be updated to read from L4 clock instead of hardcoded.
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*/
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#define PLAT_SYS_COUNTER_FREQ_IN_TICKS U(400000000)
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#define PLAT_SYS_COUNTER_FREQ_IN_MHZ U(400)
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/* FPGA config helpers */
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#define INTEL_SIP_SMC_FPGA_CONFIG_ADDR 0x80400000
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#define INTEL_SIP_SMC_FPGA_CONFIG_SIZE 0x82000000
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/* QSPI Setting */
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#define CAD_QSPIDATA_OFST 0x10900000
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#define CAD_QSPI_OFFSET 0x108d2000
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/* SDMMC Setting */
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# if ARM_LINUX_KERNEL_AS_BL33
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#define SOCFPGA_MMC_BLOCK_SIZE U(32768)
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# else
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#define SOCFPGA_MMC_BLOCK_SIZE U(8192)
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# endif
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/* Register Mapping */
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#define SOCFPGA_CCU_NOC_REG_BASE 0x1c000000
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#define SOCFPGA_F2SDRAMMGR_REG_BASE 0x18001000
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#define SOCFPGA_MMC_REG_BASE 0x10808000
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#define SOCFPGA_MEMCTRL_REG_BASE 0x108CC000
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#define SOCFPGA_RSTMGR_REG_BASE 0x10d11000
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#define SOCFPGA_SYSMGR_REG_BASE 0x10d12000
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#define SOCFPGA_PINMUX_REG_BASE 0x10d13000
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#define SOCFPGA_NAND_REG_BASE 0x10B80000
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#define SOCFPGA_ECC_QSPI_REG_BASE 0x10A22000
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#define SOCFPGA_L4_PER_SCR_REG_BASE 0x10d21000
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#define SOCFPGA_L4_SYS_SCR_REG_BASE 0x10d21100
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#define SOCFPGA_SOC2FPGA_SCR_REG_BASE 0x10d21200
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#define SOCFPGA_LWSOC2FPGA_SCR_REG_BASE 0x10d21300
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/* Define maximum page size for NAND flash devices */
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#define PLATFORM_MTD_MAX_PAGE_SIZE U(0x2000)
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/*******************************************************************************
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* Platform memory map related constants
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******************************************************************************/
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#define DRAM_BASE (0x80000000)
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#define DRAM_SIZE (0x80000000)
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#define OCRAM_BASE (0x00000000)
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#define OCRAM_SIZE (0x00080000)
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#define MEM64_BASE (0x0080000000)
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#define MEM64_SIZE (0x0080000000)
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//128MB PSS
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#define PSS_BASE (0x10000000)
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#define PSS_SIZE (0x08000000)
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//64MB MPFE
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#define MPFE_BASE (0x18000000)
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#define MPFE_SIZE (0x04000000)
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//16MB CCU
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#define CCU_BASE (0x1C000000)
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#define CCU_SIZE (0x01000000)
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//1MB GIC
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#define GIC_BASE (0x1D000000)
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#define GIC_SIZE (0x00100000)
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#define BL2_BASE (0x00000000)
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#define BL2_LIMIT (0x0007E000)
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#define BL31_BASE (0x80000000)
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#define BL31_LIMIT (0x82000000)
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/*******************************************************************************
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* UART related constants
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******************************************************************************/
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#define PLAT_UART0_BASE (0x10C02000)
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#define PLAT_UART1_BASE (0x10C02100)
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/*******************************************************************************
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* WDT related constants
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******************************************************************************/
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#define WDT_BASE (0x10D00200)
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/*******************************************************************************
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* GIC related constants
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******************************************************************************/
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#define PLAT_GIC_BASE (0x1D000000)
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#define PLAT_GICC_BASE (PLAT_GIC_BASE + 0x20000)
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#define PLAT_GICD_BASE (PLAT_GIC_BASE + 0x00000)
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#define PLAT_GICR_BASE (PLAT_GIC_BASE + 0x60000)
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#define PLAT_INTEL_SOCFPGA_GICR_BASE PLAT_GICR_BASE
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/*******************************************************************************
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* SDMMC related pointer function
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******************************************************************************/
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#define SDMMC_READ_BLOCKS sdmmc_read_blocks
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#define SDMMC_WRITE_BLOCKS sdmmc_write_blocks
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/*******************************************************************************
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* sysmgr.boot_scratch_cold6 & 7 (64bit) are used to indicate L2 reset
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* is done and HPS should trigger warm reset via RMR_EL3.
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******************************************************************************/
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#define L2_RESET_DONE_REG 0x10D12218
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#endif /* PLAT_SOCFPGA_DEF_H */
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