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chore: rename Makalu to Cortex-A715

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Change-Id: I017c955cb643e2befb6b01e1b5a07c22172b08b9
Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>
This commit is contained in:
Harrison Mutai 2023-05-23 17:28:03 +01:00
parent c0d8ee3861
commit 15889d1332
4 changed files with 40 additions and 40 deletions
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20
include/lib/cpus/aarch64/cortex_makalu.h → include/lib/cpus/aarch64/cortex_a715.h
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@ -1,26 +1,26 @@
/* /*
* Copyright (c) 2021-2022, Arm Limited. All rights reserved. * Copyright (c) 2021-2023, Arm Limited. All rights reserved.
* *
* SPDX-License-Identifier: BSD-3-Clause * SPDX-License-Identifier: BSD-3-Clause
*/ */
#ifndef CORTEX_MAKALU_H #ifndef CORTEX_A715_H
#define CORTEX_MAKALU_H #define CORTEX_A715_H
#define CORTEX_MAKALU_MIDR U(0x410FD4D0) #define CORTEX_A715_MIDR U(0x410FD4D0)
/* Cortex Makalu loop count for CVE-2022-23960 mitigation */ /* Cortex-A715 loop count for CVE-2022-23960 mitigation */
#define CORTEX_MAKALU_BHB_LOOP_COUNT U(38) #define CORTEX_A715_BHB_LOOP_COUNT U(38)
/******************************************************************************* /*******************************************************************************
* CPU Extended Control register specific definitions * CPU Extended Control register specific definitions
******************************************************************************/ ******************************************************************************/
#define CORTEX_MAKALU_CPUECTLR_EL1 S3_0_C15_C1_4 #define CORTEX_A715_CPUECTLR_EL1 S3_0_C15_C1_4
/******************************************************************************* /*******************************************************************************
* CPU Power Control register specific definitions * CPU Power Control register specific definitions
******************************************************************************/ ******************************************************************************/
#define CORTEX_MAKALU_CPUPWRCTLR_EL1 S3_0_C15_C2_7 #define CORTEX_A715_CPUPWRCTLR_EL1 S3_0_C15_C2_7
#define CORTEX_MAKALU_CPUPWRCTLR_EL1_CORE_PWRDN_BIT U(1) #define CORTEX_A715_CPUPWRCTLR_EL1_CORE_PWRDN_BIT U(1)
#endif /* CORTEX_MAKALU_H */ #endif /* CORTEX_A715_H */

56
lib/cpus/aarch64/cortex_a715.S
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@ -1,5 +1,5 @@
/* /*
* Copyright (c) 2021-2022, Arm Limited. All rights reserved. * Copyright (c) 2021-2023, Arm Limited. All rights reserved.
* *
* SPDX-License-Identifier: BSD-3-Clause * SPDX-License-Identifier: BSD-3-Clause
*/ */
@ -7,23 +7,23 @@
#include <arch.h> #include <arch.h>
#include <asm_macros.S> #include <asm_macros.S>
#include <common/bl_common.h> #include <common/bl_common.h>
#include <cortex_makalu.h> #include <cortex_a715.h>
#include <cpu_macros.S> #include <cpu_macros.S>
#include <plat_macros.S> #include <plat_macros.S>
#include "wa_cve_2022_23960_bhb_vector.S" #include "wa_cve_2022_23960_bhb_vector.S"
/* Hardware handled coherency */ /* Hardware handled coherency */
#if HW_ASSISTED_COHERENCY == 0 #if HW_ASSISTED_COHERENCY == 0
#error "Cortex Makalu must be compiled with HW_ASSISTED_COHERENCY enabled" #error "Cortex-A715 must be compiled with HW_ASSISTED_COHERENCY enabled"
#endif #endif
/* 64-bit only core */ /* 64-bit only core */
#if CTX_INCLUDE_AARCH32_REGS == 1 #if CTX_INCLUDE_AARCH32_REGS == 1
#error "Cortex Makalu supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" #error "Cortex-A715 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0"
#endif #endif
#if WORKAROUND_CVE_2022_23960 #if WORKAROUND_CVE_2022_23960
wa_cve_2022_23960_bhb_vector_table CORTEX_MAKALU_BHB_LOOP_COUNT, cortex_makalu wa_cve_2022_23960_bhb_vector_table CORTEX_A715_BHB_LOOP_COUNT, cortex_a715
#endif /* WORKAROUND_CVE_2022_23960 */ #endif /* WORKAROUND_CVE_2022_23960 */
func check_errata_cve_2022_23960 func check_errata_cve_2022_23960
@ -35,44 +35,44 @@ func check_errata_cve_2022_23960
ret ret
endfunc check_errata_cve_2022_23960 endfunc check_errata_cve_2022_23960
func cortex_makalu_reset_func func cortex_a715_reset_func
/* Disable speculative loads */ /* Disable speculative loads */
msr SSBS, xzr msr SSBS, xzr
#if IMAGE_BL31 && WORKAROUND_CVE_2022_23960 #if IMAGE_BL31 && WORKAROUND_CVE_2022_23960
/* /*
* The Cortex Makalu generic vectors are overridden to apply errata * The Cortex-A715 generic vectors are overridden to apply errata
* mitigation on exception entry from lower ELs. * mitigation on exception entry from lower ELs.
*/ */
adr x0, wa_cve_vbar_cortex_makalu adr x0, wa_cve_vbar_cortex_a715
msr vbar_el3, x0 msr vbar_el3, x0
#endif /* IMAGE_BL31 && WORKAROUND_CVE_2022_23960 */ #endif /* IMAGE_BL31 && WORKAROUND_CVE_2022_23960 */
isb isb
ret ret
endfunc cortex_makalu_reset_func endfunc cortex_a715_reset_func
/* ---------------------------------------------------- /* ----------------------------------------------------
* HW will do the cache maintenance while powering down * HW will do the cache maintenance while powering down
* ---------------------------------------------------- * ----------------------------------------------------
*/ */
func cortex_makalu_core_pwr_dwn func cortex_a715_core_pwr_dwn
/* --------------------------------------------------- /* ---------------------------------------------------
* Enable CPU power down bit in power control register * Enable CPU power down bit in power control register
* --------------------------------------------------- * ---------------------------------------------------
*/ */
mrs x0, CORTEX_MAKALU_CPUPWRCTLR_EL1 mrs x0, CORTEX_A715_CPUPWRCTLR_EL1
orr x0, x0, #CORTEX_MAKALU_CPUPWRCTLR_EL1_CORE_PWRDN_BIT orr x0, x0, #CORTEX_A715_CPUPWRCTLR_EL1_CORE_PWRDN_BIT
msr CORTEX_MAKALU_CPUPWRCTLR_EL1, x0 msr CORTEX_A715_CPUPWRCTLR_EL1, x0
isb isb
ret ret
endfunc cortex_makalu_core_pwr_dwn endfunc cortex_a715_core_pwr_dwn
#if REPORT_ERRATA #if REPORT_ERRATA
/* /*
* Errata printing function for Cortex Makalu. Must follow AAPCS. * Errata printing function for Cortex-A715. Must follow AAPCS.
*/ */
func cortex_makalu_errata_report func cortex_a715_errata_report
stp x8, x30, [sp, #-16]! stp x8, x30, [sp, #-16]!
bl cpu_get_rev_var bl cpu_get_rev_var
@ -82,15 +82,15 @@ func cortex_makalu_errata_report
* Report all errata. The revision-variant information is passed to * Report all errata. The revision-variant information is passed to
* checking functions of each errata. * checking functions of each errata.
*/ */
report_errata WORKAROUND_CVE_2022_23960, cortex_makalu, cve_2022_23960 report_errata WORKAROUND_CVE_2022_23960, cortex_a715, cve_2022_23960
ldp x8, x30, [sp], #16 ldp x8, x30, [sp], #16
ret ret
endfunc cortex_makalu_errata_report endfunc cortex_a715_errata_report
#endif #endif
/* --------------------------------------------- /* ---------------------------------------------
* This function provides Cortex Makalu-specific * This function provides Cortex-A715 specific
* register information for crash reporting. * register information for crash reporting.
* It needs to return with x6 pointing to * It needs to return with x6 pointing to
* a list of register names in ascii and * a list of register names in ascii and
@ -98,16 +98,16 @@ endfunc cortex_makalu_errata_report
* reported. * reported.
* --------------------------------------------- * ---------------------------------------------
*/ */
.section .rodata.cortex_makalu_regs, "aS" .section .rodata.cortex_a715_regs, "aS"
cortex_makalu_regs: /* The ascii list of register names to be reported */ cortex_a715_regs: /* The ascii list of register names to be reported */
.asciz "cpuectlr_el1", "" .asciz "cpuectlr_el1", ""
func cortex_makalu_cpu_reg_dump func cortex_a715_cpu_reg_dump
adr x6, cortex_makalu_regs adr x6, cortex_a715_regs
mrs x8, CORTEX_MAKALU_CPUECTLR_EL1 mrs x8, CORTEX_A715_CPUECTLR_EL1
ret ret
endfunc cortex_makalu_cpu_reg_dump endfunc cortex_a715_cpu_reg_dump
declare_cpu_ops cortex_makalu, CORTEX_MAKALU_MIDR, \ declare_cpu_ops cortex_a715, CORTEX_A715_MIDR, \
cortex_makalu_reset_func, \ cortex_a715_reset_func, \
cortex_makalu_core_pwr_dwn cortex_a715_core_pwr_dwn

2
services/std_svc/errata_abi/cpu_errata_info.h
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@ -25,7 +25,7 @@
#include <cortex_a78.h> #include <cortex_a78.h>
#include <cortex_a78_ae.h> #include <cortex_a78_ae.h>
#include <cortex_a78c.h> #include <cortex_a78c.h>
#include <cortex_makalu.h> #include <cortex_a715.h>
#include <cortex_x1.h> #include <cortex_x1.h>
#include <cortex_x2.h> #include <cortex_x2.h>
#include <neoverse_n1.h> #include <neoverse_n1.h>

2
services/std_svc/errata_abi/errata_abi_main.c
View file

@ -406,7 +406,7 @@ struct em_cpu_list cpu_list[] = {
#if CORTEX_A715_H_INC #if CORTEX_A715_H_INC
{ {
.cpu_partnumber = CORTEX_MAKALU_MIDR, .cpu_partnumber = CORTEX_A715_MIDR,
.cpu_errata_list = { .cpu_errata_list = {
[0] = {2701951, 0x00, 0x11, ERRATA_A715_2701951, \ [0] = {2701951, 0x00, 0x11, ERRATA_A715_2701951, \
ERRATA_NON_ARM_INTERCONNECT}, ERRATA_NON_ARM_INTERCONNECT},