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chore(cpus): rearrange the errata and cve in order in Cortex-A710

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Patch sorts the errata IDs in ascending order and the
CVE's in ascending order based on the year and index
for CPU Cortex-A710.

Change-Id: Ie7c2b77879f8fa5abb77204678e09cc759b10278
Signed-off-by: Sona Mathew <sonarebecca.mathew@arm.com>
This commit is contained in:
Sona Mathew 2025-03-19 16:16:27 -05:00 • committed by Arvind Ram Prakash
parent 216d437c0d
commit 10a8e85cba
1 changed files with 9 additions and 9 deletions
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18
lib/cpus/aarch64/cortex_a710.S
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@ -31,13 +31,6 @@
cpu_reset_prologue cortex_a710 cpu_reset_prologue cortex_a710
/* Disable hardware page aggregation. Enables mitigation for `CVE-2024-5660` */
workaround_reset_start cortex_a710, CVE(2024, 5660), WORKAROUND_CVE_2024_5660
sysreg_bit_set CORTEX_A710_CPUECTLR_EL1, BIT(46)
workaround_reset_end cortex_a710, CVE(2024, 5660)
check_erratum_ls cortex_a710, CVE(2024, 5660), CPU_REV(2, 1)
workaround_reset_start cortex_a710, ERRATUM(1987031), ERRATA_A710_1987031 workaround_reset_start cortex_a710, ERRATUM(1987031), ERRATA_A710_1987031
ldr x0,=0x6 ldr x0,=0x6
msr S3_6_c15_c8_0,x0 msr S3_6_c15_c8_0,x0
@ -213,6 +206,10 @@ workaround_reset_end cortex_a710, ERRATUM(2778471)
check_erratum_ls cortex_a710, ERRATUM(2778471), CPU_REV(2, 1) check_erratum_ls cortex_a710, ERRATUM(2778471), CPU_REV(2, 1)
add_erratum_entry cortex_a710, ERRATUM(3701772), ERRATA_A710_3701772
check_erratum_ls cortex_a710, ERRATUM(3701772), CPU_REV(2, 1)
workaround_reset_start cortex_a710, CVE(2022, 23960), WORKAROUND_CVE_2022_23960 workaround_reset_start cortex_a710, CVE(2022, 23960), WORKAROUND_CVE_2022_23960
#if IMAGE_BL31 #if IMAGE_BL31
/* /*
@ -225,9 +222,12 @@ workaround_reset_end cortex_a710, CVE(2022, 23960)
check_erratum_chosen cortex_a710, CVE(2022, 23960), WORKAROUND_CVE_2022_23960 check_erratum_chosen cortex_a710, CVE(2022, 23960), WORKAROUND_CVE_2022_23960
add_erratum_entry cortex_a710, ERRATUM(3701772), ERRATA_A710_3701772 /* Disable hardware page aggregation. Enables mitigation for `CVE-2024-5660` */
workaround_reset_start cortex_a710, CVE(2024, 5660), WORKAROUND_CVE_2024_5660
sysreg_bit_set CORTEX_A710_CPUECTLR_EL1, BIT(46)
workaround_reset_end cortex_a710, CVE(2024, 5660)
check_erratum_ls cortex_a710, ERRATUM(3701772), CPU_REV(2, 1) check_erratum_ls cortex_a710, CVE(2024, 5660), CPU_REV(2, 1)
/* ---------------------------------------------------- /* ----------------------------------------------------
* HW will do the cache maintenance while powering down * HW will do the cache maintenance while powering down