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xlat_tables_v2: add base table section name parameter for spm_mm
Core spm_mm code expects the translation tables are located in the
inner & outer WBWA & shareable memory.
REGISTER_XLAT_CONTEXT2 macro is used to specify the translation
table section in spm_mm.
In the commit 363830df1c
(xlat_tables_v2: merge
REGISTER_XLAT_CONTEXT_{FULL_SPEC,RO_BASE_TABLE}), REGISTER_XLAT_CONTEXT2
macro explicitly specifies the base xlat table goes into .bss by default.
This change affects the existing SynQuacer spm_mm implementation.
plat/socionext/synquacer/include/plat.ld.S linker script intends to
locate ".bss.sp_base_xlat_table" into "sp_xlat_table" section,
but this implementation is no longer available.
This patch adds the base table section name parameter for
REGISTER_XLAT_CONTEXT2 so that platform can specify the
inner & outer WBWA & shareable memory for spm_mm base xlat table.
If PLAT_SP_IMAGE_BASE_XLAT_SECTION_NAME is not defined, base xlat table
goes into .bss by default, the result is same as before.
Change-Id: Ie0e1a235e5bd4288dc376f582d6c44c5df6d31b2
Signed-off-by: Masahisa Kojima <masahisa.kojima@linaro.org>
This commit is contained in:
parent
ec29ce67cf
commit
0922e481e5
4 changed files with 12 additions and 4 deletions
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@ -201,16 +201,20 @@ typedef struct xlat_ctx xlat_ctx_t;
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* _section_name:
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* _section_name:
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* Specify the name of the section where the translation tables have to be
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* Specify the name of the section where the translation tables have to be
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* placed by the linker.
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* placed by the linker.
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*
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* _base_table_section_name:
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* Specify the name of the section where the base translation tables have to
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* be placed by the linker.
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*/
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*/
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#define REGISTER_XLAT_CONTEXT2(_ctx_name, _mmap_count, _xlat_tables_count, \
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#define REGISTER_XLAT_CONTEXT2(_ctx_name, _mmap_count, _xlat_tables_count, \
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_virt_addr_space_size, _phy_addr_space_size, \
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_virt_addr_space_size, _phy_addr_space_size, \
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_xlat_regime, _section_name) \
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_xlat_regime, _section_name, _base_table_section_name) \
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REGISTER_XLAT_CONTEXT_FULL_SPEC(_ctx_name, (_mmap_count), \
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REGISTER_XLAT_CONTEXT_FULL_SPEC(_ctx_name, (_mmap_count), \
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(_xlat_tables_count), \
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(_xlat_tables_count), \
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(_virt_addr_space_size), \
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(_virt_addr_space_size), \
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(_phy_addr_space_size), \
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(_phy_addr_space_size), \
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(_xlat_regime), \
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(_xlat_regime), \
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(_section_name), ".bss" \
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(_section_name), (_base_table_section_name) \
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)
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)
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/******************************************************************************
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/******************************************************************************
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@ -25,7 +25,6 @@ SECTIONS
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*/
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*/
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sp_xlat_table (NOLOAD) : ALIGN(PAGE_SIZE) {
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sp_xlat_table (NOLOAD) : ALIGN(PAGE_SIZE) {
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*(sp_xlat_table)
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*(sp_xlat_table)
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*(.bss.sp_base_xlat_table)
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} >SP_DRAM
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} >SP_DRAM
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}
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}
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@ -144,6 +144,7 @@
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#define PLAT_SP_IMAGE_MMAP_REGIONS 30
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#define PLAT_SP_IMAGE_MMAP_REGIONS 30
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#define PLAT_SP_IMAGE_MAX_XLAT_TABLES 20
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#define PLAT_SP_IMAGE_MAX_XLAT_TABLES 20
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#define PLAT_SP_IMAGE_XLAT_SECTION_NAME "sp_xlat_table"
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#define PLAT_SP_IMAGE_XLAT_SECTION_NAME "sp_xlat_table"
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#define PLAT_SP_IMAGE_BASE_XLAT_SECTION_NAME "sp_xlat_table"
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#define PLAT_SQ_UART1_BASE PLAT_SQ_BOOT_UART_BASE
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#define PLAT_SQ_UART1_BASE PLAT_SQ_BOOT_UART_BASE
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#define PLAT_SQ_UART1_SIZE ULL(0x1000)
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#define PLAT_SQ_UART1_SIZE ULL(0x1000)
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@ -21,13 +21,17 @@
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#ifndef PLAT_SP_IMAGE_XLAT_SECTION_NAME
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#ifndef PLAT_SP_IMAGE_XLAT_SECTION_NAME
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#define PLAT_SP_IMAGE_XLAT_SECTION_NAME "xlat_table"
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#define PLAT_SP_IMAGE_XLAT_SECTION_NAME "xlat_table"
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#endif
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#endif
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#ifndef PLAT_SP_IMAGE_BASE_XLAT_SECTION_NAME
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#define PLAT_SP_IMAGE_BASE_XLAT_SECTION_NAME ".bss"
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#endif
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/* Allocate and initialise the translation context for the secure partitions. */
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/* Allocate and initialise the translation context for the secure partitions. */
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REGISTER_XLAT_CONTEXT2(sp,
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REGISTER_XLAT_CONTEXT2(sp,
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PLAT_SP_IMAGE_MMAP_REGIONS,
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PLAT_SP_IMAGE_MMAP_REGIONS,
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PLAT_SP_IMAGE_MAX_XLAT_TABLES,
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PLAT_SP_IMAGE_MAX_XLAT_TABLES,
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PLAT_VIRT_ADDR_SPACE_SIZE, PLAT_PHY_ADDR_SPACE_SIZE,
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PLAT_VIRT_ADDR_SPACE_SIZE, PLAT_PHY_ADDR_SPACE_SIZE,
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EL1_EL0_REGIME, PLAT_SP_IMAGE_XLAT_SECTION_NAME);
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EL1_EL0_REGIME, PLAT_SP_IMAGE_XLAT_SECTION_NAME,
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PLAT_SP_IMAGE_BASE_XLAT_SECTION_NAME);
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/* Lock used for SP_MEMORY_ATTRIBUTES_GET and SP_MEMORY_ATTRIBUTES_SET */
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/* Lock used for SP_MEMORY_ATTRIBUTES_GET and SP_MEMORY_ATTRIBUTES_SET */
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static spinlock_t mem_attr_smc_lock;
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static spinlock_t mem_attr_smc_lock;
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