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0922e481e5
Core spm_mm code expects the translation tables are located in the
inner & outer WBWA & shareable memory.
REGISTER_XLAT_CONTEXT2 macro is used to specify the translation
table section in spm_mm.
In the commit 363830df1c (xlat_tables_v2: merge
REGISTER_XLAT_CONTEXT_{FULL_SPEC,RO_BASE_TABLE}), REGISTER_XLAT_CONTEXT2
macro explicitly specifies the base xlat table goes into .bss by default.
This change affects the existing SynQuacer spm_mm implementation.
plat/socionext/synquacer/include/plat.ld.S linker script intends to
locate ".bss.sp_base_xlat_table" into "sp_xlat_table" section,
but this implementation is no longer available.
This patch adds the base table section name parameter for
REGISTER_XLAT_CONTEXT2 so that platform can specify the
inner & outer WBWA & shareable memory for spm_mm base xlat table.
If PLAT_SP_IMAGE_BASE_XLAT_SECTION_NAME is not defined, base xlat table
goes into .bss by default, the result is same as before.
Change-Id: Ie0e1a235e5bd4288dc376f582d6c44c5df6d31b2
Signed-off-by: Masahisa Kojima <masahisa.kojima@linaro.org>
31 lines
737 B
ArmAsm
31 lines
737 B
ArmAsm
/*
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* Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef SYNQUACER_PLAT_LD_S__
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#define SYNQUACER_PLAT_LD_S__
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#include <lib/xlat_tables/xlat_tables_defs.h>
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#define SPM_SHIM_EXCEPTIONS_VMA SP_DRAM
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MEMORY {
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SP_DRAM (rw): ORIGIN = PLAT_SQ_SP_PRIV_BASE, LENGTH = PLAT_SQ_SP_PRIV_SIZE
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}
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SECTIONS
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{
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/*
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* Put the page tables in secure DRAM so that the PTW can make cacheable
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* accesses, as the core SPM code expects. (The SRAM on SynQuacer does
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* not support inner shareable WBWA mappings so it is mapped normal
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* non-cacheable)
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*/
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sp_xlat_table (NOLOAD) : ALIGN(PAGE_SIZE) {
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*(sp_xlat_table)
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} >SP_DRAM
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}
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#endif /* SYNQUACER_PLAT_LD_S__ */
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